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    • 2. 发明专利
    • Adhesive tape
    • 胶粘带
    • JP2013163775A
    • 2013-08-22
    • JP2012028150
    • 2012-02-13
    • Nitto Denko Corp日東電工株式会社
    • HABU TSUYOSHIKAMEI KATSUTOSHIIKUSHIMA NOBUSUKEASAI FUMITERU
    • C09J7/02C09J123/18
    • PROBLEM TO BE SOLVED: To provide an adhesive tape excellent in balance of adhesive force with peelability and level difference followability, and manufacturable by co-extrusion molding.SOLUTION: An adhesive tape is provided with an adhesive layer composed of a resin composition including an amorphous propylene-(1-butene) copolymer. When the adhesive tape is applied to an adherend having a step of 30 μm, the tape has ≤650 μm of the width of a portion at which the adhesive tape and the adherend do not contact by floating-up of the tape at the vicinity of a step lower portion, and an adhesive force of the tape adhering to a mirror wafer of a silicon-made semiconductor measured by a method based on JIS Z 0237(2000) (sticking condition of one reciprocating by 2-kg roller, peeling rate of 300 mm/min, and peeling angle of 180°) is ≤2.0 N/20 mm.
    • 要解决的问题:提供粘合力与剥离性和水平差跟随性的平衡优异的粘合带,并且可通过共挤出成型制造。粘合带设置有由包含非晶形的 丙烯 - (1-丁烯)共聚物。 当将粘合带施加到具有30μm的台阶的被粘物上时,胶带的宽度不小于带宽和被粘物不接触的部分的宽度, 通过基于JIS Z 0237(2000)的方法(通过2kg辊的一次往复运动的粘附条件)测量的粘合到硅制半导体的镜面晶片的带的粘合力,剥离速度 300mm / min,剥离角度180°)≤2.0N/ 20mm。
    • 3. 发明专利
    • Wiring circuit board aggregate sheet and method for manufacturing the same
    • 接线电路板集成片及其制造方法
    • JP2011176075A
    • 2011-09-08
    • JP2010038288
    • 2010-02-24
    • Nitto Denko Corp日東電工株式会社
    • YAMAUCHI DAISUKEKAMEI KATSUTOSHITANABE HIROYUKINAITO TOSHIKIISHII ATSUSHI
    • H05K1/02H05K3/00
    • PROBLEM TO BE SOLVED: To provide a wiring circuit board aggregate sheet and a method for manufacturing the wiring circuit board aggregate sheet allowing easy inspection on the propriety of a wiring circuit board by a simple constitution while preventing distortion and/or damage. SOLUTION: An aggregate sheet 1 of suspension substrates with circuits includes a plurality of suspension substrates 2 with circuits, and support sheets 3 formed of metal support boards 5 to support the suspension substrates 2 with circuits in an aligned state. A discrimination mark 4 for discriminating the propriety of the suspension substrate 2 with a circuit by the piercing of a needle 19 is formed to include at least one layer selected from a group composed of a base insulating layer 7, a conductor pattern 8 and a cover insulating layer 9 exposed from a support opening 18 penetrating the thickness direction of the metal support layer 6. COPYRIGHT: (C)2011,JPO&INPIT
    • 要解决的问题:提供一种布线电路板集合片和一种制造布线电路板集合片的方法,其允许通过简单的构造容易地检查布线电路板的适用性,同时防止变形和/或损坏。 解决方案:具有电路的悬置基板的聚集片材1包括具有电路的多个悬置基板2和由金属支撑板5形成的支撑片3,以支撑处于对准状态的电路的悬置基板2。 形成用于通过刺针19识别悬挂基板2与电路的合适性的鉴别标记4,其包括从由基底绝缘层7,导体图案8和盖子 绝缘层9从穿过金属支撑层6的厚度方向的支撑开口18露出。版权所有(C)2011,JPO&INPIT
    • 4. 发明专利
    • Wiring circuit board
    • 接线电路板
    • JP2009206379A
    • 2009-09-10
    • JP2008048907
    • 2008-02-29
    • Nitto Denko Corp日東電工株式会社
    • MOTOGAMI MITSURUKAMEI KATSUTOSHI
    • H05K1/02G11B5/60G11B21/21
    • H05K1/0248G11B5/484G11B5/4853G11B5/486H05K1/0219H05K1/0224H05K1/0245H05K1/0253H05K1/056H05K2201/09236H05K2201/09672H05K2201/0969
    • PROBLEM TO BE SOLVED: To provide a wiring circuit board which can fully prevent occurrence of transmission error of a signal. SOLUTION: A first insulating layer 41 is formed on a suspension body 10, and a wiring pattern W1 for writing is formed on the first insulating layer 41. A second insulating layer 42 is formed on the first insulating layer 41 to cover the wiring pattern W1. On the second insulating layer 42, a wiring pattern W2 for writing is formed above the wiring pattern W1 for writing. On the second insulating layer 42, a ground pattern G1 is also formed at an interval on one side of the wiring pattern W2 for writing. A third insulating layer 43 is formed on the second insulating layer 42 to cover the wiring pattern W2 and the ground pattern G1. An opening 10a is formed in a region of the suspension body 10 below the wiring patterns W1 and W2 for writing. COPYRIGHT: (C)2009,JPO&INPIT
    • 要解决的问题:提供一种可以完全防止信号传输错误发生的布线电路板。 解决方案:第一绝缘层41形成在悬架体10上,并且在第一绝缘层41上形成用于书写的布线图案W.第二绝缘层42形成在第一绝缘层41上以覆盖 布线图案W1。 在第二绝缘层42上,在写入用布线图案W1的上方形成写入用布线图案W2。 在第二绝缘层42上,在布线图案W2的一侧的间隔也形成接地图形G1,以进行写入。 第三绝缘层43形成在第二绝缘层42上以覆盖布线图案W2和接地图案G1。 开口10a形成在用于书写的布线图案W1和W2下方的悬架体10的区域中。 版权所有(C)2009,JPO&INPIT
    • 5. 发明专利
    • Wiring circuit board and production method therefor
    • 接线电路板及其生产方法
    • JP2009026909A
    • 2009-02-05
    • JP2007187803
    • 2007-07-19
    • Nitto Denko Corp日東電工株式会社
    • MOTOGAMI MITSURUKAMEI KATSUTOSHI
    • H05K1/02G11B5/60G11B21/21H05K3/46
    • PROBLEM TO BE SOLVED: To provide a wiring circuit board capable of fully preventing the occurrence of a cross talk between a plurality of conductors, and to provide a production method thereof. SOLUTION: A first insulating layer 41 is formed on a suspension body part 10, and a wiring pattern for writing W1 and a wiring pattern for reading R1 are formed on the first insulating layer 41. The wiring patterns W1, R1 are aligned at a predetermined interval. A second insulating layer 42 is formed on the first insulating layer 41 so as to cover the wiring patterns W1, R1, and a third insulating layer 43 is formed on the second insulating layer 42. On the third insulating layer 43, at a position over the wiring pattern for writing W1, a wiring pattern for writing W2 is formed, and at a position over the wiring pattern for reading R1, a wiring pattern for reading R2 is formed. A fourth insulating layer 44 is formed on the third insulating layer 43 so as to cover the wiring patterns W2, R2. The dielectric constant of the third insulating layer 43 is smaller than either that of the second insulating layer 42 or of the fourth insulating layer 44. COPYRIGHT: (C)2009,JPO&INPIT
    • 要解决的问题:提供能够完全防止多个导体之间发生串扰的布线电路板,并提供其制造方法。 解决方案:第一绝缘层41形成在悬架本体部分10上,并且用于写入W1的布线图案和用于读取R1的布线图形形成在第一绝缘层41上。布线图案W1,R1对齐 以预定间隔。 在第一绝缘层41上形成第二绝缘层42,以覆盖布线图案W1,R1,并且在第二绝缘层42上形成第三绝缘层43.在第三绝缘层43上, 形成用于写入W1的布线图案,写入用布线图案W2,并且在用于读取R1的布线图案上方的位置形成用于读取R2的布线图案。 第四绝缘层44形成在第三绝缘层43上以覆盖布线图案W2,R2。 第三绝缘层43的介电常数小于第二绝缘层42或第四绝缘层44的介电常数。(C)2009,JPO&INPIT
    • 10. 发明专利
    • Wiring circuit substrate and method of manufacturing the same
    • 接线电路及其制造方法
    • JP2011249369A
    • 2011-12-08
    • JP2010117819
    • 2010-05-21
    • Nitto Denko Corp日東電工株式会社
    • KAMEI KATSUTOSHISUGIMOTO YUKITAMURA KIMIHIDE
    • H05K1/02G11B21/21G11B33/12
    • H05K1/118H05K1/147H05K2201/0338Y10T29/49162
    • PROBLEM TO BE SOLVED: To provide a wiring circuit substrate capable of uniformly performing a pre-flux processing on a first inside terminal and a second inside terminal, and stably mounting a preamplifier, and a method of manufacturing the wiring circuit substrate.SOLUTION: A wiring circuit substrate 1 comprises a base insulation layer 12, and a first conductor pattern 13 and a second conductor pattern 14 formed on the base insulation layer 12. In the wiring circuit substrate 1, the first conductor pattern 13 equipped with a first wiring 21 connecting a suspension side terminal 20 provided with a metal plating layer 22 and a first preamplifier side terminal 19 soldered to the preamplifier 7, and the second conductor pattern 14 equipped with a second wiring 18 connecting a soldered substrate side terminal 17 and a second preamplifier side terminal 16 soldered to the preamplifier 7 are formed. After the metal plating layer 22 is formed on the second wiring 18, the first preamplifier side terminal 19 and the second preamplifier side terminal 16 are subjected to a pre-flux processing.
    • 要解决的问题:提供一种能够对第一内部端子和第二内部端子均匀地进行预通量处理并且稳定地安装前置放大器的布线电路基板以及制造布线电路基板的方法。 解决方案:布线电路基板1包括基底绝缘层12和形成在基底绝缘层12上的第一导体图案13和第二导体图案14.在布线电路基板1中,配备有第一导体图案13 连接具有金属镀层22的悬置侧端子20和焊接到前置放大器7的第一前置放大器侧端子19的第一布线21和配备有第二布线18的第二布线18,第二布线18将焊接的基板侧端子17 并且形成焊接到前置放大器7的第二前置放大器侧端子16。 在第二布线18上形成金属镀层22之后,对第一前置放大器侧端子19和第二前置放大器侧端子16进行预通量处理。 版权所有(C)2012,JPO&INPIT