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1. 发明申请

US20170181248A1 INFRARED LIGHT EMITTING DIODE CONTROL CIRCUIT 有权
公开(公告)号：US20170181248A1
公开(公告)日：2017-06-22
申请号：US14971525
申请日：2015-12-16
申请人： Nitin V. Sarangdhar , Victoria C. Moore , Kumar N. Dwarakanath
发明人： Nitin V. Sarangdhar , Victoria C. Moore , Kumar N. Dwarakanath
IPC分类号： H05B37/02 , H05B33/08 , H04N5/33 , G06F21/32 , G08B5/36 , G08B21/18
CPC分类号： H05B37/0227 , G06F21/32 , G06F21/82 , G08B5/36 , G08B21/182 , H04N5/33 , H05B33/0842 , H05B37/0281 , Y02B20/42
摘要： Disclosed in some examples are devices, methods, and machine-readable mediums for reliable control of IR LEDs. In some examples, a microcontroller running firmware controls whether the LED is activated or not by use of a disable signal. The microcontroller enables or disables the operation of the LED based upon a user's proximity to the LED, a watchdog timer, and a confirmation that only trusted software is executing.

2. 发明申请

US20170177846A1 PRIVACY PROTECTED INPUT-OUTPUT PORT CONTROL 有权
公开(公告)号：US20170177846A1
公开(公告)日：2017-06-22
申请号：US14978578
申请日：2015-12-22
申请人： Nitin V. Sarangdhar , Raul Gutierrez
发明人： Nitin V. Sarangdhar , Raul Gutierrez
IPC分类号： G06F21/32 , G06F21/62
CPC分类号： G06F21/32 , G06F21/62
摘要： Systems and techniques for privacy protected input-output port control are described herein. In an example, an indication may be obtained that a protected port is disabled. A set of application attributes stored in a secure memory location may be compared to a set of attested application attributes to create a verification flag. At least one port attribute of the protected port may be obtained based on the verification flag. The protected port may be enabled using the at least one port attribute. Other examples, for controlling an input-output port using computer firmware and trusted execution techniques are further disclosed.

3. 发明申请

US20160180095A1 MEASURED BOOT CAPABILITY 审中-公开
标题翻译：测量引导能力
公开(公告)号：US20160180095A1
公开(公告)日：2016-06-23
申请号：US14581275
申请日：2014-12-23
申请人： Nitin V. Sarangdhar
发明人： Nitin V. Sarangdhar
IPC分类号： G06F21/57
CPC分类号： G06F21/575 , G06F11/1417 , G06F21/57 , G06F21/572
摘要： A package with a processing device and integrated cryptographic firmware is described. The package includes a processing device including a processing module to execute a system management mode and a non-volatile memory storing cryptographic firmware to execute one or more cryptographic functions in the system management mode.
摘要翻译：描述了具有处理设备和集成密码固件的包。该包装包括处理装置，其包括执行系统管理模式的处理模块和存储加密固件的非易失性存储器，以在系统管理模式下执行一个或多个密码功能。

4. 发明申请

US20140053262A1 Secure Display for Secure Transactions 审中-公开
标题翻译：安全交易的安全显示
公开(公告)号：US20140053262A1
公开(公告)日：2014-02-20
申请号：US13994839
申请日：2011-09-30
申请人： Nitin V. Sarangdhar , Satyanarayana Avadhanam , Srikanth Kambhatla
发明人： Nitin V. Sarangdhar , Satyanarayana Avadhanam , Srikanth Kambhatla
IPC分类号： H04L29/06
CPC分类号： H04L63/145 , G06F3/14 , G06F9/451 , G06F21/84 , G09G5/14 , G09G2340/14 , G09G2358/00 , G09G2380/00
摘要： A platform may use a central processing unit to run an operating system. Independently of the operating system, in the central processing unit, a hardware controller, such as a manageability engine, may be used to control which window is on the top of the Z-order and thereby control which window is displayed to the user. As a result, in some embodiments, the hardware controller can prevent an interloper or malware from interjecting an illegitimate window over a legitimate window that the user actually desired to access. In addition, a hardware indicator may be provided to assure the user when an accessed website is legitimate.
摘要翻译：平台可以使用中央处理单元来运行操作系统。与操作系统无关的是，在中央处理单元中，可以使用诸如可管理引擎的硬件控制器来控制哪个窗口位于Z顺序的顶部，从而控制向用户显示哪个窗口。结果，在一些实施例中，硬件控制器可以防止中间件或恶意软件在用户实际希望访问的合法窗口上插入非法窗口。此外，可以提供硬件指示符以确保用户何时访问的网站是合法的。

5. 发明授权

US06463554B1 Bus patcher 失效
标题翻译：巴士补丁
公开(公告)号：US06463554B1
公开(公告)日：2002-10-08
申请号：US09156179
申请日：1998-09-17
申请人： Gerald A Budelman , William A. Hobbs , Stephen J. Peters , Tsvika Kurts , Nitin V. Sarangdhar , Kenneth B. Oliver
发明人： Gerald A Budelman , William A. Hobbs , Stephen J. Peters , Tsvika Kurts , Nitin V. Sarangdhar , Kenneth B. Oliver
IPC分类号： G06F1100
CPC分类号： G06F11/349 , G06F11/004 , G06F11/221 , G06F11/25 , G06F2201/88 , H04L41/0631 , H04L43/0811 , H04L43/12
摘要： An apparatus including a protocol watcher adapted for use with a bus, a state machine adapted to detect known bug signatures on the bus, and a perturber adapted to intervene on the bus to prevent occurrence of bugs having those signatures. A system utilizing such includes a bus, a first agent coupled to the bus, a second agent coupled to the bus for communicating to the first agent according to a bus protocol, and the bus patcher coupled to the bus for monitoring a communication from the second agent to the first agent to identify an event which would cause an error in the apparatus, and for modifying the communication such that the event is avoided. Any of the protocol watcher, state machine, and/or perturber may be programmable.
摘要翻译：一种包括适于与总线一起使用的协议观察器的装置，适用于检测总线上的已知错误签名的状态机，以及适用于在总线上干预以防止发生具有这些签名的错误的扰码器。一种使用这种系统的系统包括总线，耦合到总线的第一代理，耦合到总线的第二代理，用于根据总线协议与第一代理进行通信，并且总线修补器耦合到总线，用于监视来自第二个代理到第一代理以识别将导致设备中的错误的事件，以及用于修改通信，使得避免事件。任何协议监视器，状态机和/或监听器都可以是可编程的。

6. 发明授权

US5937171A Method and apparatus for performing deferred transactions 失效
标题翻译：执行延期交易的方法和装置
公开(公告)号：US5937171A
公开(公告)日：1999-08-10
申请号：US669101
申请日：1996-06-26
申请人： Nitin V. Sarangdhar , Konrad K. Lai , Gurbir Singh , Peter D. MacWilliams
发明人： Nitin V. Sarangdhar , Konrad K. Lai , Gurbir Singh , Peter D. MacWilliams
IPC分类号： G06F13/36 , G06F13/368 , G06F13/37 , G06F13/42 , H04L12/417 , G06F13/14
CPC分类号： G06F13/37 , G06F13/368 , G06F13/4213
摘要： A method and apparatus of performing bus transactions on the bus of the computer system. The present invention includes a method and apparatus for permitting out-of-order replies in a pipelined bus system. The out-of-order responses include the sending of tokens between both the requesting agents and the responding agents in the computer system without the use of dedicated token buses.
摘要翻译：在计算机系统的总线上执行总线事务的方法和装置。本发明包括一种用于允许流水线总线系统中的无序回复的方法和装置。无序响应包括在计算机系统中的请求代理和响应代理之间发送令牌，而不使用专用令牌总线。

7. 发明授权

US5751995A Apparatus and method of maintaining processor ordering in a multiprocessor system which includes one or more processors that execute instructions speculatively 失效
标题翻译：在包括执行指令的一个或多个处理器的多处理器系统中维持处理器排序的装置和方法
公开(公告)号：US5751995A
公开(公告)日：1998-05-12
申请号：US591224
申请日：1996-01-18
申请人： Nitin V. Sarangdhar
发明人： Nitin V. Sarangdhar
IPC分类号： G06F9/38 , G06F9/46 , G06F12/08
CPC分类号： G06F9/52 , G06F12/0831 , G06F9/3834
摘要： In a computer system having a plurality of processors, an apparatus and method for maintaining processor ordering associated with read and write operations of these processors. When data from a producer processor is initially retired, it is stored in a FIFO buffer internal to that processor. If that processor subsequently wishes access to that data, the data is retrieved from and stored back to the FIFO. The data temporarily stored in the FIFO is used to update a main memory shared by the plurality of processors. This update function occurs only after the data has been globally observed in order to guarantee that if any other processor in the system reads data from the main memory, it will obtain an updated version of that data. This ensures that the processor ordering is maintained with respect to the multiple processors residing within the computer system.
摘要翻译：在具有多个处理器的计算机系统中，用于维持与这些处理器的读取和写入操作相关联的处理器排序的装置和方法。当来自生产者处理器的数据最初被退出时，它被存储在该处理器内部的FIFO缓冲器中。如果该处理器随后希望访问该数据，则从数据检索并将其存回FIFO。临时存储在FIFO中的数据用于更新由多个处理器共享的主存储器。该更新功能仅在全局观察数据之后才能发生，以保证系统中任何其他处理器从主存储器读取数据时，将获得该数据的更新版本。这确保了相对于驻留在计算机系统内的多个处理器来维护处理器排序。

8. 发明授权

US5572703A Method and apparatus for snoop stretching using signals that convey snoop results 失效
标题翻译：使用传达窥探结果的信号进行窥探伸展的方法和装置
公开(公告)号：US5572703A
公开(公告)日：1996-11-05
申请号：US203802
申请日：1994-03-01
申请人： Peter MacWilliams , Nitin V. Sarangdhar , Matthew Fisch , Amit Merchant
发明人： Peter MacWilliams , Nitin V. Sarangdhar , Matthew Fisch , Amit Merchant
IPC分类号： G06F12/08 , G06F13/14
CPC分类号： G06F12/0831
摘要： A protocol and related apparatus for snoop stretching in a computer system having at least one requesting agent for issuing bus transaction requests and at least one snooping agent for monitoring transaction requests and issuing bus signals onto an external bus. The bus transactions are timed by a bus clock signal having a plurality of cycles. To indicate snoop stretching, during a first cycle a first snooping agent asserts both a HIT# bus signal and a HITM# bus signal together to indicate that the first snooping agent must delay assertion of valid snoop results for a predetermined snoop period. During a later cycle, to indicate the end of the snoop stretch, the first snooping agent deasserts the assertion of both the HIT# and HITM# signals together and asserts its valid snoop results. The HIT# and HITM# signals alone each represent valid snoop results. If the first snooping agent must continue delaying assertion of valid snoop results, then it reasserts both the HIT# and HITM# bus signals together for the predetermined snoop period. If a second snooping agent is ready to assert its valid snoop results, it will do so while the first snooping agent causes a snoop stretch, and will reassert its valid snoop results up to and including the cycle that the first snooping agent deasserts it snoop stretch and asserts its own valid snoop results.
摘要翻译：一种用于在具有发出总线事务请求的至少一个请求代理的计算机系统中的窥探扩展的协议和相关装置，以及用于监视事务请求和向总线信号发出总线信号的至少一个侦听代理。总线事务由具有多个周期的总线时钟信号定时。为了指示窥探伸展，在第一周期期间，第一窥探代理将HIT＃总线信号和HITM＃总线信号一起断言，以指示第一侦听代理必须在预定的窥探期间延迟有效窥探结果的断言。在稍后的循环中，为了指示窥探伸展的结束，第一次窥探代理将HIT＃和HITM＃信号的断言声明为一致，并断言其有效的窥探结果。 HIT＃和HITM＃信号单独表示有效的窥探结果。如果第一个窥探代理人必须继续延迟有效的窥探结果的断言，则在预定的窥探期间，它将HIT＃和HITM＃总线信号一起重新提供。如果第二个侦听代理程序准备好声明其有效的侦听结果，则会在第一个侦听代理程序导致侦听扩展时执行此操作，并将重新发送其有效的侦听结果，直到并包括第一个侦听代理程序将其忽略的循环snoop stretch 并声明自己有效的窥探结果。

9. 发明授权

US5572702A Method and apparatus for supporting read, write, and invalidation operations to memory which maintain cache consistency 失效
公开(公告)号：US5572702A
公开(公告)日：1996-11-05
申请号：US202790
申请日：1994-02-28
申请人： Nitin V. Sarangdhar , Michael W. Rhodehamel , Amit A. Merchant , Matthew A. Fisch , James M. Brayton
发明人： Nitin V. Sarangdhar , Michael W. Rhodehamel , Amit A. Merchant , Matthew A. Fisch , James M. Brayton
IPC分类号： G06F12/08 , G06F13/16 , G06F13/14
CPC分类号： G06F12/0831 , G06F12/0833 , G06F13/1668
摘要： Requests to memory issued by an agent on a bus are satisfied while maintaining cache consistency. The requesting agent may issue a request to another agent, or the memory unit, by placing the request on the bus. Each agent on the bus snoops the bus to determine whether the issued request can be satisfied by accessing its cache. An agent which can satisfy the request using its cache, i.e., the snooping agent, issues a signal to the requesting agent indicating so. The snooping agent places the cache line which corresponds to the request onto the bus, which is retrieved by the requesting agent. In the event of a read request, the memory unit also retrieves the cache line data from the bus and stores the cache line in main memory. In the event of a write request, the requesting agent transfers write data over the bus along with the request. This write data is retrieved by both the memory unit, which temporarily stores the data, and the snooping agent. Subsequently, the snooping agent transfers the entire cache line over the bus. The memory unit retrieves this cache line, merges it with the write data previously stored, and writes the merged cache line to memory.

10. 发明申请

US20170185434A1 VERSATILE INPUT/OUTPUT DEVICE ACCESS FOR VIRTUAL MACHINES 有权
公开(公告)号：US20170185434A1
公开(公告)日：2017-06-29
申请号：US14757417
申请日：2015-12-23
申请人： Nitin V. Sarangdhar , Ioannis Yannis T. Schoinas , Raul Gutierrez , Ravi Kolagotla
发明人： Nitin V. Sarangdhar , Ioannis Yannis T. Schoinas , Raul Gutierrez , Ravi Kolagotla
IPC分类号： G06F9/455 , G06F13/28 , G06F13/10
CPC分类号： G06F9/45558 , G06F9/4411 , G06F9/5077 , G06F13/102 , G06F13/28 , G06F2009/45579 , G06F2009/45587
摘要： Embodiments are directed to managing access to input/output devices by virtual machines (VMs). A first VM and a second VM are implemented. An I/O device controller driver has a first driver portion in the first VM and a second driver portion in the second VM. The first driver portion includes a configuration engine to configure the I/O device controller with I/O device-VM mappings, where a first I/O device is mapped exclusively to the first VM, and a second I/O device is mapped to at least the second VM. The second VM includes a general processing engine to call for I/O devices via the second driver portion, and in response to a call by the general processing engine for access to the first I/O device the second driver portion is to send an access request to the first driver portion.

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