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1. 发明授权

US06268749B1 Core clock correction in a 2/n mode clocking scheme 有权
标题翻译： 2 / n模式计时方案的核心时钟校正
公开(公告)号：US06268749B1
公开(公告)日：2001-07-31
申请号：US09586396
申请日：2000-05-31
申请人： Matthew A. Fisch , Chakrapani Pathikonda , Javed S. Barkatullah
发明人： Matthew A. Fisch , Chakrapani Pathikonda , Javed S. Barkatullah
IPC分类号： H03L700
CPC分类号： G06F1/12
摘要： A 2/N mode clock generator that generates bus clock signals through the use of bus clock enable signals selecting bus clock pulses that are in phase and out of phase with a core clock signal. The clock generator maintains synchronization between the bus clock signal and the core clock signal so that they are always in a predetermined phase relationship.
摘要翻译： 2 / N模式时钟发生器，其通过使用总线时钟使能信号来产生总线时钟信号，从而选择与核心时钟信号同相和异相的总线时钟脉冲。时钟发生器保持总线时钟信号和核心时钟信号之间的同步，使得它们总是处于预定的相位关系。

2. 发明授权

US06208180B1 Core clock correction in a 2/N mode clocking scheme 有权
标题翻译：核心时钟校正在2 / N模式计时方案
公开(公告)号：US06208180B1
公开(公告)日：2001-03-27
申请号：US09170997
申请日：1998-10-13
申请人： Matthew A. Fisch , Chakrapani Pathikonda , Javed S. Barkatullah
发明人： Matthew A. Fisch , Chakrapani Pathikonda , Javed S. Barkatullah
IPC分类号： H03L700
CPC分类号： G06F1/12
摘要： A 2/N mode dock generator that generates bus clock signals through the use of bus clock enable signals selecting bus clock pulses that are in phase and out of phase with a core clock signal. The clock generator maintains synchronization between the bus clock signal and the core clock signal so that they are always in a predetermined phase relationship.
摘要翻译：通过使用总线时钟使能信号来选择与核心时钟信号同相和异相的总线时钟脉冲来产生总线时钟信号的2 / N模式发射器。时钟发生器保持总线时钟信号和核心时钟信号之间的同步，使得它们总是处于预定的相位关系。

3. 发明授权

US6114887A Apparatus for generating bus clock signals with a 1/N characteristic in a 2/N mode clocking scheme 失效
标题翻译：用于以2 / N模式计时方案产生具有1 / N特性的总线时钟信号的装置
公开(公告)号：US6114887A
公开(公告)日：2000-09-05
申请号：US971939
申请日：1997-11-17
申请人： Chakrapani Pathikonda , Matthew A. Fisch , Michael W. Rhodehamel
发明人： Chakrapani Pathikonda , Matthew A. Fisch , Michael W. Rhodehamel
IPC分类号： G06F1/12 , H03K1/04
CPC分类号： G06F1/12
摘要： A 2/N mode clock generator that generates bus clock signals through the use of bus clock enable signals selecting bus clock pulses that are in phase and out of phase with a core clock signal. The clock generator maintains synchronization between the bus clock signal and the core clock signal so that they are always in a predetermined phase relationship.
摘要翻译： 2 / N模式时钟发生器，其通过使用总线时钟使能信号来产生总线时钟信号，从而选择与核心时钟信号同相和异相的总线时钟脉冲。时钟发生器维持总线时钟信号和核心时钟信号之间的同步，使得它们总是处于预定的相位关系。

4. 发明授权

US6006299A Apparatus and method for caching lock conditions in a multi-processor system 失效
标题翻译：用于在多处理器系统中缓存锁定条件的装置和方法
公开(公告)号：US6006299A
公开(公告)日：1999-12-21
申请号：US204592
申请日：1994-03-01
申请人： Wen-Hann Wang , Konrad K. Lai , Gurbir Singh , Mandar S. Joshi , Nitin V. Sarangdhar , Matthew A. Fisch
发明人： Wen-Hann Wang , Konrad K. Lai , Gurbir Singh , Mandar S. Joshi , Nitin V. Sarangdhar , Matthew A. Fisch
IPC分类号： G06F9/46 , G06F13/08
CPC分类号： G06F9/52
摘要： In a computer system, an apparatus for handling lock conditions wherein a first instruction executed by a first processor processes data that is common to a second processor while the second processor is locked from simultaneously executing a second instruction that also processes this same data. A lock bit is set when the first processor begins execution of the first instruction. Thereupon, the second processor is prevented from executing its instruction until the first processor has completed its processing of the shared data. Hence, the second processor queues its request in a buffer. The lock bit is cleared after the first processor has completed execution of its instruction. The first processor then checks the buffer for any outstanding requests. In response to the second processor's queued request, the first processor transmits a signal to the second processor indicating that the data is now not locked.
摘要翻译：在计算机系统中，一种用于处理锁定条件的装置，其中由第一处理器执行的第一指令在第二处理器被锁定时处理与第二处理器相同的数据，同时执行也处理该相同数据的第二指令。当第一个处理器开始执行第一个指令时，锁定位被置位。于是，第二处理器被阻止执行其指令，直到第一处理器完成对共享数据的处理。因此，第二处理器将其请求排队在缓冲器中。在第一个处理器完成其指令执行后，锁定位被清零。然后，第一个处理器检查缓冲区是否有任何未完成的请求。响应于第二处理器的排队请求，第一处理器向第二处理器发送指示数据现在不被锁定的信号。

5. 发明授权

US5802132A Apparatus for generating bus clock signals with a 1/N characteristic in a 2/N mode clocking scheme 失效
公开(公告)号：US5802132A
公开(公告)日：1998-09-01
申请号：US708928
申请日：1996-09-06
申请人： Chakrapani Pathikonda , Matthew A. Fisch , Michael W. Rhodehamel
发明人： Chakrapani Pathikonda , Matthew A. Fisch , Michael W. Rhodehamel
IPC分类号： G06F1/12 , H03K21/00
CPC分类号： G06F1/12
摘要： A 2/N mode clock generator that generates bus clock signals through the use of bus clock enable signals selecting bus clock pulses that are in phase and out of phase with a core clock signal. The clock generator maintains synchronization between the bus clock signal and the core clock signal so that they are always in a predetermined phase relationship.

6. 发明授权

US5774700A Method and apparatus for determining the timing of snoop windows in a pipelined bus 失效
标题翻译：用于确定流水线总线中的窥探窗口的定时的方法和装置
公开(公告)号：US5774700A
公开(公告)日：1998-06-30
申请号：US425370
申请日：1995-04-20
申请人： Matthew A. Fisch , Nitin V. Sarangdhar
发明人： Matthew A. Fisch , Nitin V. Sarangdhar
IPC分类号： G06F12/08 , G06F1/04
CPC分类号： G06F12/0831
摘要： A method and apparatus for determining the timing of snoop windows in a pipelined bus includes a snoop timer, a snoop counter, and snoop resolution logic. The snoop timer indicates the number of clocks until the next snoop window. The snoop counter keeps track of the number of snoop windows currently being tracked by the apparatus and is updated by the snoop resolution logic. In one embodiment, the snoop resolution logic updates the snoop counter when a snoop event occurs on the bus. In one embodiment, the apparatus also includes snoop drive logic which drives snoop result signals onto the bus during snoop windows.
摘要翻译：用于确定流水线总线中的窥探窗口的定时的方法和装置包括窥探定时器，窥探计数器和窥探分辨率逻辑。监听定时器指示下一个监听窗口之前的时钟数。窥探计数器跟踪当前由设备跟踪的窥探窗口的数量，并由窥探分辨率逻辑更新。在一个实施例中，当在总线上发生窥探事件时，窥探分辨率逻辑更新窥探计数器。在一个实施例中，该装置还包括窥探驱动逻辑，其在窥探窗口期间将窥探结果信号驱动到总线上。

7. 发明授权

US5764934A Processor subsystem for use with a universal computer architecture 失效
标题翻译：处理器子系统，用于通用计算机体系结构
公开(公告)号：US5764934A
公开(公告)日：1998-06-09
申请号：US675854
申请日：1996-07-03
申请人： Matthew A. Fisch , James E. Jacobson, Jr. , Michael W. Rhodehamel
发明人： Matthew A. Fisch , James E. Jacobson, Jr. , Michael W. Rhodehamel
IPC分类号： G06F13/36 , G06F13/38 , G06F13/40 , G06F13/42 , G06F15/76
CPC分类号： G06F13/4027
摘要： A processor subsystem includes a processor and a bus bridge conversion device for insertion into a slot of a host computer system. The processor operates according to a signaling protocol which is different than the signaling protocol of the computer system bus. The bus conversion device converts the signaling protocol of the system bus to the signaling protocol of the processor, and vice-versa. The bus conversion device includes logic for bus arbitration conversion, bus lock conversion, and cache coherency control. Logic is also included that converts incoming and outgoing requests so that the card may properly transact with other agents coupled to the bus.
摘要翻译：处理器子系统包括用于插入到主计算机系统的时隙中的处理器和总线桥转换装置。处理器根据与计算机系统总线的信令协议不同的信令协议进行操作。总线转换装置将系统总线的信令协议转换为处理器的信令协议，反之亦然。总线转换装置包括用于总线仲裁转换，总线锁转换和高速缓存一致性控制的逻辑。还包括逻辑，可转换传入和传出的请求，以便卡可以与耦合到总线的其他代理进行正确的交互。

8. 发明授权

US5581782A Computer system with distributed bus arbitration scheme for symmetric and priority agents 失效
标题翻译：具有分布式总线仲裁方案的计算机系统，用于对称和优先代理
公开(公告)号：US5581782A
公开(公告)日：1996-12-03
申请号：US538597
申请日：1995-10-03
申请人： Nitin V. Sarangdhar , Konrad K. Lai , Gurbir Singh , Michael W. Rhodehamel , Matthew A. Fisch
发明人： Nitin V. Sarangdhar , Konrad K. Lai , Gurbir Singh , Michael W. Rhodehamel , Matthew A. Fisch
IPC分类号： G06F13/36 , G06F13/364 , H04L12/403 , G06F13/18
CPC分类号： G06F13/364 , G06F13/36 , H04L12/403 , H04L12/4015
摘要： A system and method for providing a high performance symmetric arbitration protocol that includes support for priority agents. The bus arbitration protocol supports two classes of bus agents: symmetric agents and priority agents. The symmetric agents support fair, distributed arbitration using a round-robin algorithm. Each symmetric agent has a unique Agent ID assigned at reset. The algorithm arranges the symmetric agents in a circular order of priority. Each symmetric agent also maintains a bus ownership state of busy or idle and a Rotating ID that reflects the symmetric agent with the lowest priority in the next arbitration event. On an arbitration event, the symmetric agent with the highest priority becomes the symmetric owner. However, the symmetric owner is not necessarily the overall bus owner (i.e., a priority agent may be the overall bus owner). The symmetric owner is allowed to take ownership of the bus and issue a transaction on the bus provided no other action of higher priority is preventing the use of the bus. A symmetric owner can maintain ownership without re-arbitrating if the transaction is either a bus-locked or a burst access transaction. The priority agent(s) has higher priority than the symmetric owner. Once the priority agent arbitrates for the bus, it prevents the symmetric owner from issuing any new transactions on the bus unless the new transaction is part of an ongoing bus-locked operation.
摘要翻译：一种用于提供包括对优先代理的支持的高性能对称仲裁协议的系统和方法。总线仲裁协议支持两类总线代理：对称代理和优先代理。对称代理使用循环算法支持公平的分布式仲裁。每个对称代理都具有在复位时分配的唯一代理ID。该算法按照循环顺序排列对称代理。每个对称代理还维持忙或空闲的总线所有权状态以及在下一个仲裁事件中反映具有最低优先级的对称代理的旋转ID。在仲裁事件中，优先级最高的对称代理成为对称所有者。然而，对称所有者不一定是总线总线所有者（即，优先代理可以是总线总线所有者）。允许对称所有者获得公共汽车的所有权，并在公共汽车上发出交易，只要没有更高优先级的其他动作阻止使用公共汽车。如果事务是总线锁定或突发访问事务，对称所有者可以维护所有权而不重新仲裁。优先级代理的优先级高于对称所有者。一旦优先级代理对总线进行仲裁，就可以防止对称所有者在总线上发出任何新的事务，除非新的事务是持续的总线锁定操作的一部分。

9. 发明授权

US5515516A Initialization mechanism for symmetric arbitration agents 失效
公开(公告)号：US5515516A
公开(公告)日：1996-05-07
申请号：US205035
申请日：1994-03-01
申请人： Matthew A. Fisch , Michael W. Rhodehamel , Nitin Sarangdhar
发明人： Matthew A. Fisch , Michael W. Rhodehamel , Nitin Sarangdhar
IPC分类号： G06F15/00 , G06F9/02 , G06F13/36 , G06F13/362 , G06F13/374 , G06F15/16
CPC分类号： G06F13/362 , G06F13/374
摘要： An initialization mechanism for symmetric arbitration agents ensures that multiple agents on a bus are each initialized with a different arbitration counter value. The arbitration counter of each bus agent is used to keep track of which agent was the last or current owner of the bus and which agent will be the next owner of the bus. All bus agents agree on which agent will be the priority agent at system reset and thus be allowed first ownership of the bus. Each agent's arbitration counter is initialized according to each agent's own agent identification. The arbitration pins of the bus agents are interconnected such that each agent determines for itself a unique agent identification based on which pin of its arbitration pins is active at system reset and the maximum number of bus agents allowed on the bus. After determining its agent identification, each bus agent initializes its arbitration counter such that every agent agrees which agent is the priority agent. Each agent performs this initialization based on its agent identification, the identity of the priority agent, and the maximum number of agents allowed on the bus.

10. 发明授权

US5572702A Method and apparatus for supporting read, write, and invalidation operations to memory which maintain cache consistency 失效
公开(公告)号：US5572702A
公开(公告)日：1996-11-05
申请号：US202790
申请日：1994-02-28
申请人： Nitin V. Sarangdhar , Michael W. Rhodehamel , Amit A. Merchant , Matthew A. Fisch , James M. Brayton
发明人： Nitin V. Sarangdhar , Michael W. Rhodehamel , Amit A. Merchant , Matthew A. Fisch , James M. Brayton
IPC分类号： G06F12/08 , G06F13/16 , G06F13/14
CPC分类号： G06F12/0831 , G06F12/0833 , G06F13/1668
摘要： Requests to memory issued by an agent on a bus are satisfied while maintaining cache consistency. The requesting agent may issue a request to another agent, or the memory unit, by placing the request on the bus. Each agent on the bus snoops the bus to determine whether the issued request can be satisfied by accessing its cache. An agent which can satisfy the request using its cache, i.e., the snooping agent, issues a signal to the requesting agent indicating so. The snooping agent places the cache line which corresponds to the request onto the bus, which is retrieved by the requesting agent. In the event of a read request, the memory unit also retrieves the cache line data from the bus and stores the cache line in main memory. In the event of a write request, the requesting agent transfers write data over the bus along with the request. This write data is retrieved by both the memory unit, which temporarily stores the data, and the snooping agent. Subsequently, the snooping agent transfers the entire cache line over the bus. The memory unit retrieves this cache line, merges it with the write data previously stored, and writes the merged cache line to memory.

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