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1. 发明申请

US20170185434A1 VERSATILE INPUT/OUTPUT DEVICE ACCESS FOR VIRTUAL MACHINES 有权
公开(公告)号：US20170185434A1
公开(公告)日：2017-06-29
申请号：US14757417
申请日：2015-12-23
申请人： Nitin V. Sarangdhar , Ioannis Yannis T. Schoinas , Raul Gutierrez , Ravi Kolagotla
发明人： Nitin V. Sarangdhar , Ioannis Yannis T. Schoinas , Raul Gutierrez , Ravi Kolagotla
IPC分类号： G06F9/455 , G06F13/28 , G06F13/10
CPC分类号： G06F9/45558 , G06F9/4411 , G06F9/5077 , G06F13/102 , G06F13/28 , G06F2009/45579 , G06F2009/45587
摘要： Embodiments are directed to managing access to input/output devices by virtual machines (VMs). A first VM and a second VM are implemented. An I/O device controller driver has a first driver portion in the first VM and a second driver portion in the second VM. The first driver portion includes a configuration engine to configure the I/O device controller with I/O device-VM mappings, where a first I/O device is mapped exclusively to the first VM, and a second I/O device is mapped to at least the second VM. The second VM includes a general processing engine to call for I/O devices via the second driver portion, and in response to a call by the general processing engine for access to the first I/O device the second driver portion is to send an access request to the first driver portion.

2. 发明申请

US20060101230A1 Maintaining even and odd array pointers to extreme values by searching and comparing multiple elements concurrently where a pointer is adjusted after processing to account for a number of pipeline stages 审中-公开
标题翻译：通过在处理之后调整指针进行调整以同时考虑多个流水线阶段，同时搜索和比较多个元素，将均匀和奇数数组指针维持在极端值
公开(公告)号：US20060101230A1
公开(公告)日：2006-05-11
申请号：US11231397
申请日：2005-09-20
申请人： Charles Roth , Ravi Kolagotla , Jose Fridman
发明人： Charles Roth , Ravi Kolagotla , Jose Fridman
IPC分类号： G06F15/00
CPC分类号： G06F7/22 , G06F9/30021 , G06F9/30036
摘要： In one embodiment, a programmable processor searches an array of N data elements in response to N/M machine instructions, where the processor has a pipeline configured to process M data elements in parallel. In response to the machine instructions, a control unit directs the pipeline to retrieve M data elements from the array of elements in a single fetch cycle, concurrently compare the data elements to M current extreme values, and update the current extreme values, as well as M references to the current extreme values, based on the comparisons.
摘要翻译：在一个实施例中，可编程处理器响应于N / M机器指令来搜索N个数据元素的阵列，其中处理器具有被配置为并行处理M个数据元素的流水线。响应于机器指令，控制单元引导流水线在单次提取循环中从元素阵列中检索M个数据元素，同时将数据元素与M个当前极值进行比较，并更新当前的极值，以及基于比较，M引用当前的极值。

3. 发明申请

US20050228951A1 Virtualized load buffers 有权
标题翻译：虚拟化负载缓冲区
公开(公告)号：US20050228951A1
公开(公告)日：2005-10-13
申请号：US10821549
申请日：2004-04-08
申请人： Ramesh Peri , John Fernando , Ravi Kolagotla
发明人： Ramesh Peri , John Fernando , Ravi Kolagotla
IPC分类号： G06F12/00 , G06F12/08
CPC分类号： G06F12/0893
摘要： A memory addressing technique using load buffers-to improve data access performance. More particularly, embodiments of the invention relate to a method and apparatus to improve cache access performance in a computer system by exploiting addressing mode information within an instruction accessing a cache memory or other memory device within the computer system.
摘要翻译：使用加载缓冲区的存储器寻址技术来提高数据访问性能。更具体地，本发明的实施例涉及通过利用访问计算机系统内的高速缓冲存储器或其他存储器设备的指令内的寻址模式信息来改善计算机系统中的高速缓存访问性能的方法和装置。

4. 发明授权

US06948056B1 Maintaining even and odd array pointers to extreme values by searching and comparing multiple elements concurrently where a pointer is adjusted after processing to account for a number of pipeline stages 有权
标题翻译：通过在处理之后调整指针进行调整以同时考虑多个流水线阶段，同时搜索和比较多个元素，将均匀和奇数数组指针维持在极端值
公开(公告)号：US06948056B1
公开(公告)日：2005-09-20
申请号：US09675066
申请日：2000-09-28
申请人： Charles P. Roth , Ravi Kolagotla , Jose Fridman
发明人： Charles P. Roth , Ravi Kolagotla , Jose Fridman
IPC分类号： G06F9/38 , G06F7/02 , G06F7/22 , G06F9/30 , G06F9/302 , G06F15/80
CPC分类号： G06F7/22 , G06F9/30021 , G06F9/30036
摘要： In one embodiment, a programmable processor searches an array of N data elements in response to N/M machine instructions, where the processor has a pipeline configured to process M data elements in parallel. In response to the machine instructions, a control unit directs the pipeline to retrieve M data elements from the array of elements in a single fetch cycle, concurrently compare the data elements to M current extreme values, and update the current extreme values, as well as M references to the current extreme values, based on the comparisons.
摘要翻译：在一个实施例中，可编程处理器响应于N / M机器指令来搜索N个数据元素的阵列，其中处理器具有被配置为并行处理M个数据元素的流水线。响应于机器指令，控制单元引导流水线在单次提取循环中从元素阵列中检索M个数据元素，同时将数据元素与M个当前极值进行比较，并更新当前的极值，以及基于比较，M引用当前的极值。

5. 发明授权

US06760830B2 Modulo addressing 有权
标题翻译：模寻址
公开(公告)号：US06760830B2
公开(公告)日：2004-07-06
申请号：US09751507
申请日：2000-12-29
申请人： Ryo Inoue , Ravi Kolagotla , Raghavan Sudhakar
发明人： Ryo Inoue , Ravi Kolagotla , Raghavan Sudhakar
IPC分类号： G06F1200
CPC分类号： G06F5/10 , G06F7/72 , G06F9/3552 , G06F2205/106
摘要： In one embodiment, a modulo addressing unit for a processor is described that includes a plurality of adders to generate an uncorrected target module address and at least one corrected target module address in parallel. A comparator selects one of the target module addresses a function of a base address (b) for a circular buffer, a length (L) of the circular buffer, an index address (I) and a modifier value (M). In one embodiment the comparator selects a first corrected target module address when I+M =B+L and an uncorrected module address when B
摘要翻译：在一个实施例中，描述了一种用于处理器的模寻址单元，其包括多个加法器，以并行生成未校正的目标模地址和至少一个校正的目标模数地址。比较器选择目标模数地址中的一个作为循环缓冲器的基址（b），循环缓冲器的长度（L），索引地址（I）和修改值（M）的函数。在一个实施例中，当I + M = B + L时第二校正目标模地址和当B <= I + M

6. 发明授权

US06760800B1 Event vector table override 有权
标题翻译：事件向量表覆盖
公开(公告)号：US06760800B1
公开(公告)日：2004-07-06
申请号：US09672289
申请日：2000-09-28
申请人： Charles P. Roth , Ravi Kolagotla , Jose Fridman
发明人： Charles P. Roth , Ravi Kolagotla , Jose Fridman
IPC分类号： G06F1324
CPC分类号： G06F9/4812 , G06F9/4486
摘要： In an embodiment, a system may include a processor that handles a number of events. These events may include general purpose interrupts (GPIs) assigned to particular devices in the system. Addresses for event service routines appropriate for particular events may be stored in an event vector table (EVT). In a system with a number of devices that utilize the processor's resources, some interrupts may be overloaded, that is, assigned to more than one device. If an overloaded interrupt occurs, the processor may override the EVT entry and select an address supplied by a system controller at a set of reset vector pins.
摘要翻译：在一个实施例中，系统可以包括处理多个事件的处理器。这些事件可能包括分配给系统中特定设备的通用中断（GPI）。适用于特定事件的事件服务例程的地址可以存储在事件向量表（EVT）中。在具有利用处理器的资源的多个设备的系统中，一些中断可能被重载，也就是分配给多个设备。如果发生过载中断，则处理器可以覆盖EVT条目，并在一组复位向量引脚上选择由系统控制器提供的地址。

7. 发明申请

US20070136564A1 Method and apparatus to save and restore context using scan cells 审中-公开
标题翻译：使用扫描单元保存和恢复上下文的方法和装置
公开(公告)号：US20070136564A1
公开(公告)日：2007-06-14
申请号：US11302742
申请日：2005-12-14
申请人： Sankaran Menon , John Fernando , Ravi Kolagotla
发明人： Sankaran Menon , John Fernando , Ravi Kolagotla
IPC分类号： G06F9/44
CPC分类号： G11C29/32 , G11C2029/3202
摘要： Apparatus including a save path to connect an output of a first latch of a first save/restore cell of a save/restore chain to an input of a second latch of the first save/restore cell, a restore path to connect an output from the second latch to an input of the first latch, and a scan path to connect the output of the second latch to an input of a second save/restore cell of the save/restore chain. The apparatus is useful for fast context switching.
摘要翻译：一种装置，包括将保存/恢复链的第一保存/恢复单元的第一锁存器的输出连接到第一存储/恢复单元的第二锁存器的输入的保存路径，连接来自第一存储/恢复单元的输出的恢复路径第二锁存器到第一锁存器的输入端，以及扫描路径，用于将第二锁存器的输出连接到保存/恢复链路的第二保存/恢复单元的输入。该装置对于快速上下文切换是有用的。

8. 发明申请

US20060143554A1 Scalable traceback technique for channel decoder 有权
公开(公告)号：US20060143554A1
公开(公告)日：2006-06-29
申请号：US11022212
申请日：2004-12-23
申请人： Raghavan Sudhakar , Ravi Kolagotla
发明人： Raghavan Sudhakar , Ravi Kolagotla
IPC分类号： H03M13/03
CPC分类号： H03M13/4169 , H03M13/4107 , H03M13/6502
摘要： Apparatus, system, and method for scalable traceback techniques for channel decoding are described.

9. 发明授权

US06986026B2 Single-step processing and selecting debugging modes 有权
标题翻译：单步处理和选择调试模式
公开(公告)号：US06986026B2
公开(公告)日：2006-01-10
申请号：US09738649
申请日：2000-12-15
申请人： Charles P. Roth , Ravi P. Singh , Tien Dingh , Ravi Kolagotla , Marc Hoffman , Russell Rivin
发明人： Charles P. Roth , Ravi P. Singh , Tien Dingh , Ravi Kolagotla , Marc Hoffman , Russell Rivin
IPC分类号： G06F9/00
CPC分类号： G06F11/3664 , G06F11/3648
摘要： In one embodiment, techniques are disclosed for causing a programmable processor to process one instruction at a time. Single-step debugging may be performed by taking an exception after each instruction or by invoking emulation mode after each instruction. The particular single-step debugging technique may be based upon state of control bits, or may be based upon the processor's current mode of operation, or both.
摘要翻译：在一个实施例中，公开了用于使可编程处理器一次处理一个指令的技术。单步调试可以通过在每个指令之后执行异常或在每条指令后调用仿真模式来执行。特定的单步调试技术可以基于控制位的状态，或者可以基于处理器的当前操作模式，或两者。

10. 发明授权

US06820102B2 DSP unit for multi-level global accumulation 有权
标题翻译： DSP单元用于多级全局积累
公开(公告)号：US06820102B2
公开(公告)日：2004-11-16
申请号：US10630517
申请日：2003-07-29
申请人： Bradley C. Aldrich , Ravi Kolagotla
发明人： Bradley C. Aldrich , Ravi Kolagotla
IPC分类号： G06F1500
CPC分类号： G06F7/544 , G06F2207/5442
摘要： In one embodiment, a digital-signal processor (DSP) is described for multi-level global accumulation. The DSP includes a plurality of absolute difference determinators in a first stage. The absolute difference determinators may include arithmetic logic-units (ALUS) in combination with multiplexers. By using multiple absolute difference determinators, the throughput of the DSP is increased. An existing multiplier may be reconfigured into an adder tree to process the absolute difference results obtained in the first stage. To further increase, throughput, multiple DSPs with multiple absolute difference determinators may be operated in parallel.
摘要翻译：在一个实施例中，描述了用于多级全局累积的数字信号处理器（DSP）。 DSP在第一级中包括多个绝对差分确定器。绝对差分确定器可以包括与多路复用器组合的算术逻辑单元（ALUS）。通过使用多个绝对差分确定器，DSP的吞吐量增加。可以将现有的乘法器重新配置为加法器树，以处理在第一级中获得的绝对差分结果。为了进一步提高吞吐量，可以并行地运行具有多个绝对差分确定器的多个DSP。

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