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1. 发明授权

US6128208A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US6128208A
公开(公告)日：2000-10-03
申请号：US401185
申请日：1999-09-23
申请人： Niichi Itoh , Yasunobu Nakase , Tetsuya Watanabe , Chikayoshi Morishima
发明人： Niichi Itoh , Yasunobu Nakase , Tetsuya Watanabe , Chikayoshi Morishima
IPC分类号： H01L27/10 , H01L21/8242 , H01L27/108 , G11C5/02
CPC分类号： H01L27/10844 , H01L27/10897
摘要： Provided is a semiconductor memory having a layout structure in which a memory cell has excellent patterning controllability. A pattern of element components (active regions 10 to 15 and 21 to 23 and polysilicon regions 31 to 42) of a memory cell for one memory cell unit of a memory cell array region 1 is identical to that of a dummy cell of a peripheral dummy cell region 3, and both patterns present a line symmetrical relationship with respect to a boundary line BC1. In addition, a pattern of the memory cell for one memory cell unit of the memory cell array region 1 is identical to that of a dummy cell of a power wiring region 2, and both patterns present a line symmetrical relationship with respect to a boundary line BC2.
摘要翻译：提供一种具有布局结构的半导体存储器，其中存储单元具有优异的图案化可控性。存储单元阵列区域1的一个存储单元单元的存储单元的元件部件（有源区域10至15和21至23以及多晶硅区域31至42）的图案与外围虚拟元件的虚设单元相同单元区域3，并且两个图案相对于边界线BC1呈现线对称关系。此外，存储单元阵列区域1的一个存储单元单元的存储单元的图案与电力布线区域2的虚设单元的图案相同，并且两个图案相对于边界线呈现线对称关系 BC2。

2. 发明授权

US06201758B1 Semiconductor memory device permitting time required for writing data to be reduced 失效
标题翻译：允许减少写入数据所需的时间的半导体存储器件
公开(公告)号：US06201758B1
公开(公告)日：2001-03-13
申请号：US09499044
申请日：2000-02-07
申请人： Chikayoshi Morishima , Yasunobu Nakase , Tetsuya Watanabe , Niichi Itoh
发明人： Chikayoshi Morishima , Yasunobu Nakase , Tetsuya Watanabe , Niichi Itoh
IPC分类号： G11C800
CPC分类号： G11C11/419
摘要： A precharge circuit and a bit line load circuit are provided to a read bit line pair. The bit line load circuit continuously supplies a prescribed current to a read bit line. When data is written to one of memory cells selected in common by one read word line, the level of each read bit line will not be lowered to the level of the ground potential by the bit line load circuit if a read word line is activated, and therefore the loads of both discharge and charge operations by transistors in the memory cell are reduced.
摘要翻译：向读位线对提供预充电电路和位线负载电路。位线负载电路将规定的电流连续地提供给读位线。当将数据写入一个读取字线共同选择的存储器单元之一时，如果读取的字线被激活，则每个读取位线的电平将不会被位线负载电路降低到地电位的电平，因此减小存储单元中的晶体管的放电和充电操作的负载。

3. 发明授权

US06327166B1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US06327166B1
公开(公告)日：2001-12-04
申请号：US09651322
申请日：2000-08-31
申请人： Niichi Itoh , Yasunobu Nakase , Tetsuya Watanabe , Chikayoshi Morishima
发明人： Niichi Itoh , Yasunobu Nakase , Tetsuya Watanabe , Chikayoshi Morishima
IPC分类号： G11C502
CPC分类号： H01L27/10844 , H01L27/10897
摘要： Provided is a semiconductor memory having a layout structure in which a memory cell has excellent patterning controllability. A pattern of element components (active regions 10 to 15 and 21 to 23 and polysilicon regions 31 to 42) of a memory cell for one memory cell unit of a memory cell array region 1 is identical to that of a dummy cell of a peripheral dummy cell region 3, and both patterns present a line symmetrical relationship with respect to a boundary line BC1. In addition, a pattern of the memory cell for one memory cell unit of the memory cell array region 1 is identical to that of a dummy cell of a power wiring region 2, and both patterns present a line symmetrical relationship with respect to a boundary line BC2.
摘要翻译：提供一种具有布局结构的半导体存储器，其中存储单元具有优异的图案化可控性。存储单元阵列区域1的一个存储单元单元的存储单元的元件部件（有源区域10至15和21至23以及多晶硅区域31至42）的图案与外围虚拟元件的虚设单元相同单元区域3，并且两个图案相对于边界线BC1呈现线对称关系。此外，存储单元阵列区域1的一个存储单元单元的存储单元的图案与电力布线区域2的虚设单元的图案相同，并且两个图案相对于边界线呈现线对称关系 BC2。

4. 发明授权

US06577021B2 Static-type semiconductor memory device 失效
公开(公告)号：US06577021B2
公开(公告)日：2003-06-10
申请号：US10096728
申请日：2002-03-14
申请人： Chikayoshi Morishima , Yoshinori Okumura , Takashi Kuroi
发明人： Chikayoshi Morishima , Yoshinori Okumura , Takashi Kuroi
IPC分类号： H01L2711
CPC分类号： H01L27/1104 , Y10S257/904
摘要： An SRAM of the present invention comprises a plurality of memory cells, which are formed over a plurality of wells, which store data and which do not have a well contact region for fixing the potential of the wells, and a plurality of well contact cells for fixing the potential of the wells that are formed over the plurality of wells so as to adjoin the memory cells, wherein the areas of the memory cells and the areas of the well contact cells are equal.

5. 发明授权

US06466494B2 Semiconductor integrated circuit device with memory circuit 失效
标题翻译：具有存储电路的半导体集成电路器件
公开(公告)号：US06466494B2
公开(公告)日：2002-10-15
申请号：US09833256
申请日：2001-04-12
申请人： Chikayoshi Morishima
发明人： Chikayoshi Morishima
IPC分类号： G11C800
CPC分类号： G11C29/80 , G11C29/812 , G11C2207/104
摘要： A shared program circuit is provided for a plurality of memory circuits, and a select circuit is provided for selecting one of the memory circuits. The select circuit includes gate circuits for transmitting a program signal from the shared program circuit to the memory circuits, and a gate selector that activates one of the gate circuits. Thus, in a semiconductor integrated circuit device provided with a plurality of memory circuits, like an ASIC, chip area occupied by a program circuit for programming an address of a defective memory cell therein is reduced.
摘要翻译：为多个存储电路提供共享程序电路，并且提供选择电路用于选择存储电路之一。选择电路包括用于从共享程序电路向存储器电路发送编程信号的门电路，以及激活门电路之一的门选择器。因此，在设置有诸如ASIC的多个存储器电路的半导体集成电路器件中，减少了用于对其中的有缺陷的存储单元的地址进行编程的程序电路占用的芯片面积。

6. 发明授权

US6124749A Semiconductor circuit device with reduced power consumption 失效
标题翻译：半导体电路器件功耗降低
公开(公告)号：US6124749A
公开(公告)日：2000-09-26
申请号：US080259
申请日：1998-05-18
申请人： Chikayoshi Morishima
发明人： Chikayoshi Morishima
IPC分类号： G11C11/414 , H01L21/8234 , H01L27/088 , H03K19/00 , H03K17/16
CPC分类号： H03K19/0019
摘要： In the semiconductor circuit device of the present invention, the switching circuit 10 connects the power supply pin 4 to the capacitance 9 before the input signal 2 to the semiconductor circuit 1 is changed so that the electric charge of the semiconductor 1 is stored in the capacitance 9, and when the input signal 2 is changed, the semiconductor circuit 1 is charged with the electric charge stored in the capacitance 9. And, after the input signal 2 is changed, the switching circuit 10 connects the power supply pin 4 to a power supply to charge the semiconductor circuit 1.
摘要翻译：在本发明的半导体电路装置中，切换电路10在将半导体电路1的输入信号2改变为将半导体1的电荷存储在电容器中之前，将电源引脚4与电容9连接如图9所示，并且当输入信号2改变时，对存储在电容9中的电荷对半导体电路1进行充电。并且，在输入信号2改变之后，开关电路10将电源引脚4连接到电源供给半导体电路1充电。

7. 发明授权

US5969995A Static semiconductor memory device having active mode and sleep mode 有权
标题翻译：具有活动模式和休眠模式的静态半导体存储器件
公开(公告)号：US5969995A
公开(公告)日：1999-10-19
申请号：US129095
申请日：1998-08-05
申请人： Chikayoshi Morishima
发明人： Chikayoshi Morishima
IPC分类号： G11C11/41 , G11C5/14 , G11C11/417 , G11C16/04
CPC分类号： G11C11/417 , G11C5/14
摘要： A power supply control circuit of an SRAM cuts off supply of power supply voltage to any component other than memory cells and a word line potential fix circuit in a sleep period in which only retention of data is carried out. The word line potential fix circuit fixes a word line at a non-selection level in the sleep period. The potential on the word line never becomes unstable in the sleep period so that data in the memory cell is never destroyed. Accordingly, a static semiconductor memory device consuming less power and having a high data retention ability can be provided.
摘要翻译： SRAM的电源控制电路在仅进行数据保留的休眠期间中断电源电压供给除了存储单元以外的任何部件和字线电位固定电路。字线电位固定电路在睡眠期间将字线固定在非选择电平。字线上的电位在睡眠期间永远不会变得不稳定，从而不会破坏存储单元中的数据。因此，可以提供消耗较少功率并且具有高数据保持能力的静态半导体存储器件。

8. 发明授权

US5708802A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US5708802A
公开(公告)日：1998-01-13
申请号：US564651
申请日：1995-11-29
申请人： Chikayoshi Morishima , Shigeki Ohbayashi
发明人： Chikayoshi Morishima , Shigeki Ohbayashi
IPC分类号： G06F1/08 , G06F1/04
CPC分类号： G06F1/08
摘要： To obtain a semiconductor memory device capable of keeping the internal circuit in active state at all times, without increasing the power consumption during normal operation, and not increasing the number of pins. A burn-in clock generating circuit (1) receives an external clock CLK, a mode signal MODE, and an internal clock INTCLK to output a burn-in clock BICLK to a decoder (5). The burn-in clock BICLK becomes a signal equivalent to the internal clock INTCLK when the mode signal MODE is a fixed signal of H or L indicating normal operation, and becomes a fixed signal of H for indicating activation at all times when the mode signal MODE is a clock at half frequency of the external clock CLK.
摘要翻译：为了获得能够始终保持内部电路处于活动状态的半导体存储器件，而不增加正常操作期间的功耗，并且不增加引脚数。老化时钟发生电路（1）接收外部时钟CLK，模式信号MODE和内部时钟INTCLK，以将老化时钟BICLK输出到解码器（5）。当模式信号MODE是指示正常操作的H或L的固定信号时，老化时钟BICLK变为等于内部时钟INTCLK的信号，并且当模式信号MODE 是外部时钟CLK的一半频率的时钟。

9. 发明授权

US07535251B2 Semiconductor device and impedance adjusting method thereof 失效
标题翻译：半导体装置及其阻抗调整方法
公开(公告)号：US07535251B2
公开(公告)日：2009-05-19
申请号：US11852032
申请日：2007-09-07
申请人： Chikayoshi Morishima , Tokuya Osawa , Masaru Haraguchi , Yoshihiro Yamashita
发明人： Chikayoshi Morishima , Tokuya Osawa , Masaru Haraguchi , Yoshihiro Yamashita
IPC分类号： H03K17/16 , H03K19/003 , H03K19/094 , H03K19/0175 , H03K19/084 , G11C8/00
CPC分类号： H03K19/0005 , H03K19/018578
摘要： There is provided a semiconductor device including an output buffer circuit which reduces an area occupied by a circuit for impedance adjustment and allows high-speed impedance adjustment. In an impedance measuring circuit, the impedance values of reference transistors having the same sizes as those of a plurality of transistors composing the output buffer circuit which are equal in size are measured. An impedance code generating circuit outputs impedance codes corresponding to the impedance values of the reference transistors to an output buffer code generating circuit based on the result of the measurement from the impedance measuring circuit. The output buffer code generating circuit generates output buffer codes for adjusting the impedance of the output buffer circuit by performing an arithmetic operation process to provide an objective impedance based on the impedance codes.
摘要翻译：提供了一种包括输出缓冲电路的半导体器件，其减少用于阻抗调整的电路占据的面积，并允许高速阻抗调节。在阻抗测量电路中，测量与构成输出缓冲电路的多个晶体管尺寸相同尺寸的参考晶体管的尺寸相等的阻抗值。基于来自阻抗测量电路的测量结果，阻抗代码产生电路将对应于参考晶体管的阻抗值的阻抗代码输出到输出缓冲器代码产生电路。输出缓冲器代码产生电路通过执行算术运算处理产生用于调节输出缓冲器电路的阻抗的输出缓冲器代码，以提供基于阻抗代码的物镜阻抗。

10. 发明授权

US07339850B2 Semiconductor memory device allowing high-speed data reading 有权
标题翻译：半导体存储器件允许高速数据读取
公开(公告)号：US07339850B2
公开(公告)日：2008-03-04
申请号：US11178430
申请日：2005-07-12
申请人： Chikayoshi Morishima
发明人： Chikayoshi Morishima
IPC分类号： G11C8/00 , G11C15/02 , G11C7/06
CPC分类号： G11C11/413 , G11C7/1051 , G11C7/1066 , G11C7/1069 , G11C7/1078 , G11C7/1096 , G11C2207/005
摘要： Each of a plurality of memory blocks arranged for 1 bit data is divided into two subarrays. A separate local data line is provided for each subarray and coupled to a sense amplifier via an isolation gate. A memory cell is selected in a selected subarray of a selected memory block, and a bit line of the selected memory cell is coupled to a corresponding local data line. Only a local data line of the selected subarray is coupled to the sense amplifier to perform a sense operation, and a global read data line is driven via a read driver in accordance with an output signal of the sense amplifier. A load of a sense node of the sense amplifier in a semiconductor memory device is reduced to implement high-speed reading of internal data.
摘要翻译：排列为1位数据的多个存储块中的每一个被分成两个子阵列。为每个子阵列提供单独的本地数据线，并通过隔离门耦合到读出放大器。在所选择的存储器块的所选子阵列中选择存储器单元，并且所选择的存储器单元的位线耦合到相应的本地数据线。只有所选子阵列的本地数据线被耦合到读出放大器以执行感测操作，并且根据读出放大器的输出信号通过读驱动器来驱动全局读数据线。减少半导体存储器件中的读出放大器的感测节点的负载，以实现对内部数据的高速读取。

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