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1. 发明授权

US6128208A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US6128208A
公开(公告)日：2000-10-03
申请号：US401185
申请日：1999-09-23
申请人： Niichi Itoh , Yasunobu Nakase , Tetsuya Watanabe , Chikayoshi Morishima
发明人： Niichi Itoh , Yasunobu Nakase , Tetsuya Watanabe , Chikayoshi Morishima
IPC分类号： H01L27/10 , H01L21/8242 , H01L27/108 , G11C5/02
CPC分类号： H01L27/10844 , H01L27/10897
摘要： Provided is a semiconductor memory having a layout structure in which a memory cell has excellent patterning controllability. A pattern of element components (active regions 10 to 15 and 21 to 23 and polysilicon regions 31 to 42) of a memory cell for one memory cell unit of a memory cell array region 1 is identical to that of a dummy cell of a peripheral dummy cell region 3, and both patterns present a line symmetrical relationship with respect to a boundary line BC1. In addition, a pattern of the memory cell for one memory cell unit of the memory cell array region 1 is identical to that of a dummy cell of a power wiring region 2, and both patterns present a line symmetrical relationship with respect to a boundary line BC2.
摘要翻译：提供一种具有布局结构的半导体存储器，其中存储单元具有优异的图案化可控性。存储单元阵列区域1的一个存储单元单元的存储单元的元件部件（有源区域10至15和21至23以及多晶硅区域31至42）的图案与外围虚拟元件的虚设单元相同单元区域3，并且两个图案相对于边界线BC1呈现线对称关系。此外，存储单元阵列区域1的一个存储单元单元的存储单元的图案与电力布线区域2的虚设单元的图案相同，并且两个图案相对于边界线呈现线对称关系 BC2。

2. 发明授权

US06327166B1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US06327166B1
公开(公告)日：2001-12-04
申请号：US09651322
申请日：2000-08-31
申请人： Niichi Itoh , Yasunobu Nakase , Tetsuya Watanabe , Chikayoshi Morishima
发明人： Niichi Itoh , Yasunobu Nakase , Tetsuya Watanabe , Chikayoshi Morishima
IPC分类号： G11C502
CPC分类号： H01L27/10844 , H01L27/10897
摘要： Provided is a semiconductor memory having a layout structure in which a memory cell has excellent patterning controllability. A pattern of element components (active regions 10 to 15 and 21 to 23 and polysilicon regions 31 to 42) of a memory cell for one memory cell unit of a memory cell array region 1 is identical to that of a dummy cell of a peripheral dummy cell region 3, and both patterns present a line symmetrical relationship with respect to a boundary line BC1. In addition, a pattern of the memory cell for one memory cell unit of the memory cell array region 1 is identical to that of a dummy cell of a power wiring region 2, and both patterns present a line symmetrical relationship with respect to a boundary line BC2.
摘要翻译：提供一种具有布局结构的半导体存储器，其中存储单元具有优异的图案化可控性。存储单元阵列区域1的一个存储单元单元的存储单元的元件部件（有源区域10至15和21至23以及多晶硅区域31至42）的图案与外围虚拟元件的虚设单元相同单元区域3，并且两个图案相对于边界线BC1呈现线对称关系。此外，存储单元阵列区域1的一个存储单元单元的存储单元的图案与电力布线区域2的虚设单元的图案相同，并且两个图案相对于边界线呈现线对称关系 BC2。

3. 发明授权

US06201758B1 Semiconductor memory device permitting time required for writing data to be reduced 失效
标题翻译：允许减少写入数据所需的时间的半导体存储器件
公开(公告)号：US06201758B1
公开(公告)日：2001-03-13
申请号：US09499044
申请日：2000-02-07
申请人： Chikayoshi Morishima , Yasunobu Nakase , Tetsuya Watanabe , Niichi Itoh
发明人： Chikayoshi Morishima , Yasunobu Nakase , Tetsuya Watanabe , Niichi Itoh
IPC分类号： G11C800
CPC分类号： G11C11/419
摘要： A precharge circuit and a bit line load circuit are provided to a read bit line pair. The bit line load circuit continuously supplies a prescribed current to a read bit line. When data is written to one of memory cells selected in common by one read word line, the level of each read bit line will not be lowered to the level of the ground potential by the bit line load circuit if a read word line is activated, and therefore the loads of both discharge and charge operations by transistors in the memory cell are reduced.
摘要翻译：向读位线对提供预充电电路和位线负载电路。位线负载电路将规定的电流连续地提供给读位线。当将数据写入一个读取字线共同选择的存储器单元之一时，如果读取的字线被激活，则每个读取位线的电平将不会被位线负载电路降低到地电位的电平，因此减小存储单元中的晶体管的放电和充电操作的负载。

4. 发明授权

US06717842B2 Static type semiconductor memory device with dummy memory cell 有权
标题翻译：具有虚拟存储单元的静态型半导体存储器件
公开(公告)号：US06717842B2
公开(公告)日：2004-04-06
申请号：US10339324
申请日：2003-01-10
申请人： Tetsuya Watanabe , Koji Nii , Yasunobu Nakase
发明人： Tetsuya Watanabe , Koji Nii , Yasunobu Nakase
IPC分类号： G11C1100
CPC分类号： G11C11/419
摘要： The dummy cell of the SRAM corresponds to a normal memory cell of which first and second P-channel MOS transistors for loading are replaced by the first and the second N-channel MOS transistors, of which gate and source are provided with power supply potential and ground potential, respectively. When a word line rises to “H” level, third and fourth N-channel MOS transistors for accessing are rendered conductive, to pass current from dummy bit line to a line of ground potential via the third N-channel MOS transistor, the first N-channel MOS transistor, and a fifth N-channel MOS transistor for driving. Accordingly, speed of potential decrease of the dummy bit line may be faster than that of bit line. Hence, operational timing can easily be optimized, and operational margin can be increased.
摘要翻译： SRAM的虚拟单元对应于其第一和第二P沟道MOS晶体管用于加载的第一和第二N沟道MOS晶体管被替代的正常存储单元，其中栅极和源极被提供有电源电位，地电位。当字线上升到“H”电平时，用于访问的第三和第四N沟道MOS晶体管导通，经由第三N沟道MOS晶体管将电流从虚拟位线传递到地电位，第一N 沟道MOS晶体管和用于驱动的第五N沟道MOS晶体管。因此，虚拟位线的潜在降低速度可能比位线的速度更快。因此，可以容易地优化操作时间，并且可以增加操作裕量。

5. 发明授权

US06188285B1 Phase-locked loop circuit and voltage-controlled oscillator capable of producing oscillations in a plurality of frequency ranges 失效
标题翻译：能够产生多个频率范围的振荡的锁相环电路和压控振荡器
公开(公告)号：US06188285B1
公开(公告)日：2001-02-13
申请号：US09281904
申请日：1999-03-31
申请人： Jingo Nakanishi , Yasunobu Nakase
发明人： Jingo Nakanishi , Yasunobu Nakase
IPC分类号： H03B502
CPC分类号： H03L7/0995 , H03B5/1221 , H03B5/1253 , H03L7/0802
摘要： In a PLL circuit including a plurality of VCOs, first and second switches are respectively connected between the gate and source and the gate and drain of a P channel MOS transistor included in a current mirror circuit of each VCO. In a VCO which is employed, only the second switch is turned on to allow a control current to flow. In a VCO which is not employed, only the first switch is turned on to cut off the control current. Compared with a conventional circuit in which all of the plurality of VCOs are always producing oscillations, the power consumption is reduced.
摘要翻译：在包括多个VCO的PLL电路中，第一和第二开关分别连接在每个VCO的电流镜像电路中的P沟道MOS晶体管的栅极和源极以及栅极和漏极之间。在采用的VCO中，只有第二开关导通以允许控制电流流动。在不使用的VCO中，只有第一开关导通以截止控制电流。与其中所有多个VCO总是产生振荡的常规电路相比，功耗降低。

6. 发明授权

US5982366A Cursor memory 失效
标题翻译：游标记忆
公开(公告)号：US5982366A
公开(公告)日：1999-11-09
申请号：US912637
申请日：1997-08-18
申请人： Yasunobu Nakase
发明人： Yasunobu Nakase
IPC分类号： G09G5/00 , G09G5/08
CPC分类号： G09G5/08
摘要： First and second pattern data constituting cursor pattern data are stored separately in banks (101a, 101b). A cursor memory body (101) simultaneously outputs the first and second pattern data from the banks (101a, 101b). Therefore, a read circuit (102) can simultaneously output the first and second pattern data through a port (P2) with a simple control. With this configuration, an easy-controllable cursor memory can be provided.
摘要翻译：构成光标图案数据的第一和第二图案数据分别存储在存储体（101a，101b）中。光标存储器主体（101）同时从存储体（101a，101b）输出第一和第二图案数据。因此，读取电路（102）可以通过简单的控制通过端口（P2）同时输出第一和第二模式数据。利用该配置，可以提供易于控制的光标存储器。

7. 发明授权

US5298774A Gate array system semiconductor integrated circuit device 失效
标题翻译：门阵列系统半导体集成电路器件
公开(公告)号：US5298774A
公开(公告)日：1994-03-29
申请号：US844920
申请日：1992-03-05
申请人： Kimio Ueda , Yasunobu Nakase
发明人： Kimio Ueda , Yasunobu Nakase
IPC分类号： H01L27/02 , H01L27/118 , H01L27/10
CPC分类号： H01L27/11807 , H01L27/0203
摘要： Disclosed is a semiconductor integrated circuit device of a gate array system making it possible to mount a digital circuit and a high-precision analog circuit on a common substrate. This semiconductor integrated circuit device includes a basic cell array formed by a plurality of NMOS transistors and a plurality of PMOS transistors formed in rows on a semiconductor substrate. The basic cell array includes a plurality of N well regions formed in rows on the semiconductor substrate, P well regions and well terminal regions. The P well regions or N well regions are divided into small regions of the other conductivity type.
摘要翻译：公开了一种门阵列系统的半导体集成电路器件，使得可以在公共衬底上安装数字电路和高精度模拟电路。该半导体集成电路器件包括由多个NMOS晶体管形成的基本单元阵列和在半导体衬底上以行形成的多个PMOS晶体管。基本单元阵列包括在半导体衬底上的行中形成的多个N阱区，P阱区和阱端子区。 P阱区或N阱区分为另一种导电类型的小区域。

8. 发明授权

US4821234A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US4821234A
公开(公告)日：1989-04-11
申请号：US046788
申请日：1987-05-07
申请人： Yasunobu Nakase
发明人： Yasunobu Nakase
IPC分类号： G11C11/34 , G11C8/08 , G11C11/415 , G11C11/40
CPC分类号： G11C8/08 , G11C11/415
摘要： When a pair of word lines 1 and 2 change from a selected state to a non selected state, a word line discharging circuit 10 enables a transistor 15 to conduct during a period when this pair of word lines 1 and 2 are maintained at the highest potential compared with the other pairs of word lines, so that the pair of word lines 1 and 2 are discharged by means of a first discharging current source 11. The word line discharging circuit 10 enables a transistor 16 to conduct after another pair of word lines attain the highest potential, so that the pair of word lines 1 and 2 are discharged by means of a second discharging current source 12.
摘要翻译：当一对字线1和2从选择状态变为非选择状态时，字线放电电路10使晶体管15在这一对字线1和2保持在最高电位的时段期间导通与其他字线对相比，使得一对字线1和2通过第一放电电流源11放电。字线放电电路10使晶体管16在另一对字线达到之后导通使得一对字线1和2通过第二放电电流源12放电。

9. 发明授权

US06765413B2 Bus circuit preventing delay of the operational speed and design method thereof 失效
标题翻译：总线电路防止操作速度的延迟及其设计方法
公开(公告)号：US06765413B2
公开(公告)日：2004-07-20
申请号：US10118145
申请日：2002-04-09
申请人： Yasunobu Nakase
发明人： Yasunobu Nakase
IPC分类号： H03K19175
CPC分类号： G11C7/1057 , G11C5/063 , G11C7/1051
摘要： In a bus circuit which includes a plurality of signal lines, insertion pattern &agr;, which provides repeaters in only an odd numbered series of signal lines, and insertion pattern &bgr;, of which the segment length is equal to that of pattern &agr; and which provides repeaters to only an even numbered series of signal lines, are arranged in an alternating manner in accordance with the length of the signal lines. As a result, the segments during which data signals on the neighboring signal lines run together in opposite phases become half the entire length of the signal lines. Therefore, this bus circuit can prevent the operational speed from becoming slowed.
摘要翻译：在包括多个信号线的总线电路中，仅在奇数编号的一系列信号线中提供中继器的插入模式α和其长度等于模式α的插入模式，并且提供中继器只有偶数编号的信号线系列根据信号线的长度以交替的方式排列。结果，相邻信号线上的数据信号以相反相位一起运行的段成为信号线整个长度的一半。因此，该总线电路可以防止运行速度变慢。

10. 发明授权

US06760269B2 Semiconductor memory device capable of generating internal data read timing precisely 失效
标题翻译：能够准确地产生内部数据读取定时的半导体存储器件
公开(公告)号：US06760269B2
公开(公告)日：2004-07-06
申请号：US10445009
申请日：2003-05-27
申请人： Yasunobu Nakase , Koji Nii
发明人： Yasunobu Nakase , Koji Nii
IPC分类号： G11C700
CPC分类号： G11C7/227 , G11C7/22 , G11C29/023 , G11C29/026 , G11C29/028 , G11C29/24 , G11C2207/2281
摘要： Dummy cells are divided into a plurality of divided dummy columns, and divided dummy bit lines are arranged corresponding to the divided dummy columns. These divided dummy bit lines are provided with dummy sense amplifiers that drive a sense control line transmitting a sense enable signal activating a sense amplifier. A faster activation timing of the sense amplifier can be achieved.
摘要翻译：虚拟单元被分成多个划分的虚拟列，并且分割的虚拟位线对应于分割的虚拟列排列。这些分开的虚拟位线设置有虚拟读出放大器，其驱动感测控制线传输感测使能信号来激活读出放大器。可以实现读出放大器的更快的激活定时。

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