专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08043918B2 Semiconductor device and its manufacturing method 失效
标题翻译：半导体器件及其制造方法
公开(公告)号：US08043918B2
公开(公告)日：2011-10-25
申请号：US12840430
申请日：2010-07-21
申请人： Takashi Kuroi , Katsuyuki Horita , Masashi Kitazawa , Masato Ishibashi
发明人： Takashi Kuroi , Katsuyuki Horita , Masashi Kitazawa , Masato Ishibashi
IPC分类号： H01L21/336
CPC分类号： H01L21/823475 , H01L21/743 , H01L21/76229 , H01L21/763 , H01L21/823481 , H01L21/823871 , H01L21/823878 , H01L29/7833 , H01L2924/0002 , H01L2924/00
摘要： To manufacture in high productivity a semiconductor device capable of securely achieving element isolation by a trench-type element isolation and capable of effectively preventing potentials of adjacent elements from affecting other nodes, a method of manufacturing the semiconductor device includes: a step of forming a first layer on a substrate; a step of forming a trench by etching the first layer and the substrate; a step of thermally oxidizing an inner wall of the trench; a step of depositing a first conductive film having a film thickness equal to or larger than one half of the trench width of the trench on the substrate including the trench; a step of removing a first conductive film from the first layer by a CMP method and keeping the first conductive film left in only the trench; a step of anisotropically etching the first conductive film within the trench to adjust the height of the conductive film to become lower than the height of the surface of the substrate; a step of depositing an insulating film on the first conductive film by the CVD method to embed the upper part of the first conductive film within the trench; a step of flattening the insulating film by the CMP method; and a step of removing the first layer.
摘要翻译：为了以高生产率制造能够通过沟槽型元件隔离可靠地实现元件隔离并且能够有效地防止相邻元件的电位影响其他节点的半导体器件，制造半导体器件的方法包括：形成第一层; 通过蚀刻第一层和衬底形成沟槽的步骤; 热氧化沟槽内壁的步骤; 在包括沟槽的衬底上沉积膜厚度等于或大于沟槽的沟槽宽度的一半的第一导电膜的步骤; 通过CMP方法从第一层除去第一导电膜并保持第一导电膜仅留在沟槽中的步骤; 在沟槽内各向异性蚀刻第一导电膜的步骤，以调节导电膜的高度，使其低于衬底表面的高度; 通过CVD法在第一导电膜上沉积绝缘膜以将第一导电膜的上部嵌入沟槽内的步骤; 通过CMP方法使绝缘膜平坦化的步骤; 以及去除第一层的步骤。

2. 发明授权

US07791163B2 Semiconductor device and its manufacturing method 失效
标题翻译：半导体器件及其制造方法
公开(公告)号：US07791163B2
公开(公告)日：2010-09-07
申请号：US11577878
申请日：2005-10-18
申请人： Takashi Kuroi , Katsuyuki Horita , Masashi Kitazawa , Masato Ishibashi
发明人： Takashi Kuroi , Katsuyuki Horita , Masashi Kitazawa , Masato Ishibashi
IPC分类号： H01L29/768
CPC分类号： H01L21/823475 , H01L21/743 , H01L21/76229 , H01L21/763 , H01L21/823481 , H01L21/823871 , H01L21/823878 , H01L29/7833 , H01L2924/0002 , H01L2924/00
摘要： In the process of manufacturing a semiconductor device, a first layer is formed on a substrate, and the first layer and the substrate are etched to form a trench. The inner wall of the trench is thermally oxidized. On the substrate, including inside the trench, is deposited a first conductive film having a thickness equal to or larger than one half of the width of the trench. The first conductive film on the first layer is removed by chemical mechanical polishing such that the first conductive film remains in only the trench. The height of the first conductive film in the trench is adjusted to be lower than a surface of the substrate by anisotropically etching the first conductive film. An insulating film is deposited on the substrate by chemical vapor deposition to cover an upper surface of the first conductive film in the trench. The insulating film is flattened by chemical mechanical polishing, and the first layer is removed.
摘要翻译：在制造半导体器件的过程中，在衬底上形成第一层，并且蚀刻第一层和衬底以形成沟槽。沟槽的内壁被热氧化。在包括沟槽内部的衬底上沉积厚度等于或大于沟槽宽度的一半的第一导电膜。通过化学机械抛光去除第一层上的第一导电膜，使得第一导电膜仅保留在沟槽中。通过各向异性蚀刻第一导电膜，将沟槽中的第一导电膜的高度调节为低于衬底的表面。通过化学气相沉积在衬底上沉积绝缘膜以覆盖沟槽中的第一导电膜的上表面。绝缘膜通过化学机械抛光而变平，第一层被去除。

3. 发明申请

US20060163624A1 Semiconductor device, and manufacturing method thereof 审中-公开
标题翻译：半导体装置及其制造方法
公开(公告)号：US20060163624A1
公开(公告)日：2006-07-27
申请号：US11319740
申请日：2005-12-29
申请人： Takashi Kuroi
发明人： Takashi Kuroi
IPC分类号： H01L29/76 , H01L21/28
CPC分类号： H01L21/28097 , H01L21/26506 , H01L21/26513 , H01L21/823814 , H01L21/823835 , H01L29/41783 , H01L29/665 , H01L29/66507 , H01L29/66545 , H01L29/6659 , H01L29/66643
摘要： The present invention provides a semiconductor device having a fully silicided gate electrode (full-silicide gate electrode) and a manufacturing method thereof, that has no problem of the increase in junction leak current, can increase a thickness of a metal silicide film formed on a source/drain region, and can form a fully silicided gate electrode and metal silicide film with one silicide forming process. A metal silicide film is formed such that its upper main face becomes higher than a semiconductor substrate. The thickness of the metal silicide film can be increased in order to secure a sufficient distance from an interface between the metal silicide film and the semiconductor substrate to an interface between a source/drain diffusion layer and the semiconductor substrate. As a result, the thickness of the metal silicide layer can be increased while avoiding the increase in junction leak current, even if a full-silicide gate electrode is formed.
摘要翻译：本发明提供了一种具有全硅化物栅电极（全硅化物栅电极）及其制造方法的半导体器件，其不存在结漏电流增加的问题，可以增加形成在金属硅化物膜上的金属硅化物膜的厚度源极/漏极区域，并且可以形成具有一个硅化物形成工艺的完全硅化的栅电极和金属硅化物膜。形成金属硅化物膜，使得其上主面变得高于半导体衬底。可以增加金属硅化物膜的厚度，以确保从金属硅化物膜和半导体衬底之间的界面到源极/漏极扩散层和半导体衬底之间的界面的足够的距离。结果，即使形成全硅化物栅电极，也可以避免金属硅化物层的厚度，同时避免结漏电流的增加。

4. 发明申请

US20060027883A1 Semiconductor device and manufacturing method thereof 审中-公开
标题翻译：半导体装置及其制造方法
公开(公告)号：US20060027883A1
公开(公告)日：2006-02-09
申请号：US11241921
申请日：2005-10-04
申请人： Takashi Kuroi , Yasuyoshi Itoh , Katsuyuki Horita , Katsuomi Shiozawa
发明人： Takashi Kuroi , Yasuyoshi Itoh , Katsuyuki Horita , Katsuomi Shiozawa
IPC分类号： H01L29/94
CPC分类号： H01L29/66553 , H01L21/26586 , H01L21/28088 , H01L21/28114 , H01L29/42376 , H01L29/4966 , H01L29/517 , H01L29/66545 , H01L29/6659
摘要： An object is to obtain a semiconductor device in which channel length is reduced without increasing the gate resistance to realize higher operation speed and its manufacturing method. An MOSFET has a trench-type element isolation structure (2) formed in the main surface of a semiconductor substrate (1), a pair of extensions (3) and source/drain regions (4) selectively formed in the main surface of the semiconductor substrate (1) to face each other through a channel region (50), a silicon oxide film (5) formed on the trench-type element isolation structure (2) and on the source/drain regions (4) through a silicon oxide film (12), sidewalls (6) formed on sides of the silicon oxide film (5), a gate insulating film (7) formed on the main surface of the semiconductor substrate (1) in the part in which the channel region (50) is formed, and a gate electrode (8) formed to fill a recessed portion in an inversely tapered form formed by the sides of the sidewalls (6) and the upper surface of the gate insulating film (7).
摘要翻译：本发明的目的是获得其中通道长度减小而不增加栅极电阻以实现更高的操作速度的半导体器件及其制造方法。 MOSFET具有形成在半导体衬底（1）的主表面中的沟槽型元件隔离结构（2），在半导体的主表面中选择性地形成的一对延伸部（3）和源极/漏极区域（4）衬底（1）通过沟道区域（50）彼此面对，通过硅氧化膜形成在沟槽型元件隔离结构（2）上和源极/漏极区域（4）上的氧化硅膜（5）（12），形成在氧化硅膜（5）的侧面上的侧壁（6），形成在半导体衬底（1）的主表面上的沟道区域（50）的部分中的栅极绝缘膜（7）以及形成为以由侧壁（6）的侧面和栅极绝缘膜（7）的上表面形成的倒锥形状填充凹部的栅电极（8）。

5. 发明授权

US06274457B1 Method for manufacturing an isolation trench having plural profile angles 失效
标题翻译：用于制造具有多个轮廓角的隔离沟槽的方法
公开(公告)号：US06274457B1
公开(公告)日：2001-08-14
申请号：US09481386
申请日：2000-01-12
申请人： Maiko Sakai , Takashi Kuroi , Katsuyuki Horita
发明人： Maiko Sakai , Takashi Kuroi , Katsuyuki Horita
IPC分类号： H01L2176
CPC分类号： H01L21/76232
摘要： A semiconductor device comprising a semiconductor substrate, a trench formed in the substrate and having an inner wall including a sidewall and a bottom surface, a silicon oxide film deposited on the inner wall, and a buried oxide film deposited on the silicon oxide film to bury the trench, wherein the sidewall has portions of a sidewall sloped at a first profile angle A1, a second profile angle A2 and a third profile angle A3 from a surface of the substrate toward the bottom surface of the trench, and the profile angles have a relationship of A1
摘要翻译：一种半导体器件，包括半导体衬底，形成在衬底中并具有包括侧壁和底表面的内壁的沟槽，沉积在内壁上的氧化硅膜和沉积在氧化硅膜上的掩埋氧化膜以埋入沟槽，其中侧壁具有从基板的表面到沟槽的底表面以第一轮廓角A1倾斜的侧壁的第二轮廓角A2和第三轮廓角A3，并且轮廓角具有 A1

6. 发明授权

US5744845A Complementary MOS field effect transistor with tunnel effect means 失效
标题翻译：具有隧道效应的互补MOS场效应晶体管
公开(公告)号：US5744845A
公开(公告)日：1998-04-28
申请号：US800147
申请日：1997-02-13
申请人： Hirokazu Sayama , Takashi Kuroi
发明人： Hirokazu Sayama , Takashi Kuroi
IPC分类号： H01L21/28 , H01L21/8238 , H01L27/092 , H01L29/49 , H01L29/76 , H01L29/94
CPC分类号： H01L29/4975 , H01L21/823842 , H01L27/092 , H01L29/4941
摘要： In a complementary MOS field effect transistor having a dual gate electrode structure, which is improved so that an element property can be enhanced, a first gate electrode of an n channel MOSFET includes a first barrier film, and a second gate electrode of a p channel MOSFET includes a second barrier film. The first barrier film has a sufficiently small thickness so that a potential can be transmitted from a first conductive film to a first polycrystalline silicon film by means of a tunnel effect. The second barrier film has a sufficiently small thickness so that a potential can be transmitted from a second conductive film to a second silicon film by means of a tunnel effect.
摘要翻译：在具有双栅电极结构的互补MOS场效应晶体管中，其被改进以使得元件特性可以增强，n沟道MOSFET的第一栅电极包括第一阻挡膜，以及ap沟道MOSFET的第二栅电极包括第二阻挡膜。第一阻挡膜具有足够小的厚度，使得电势可以通过隧道效应从第一导电膜传输到第一多晶硅膜。第二阻挡膜具有足够小的厚度，从而可以通过隧道效应从第二导电膜向第二硅膜传输电位。

7. 发明授权

US5710438A Semiconductor device with a silicide layer 失效
标题翻译：具有硅化物层的半导体器件
公开(公告)号：US5710438A
公开(公告)日：1998-01-20
申请号：US550939
申请日：1995-10-31
申请人： Hidekazu Oda , Takashi Kuroi
发明人： Hidekazu Oda , Takashi Kuroi
IPC分类号： H01L29/78 , H01L21/265 , H01L21/28 , H01L21/285 , H01L21/336 , H01L29/45 , H01L29/49 , H01L29/76 , H01L27/108 , H01L29/94
CPC分类号： H01L29/66575 , H01L21/28052 , H01L21/28518 , H01L29/456 , H01L29/4933
摘要： To form a silicide layer excellent in flatness, uniform in film thickness, and less in junction leak, by destroying the natural oxide film which adversely affects a formation of silicide layer of cobalt or nickel. A cobalt layer (7) is formed in a film thickness of 20 nm or less on an electrode layer (4A) of a gate electrode (4) and on source/drain diffusion layers (1, 2), and a nitrogen (8) is injected by the ion implantation at a density of about 1E15/cm.sup.3 with an injection energy of 10 keV or more. At this time, the nitrogens (8) destroy the natural oxide film existing in the interface of the cobalt layer (7) and electrode layer (4A), and in the interface of the cobalt layer (7) and the source/drain diffusion layers (1, 2), and distribute deeply into the electrode layer (4A) and the source/drain diffusion layers (1, 2). Later, by a silicide forming reaction of cobalt, a silicide layer (6) is formed. Since the natural oxide film does not exist, the silicide forming reaction proceeds uniformly. Instead of the nitrogen (8), fluorine or silicon may be also used.
摘要翻译：通过破坏对钴或镍的硅化物层的形成有不利影响的自然氧化膜，形成平坦度优异，膜厚均匀，并且漏点较少的硅化物层。在栅电极（4）的电极层（4A）和源/漏扩散层（1,2）上形成厚度为20nm以下的钴层（7），氮（8）通过离子注入以约1E15 / cm3的密度注入，注入能量为10keV以上。此时，氮（8）破坏存在于钴层（7）和电极层（4A）的界面中的自然氧化膜，并且在钴层（7）和源极/漏极扩散层（1,2），并且深深地分布到电极层（4A）和源极/漏极扩散层（1,2）中。然后，通过钴的硅化物形成反应，形成硅化物层（6）。由于天然氧化物膜不存在，所以硅化物形成反应均匀地进行。代替氮（8），也可以使用氟或硅。

8. 发明授权

US5543647A Semiconductor device having a plurality of impurity layers 失效
标题翻译：具有多个杂质层的半导体器件
公开(公告)号：US5543647A
公开(公告)日：1996-08-06
申请号：US339200
申请日：1994-11-10
申请人： Maiko Kobayashi , Takashi Kuroi
发明人： Maiko Kobayashi , Takashi Kuroi
IPC分类号： H01L21/76 , H01L21/265 , H01L21/762 , H01L29/10 , H01L29/76
CPC分类号： H01L29/1083 , H01L21/762
摘要： A semiconductor device in which ability for isolating elements from each other can be improved and increase in substrate constant and junction capacitance can be suppressed, is disclosed. An impurity layer for improving the ability for isolating elements is positioned only immediately below an isolating insulating film. An impurity layer for adjusting substrate constant and junction capacitance is formed through independent steps from the impurity layer for improving the isolating ability.
摘要翻译：公开了能够提高彼此隔离元件的能力的半导体器件，并且可以抑制衬底常数和结电容的增加。用于提高隔离元件的能力的杂质层位于隔离绝缘膜的正下方。用于调整衬底常数的杂质层和结电容通过与杂质层的独立步骤形成，以提高隔离能力。

9. 发明授权

US5488245A Semiconductor memory device capable of electrically erasing and writing information 失效
标题翻译：能够电擦除和写入信息的半导体存储器件
公开(公告)号：US5488245A
公开(公告)日：1996-01-30
申请号：US318482
申请日：1994-10-05
申请人： Masahiro Shimizu , Masayoshi Shirahata , Takashi Kuroi , Takehisa Yamaguchi
发明人： Masahiro Shimizu , Masayoshi Shirahata , Takashi Kuroi , Takehisa Yamaguchi
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11521 , H01L27/115 , H01L29/7883
摘要： A semiconductor memory device and a manufacturing method of the same can effectively prevent deterioration of endurance characteristic which may occur in a data erasing operation, and a drain disturb phenomenon which may occur in a data writing operation. In the semiconductor memory device, an N-type impurity layer 3 is formed on a main surface of a P-type silicon substrate 1 located in a channel region. Thereby, a high electric field is not applied to a boundary region between the N-type impurity layer 3 and an N-type source diffusion region 10 during erasing of data, so that generation of interband tunneling in this region is effectively prevented. Also in this semiconductor memory device, the drain diffusion region 9 has an offset structure in which no portion thereof overlaps the floating gate electrode 5. Therefore, an electric field, which is generated across the floating gate electrode 5 and the drain diffusion region 9 in an unselected cell during writing of data, is weakened, as compared with the prior art, and the drain disturb phenomenon due to F-N tunneling is effectively prevented.
摘要翻译：半导体存储器件及其制造方法可以有效地防止在数据擦除操作中可能发生的耐久特性的劣化，以及在数据写入操作中可能发生的漏极干扰现象。在半导体存储器件中，在位于沟道区域中的P型硅衬底1的主表面上形成N型杂质层3。因此，在擦除数据期间，不向N型杂质层3和N型源极扩散区域10之间的边界区域施加高电场，从而有效地防止了在该区域产生带间隧穿。另外，在该半导体存储器件中，漏极扩散区域9具有偏移结构，其中没有任何部分与浮置栅极电极5重叠。因此，在浮置栅极电极5和漏极扩散区域9两端产生的电场与现有技术相比，写入数据期间的未选择的单元被削弱，并且有效地防止了由于FN隧穿引起的漏极干扰现象。

10. 发明授权

US5341022A Bipolar transistor having a high ion concentration buried floating collector and method of fabricating the same 失效
标题翻译：具有高离子浓度埋地浮动集电极的双极晶体管及其制造方法
公开(公告)号：US5341022A
公开(公告)日：1994-08-23
申请号：US31988
申请日：1993-03-16
申请人： Takashi Kuroi , Shigeru Kusunoki
发明人： Takashi Kuroi , Shigeru Kusunoki
IPC分类号： H01L21/265 , H01L21/322 , H01L21/331 , H01L29/08 , H01L29/73 , H01L29/732 , H01L29/32
CPC分类号： H01L29/66272 , H01L21/3221 , H01L29/0821 , Y10S148/01 , Y10S148/086 , Y10S257/928
摘要： A semiconductor device having a reduced leakage current is fabricated in a short time at a low cost with excellent controllability. A buried layer (20) which includes a principal buried layer (21) of high ion concentration containing secondary defects (22) sandwiched between secondary buried layers (3a, 3b) of low ion concentration from upper and lower directions is formed on a semiconductor substrate (1). The secondary defects (22) have stable gettering effects for reducing defects caused during formation of a transistor (200) and contamination by heavy metals. Further, the secondary buried layers (3a, 3b) prevent depletion layers from reaching the secondary defects (22). The semiconductor device can be formed in a short time since no epitaxial growth is employed.
摘要翻译：在短时间内以低成本制造具有减小的漏电流的半导体器件，具有优异的可控性。在半导体衬底上形成埋设层（20），该掩埋层（20）包括高离子浓度的主要埋置层（21），其含有从上下方向上的低离子浓度的二次掩埋层（3a，3b）夹入的二次缺陷（22）（1）。二次缺陷（22）具有稳定的吸气效应，可减少晶体管（200）形成过程中产生的缺陷和重金属污染。此外，二次埋层（3a，3b）防止耗尽层达到二次缺陷（22）。半导体器件可以在短时间内形成，因为不使用外延生长。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式