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1. 发明授权

US06410956B1 Method and system for using a spacer to offset implant damage and reduce lateral diffusion in flash memory devices 有权
标题翻译：使用间隔物补偿植入物损伤并减少闪存装置中的横向扩散的方法和系统
公开(公告)号：US06410956B1
公开(公告)日：2002-06-25
申请号：US09478864
申请日：2000-01-07
申请人： Vei-Han Chan , Scott D. Luning , Mark Randolph , Nicholas H. Tripsas , Daniel Sobek , Janet Wang , Timothy J. Thurgate , Sameer Haddad
发明人： Vei-Han Chan , Scott D. Luning , Mark Randolph , Nicholas H. Tripsas , Daniel Sobek , Janet Wang , Timothy J. Thurgate , Sameer Haddad
IPC分类号： H01L2976
CPC分类号： H01L29/66825
摘要： A system and method for providing a memory cell on a semiconductor is disclosed. In one aspect, the method and system include providing at least one gate stack on the semiconductor, depositing at least one spacer, and providing at least one source implant in the semiconductor. The at least one gate stack has an edge. A portion of the at least one spacer is disposed along the edge of the at least one gate stack. In another aspect, the method and system include providing at least one gate stack on the semiconductor, providing a first junction implant in the semiconductor, depositing at least one spacer, and providing a second junction implant in the semiconductor after the at least one spacer is deposited. The at least one gate stack has an edge. A portion of the at least one spacer is disposed at the edge of the at least one gate stack. In a third aspect, the method and system include providing at least one gate stack on the semiconductor, providing at least one source implant in the semiconductor, depositing at least one spacer after the at least one source implant is provided, and providing at least one drain implant in the semiconductor after the spacer is deposited. The at least one gate has an edge. A portion of the at least one spacer is disposed along the edge of the at least one gate.
摘要翻译：公开了一种在半导体上提供存储单元的系统和方法。在一个方面，所述方法和系统包括在半导体上提供至少一个栅极堆叠，沉积至少一个间隔物，以及在半导体中提供至少一个源极注入。至少一个栅极堆叠具有边缘。所述至少一个间隔物的一部分沿着所述至少一个栅极叠层的边缘设置。在另一方面，该方法和系统包括在半导体上提供至少一个栅极叠层，在半导体中提供第一结注入，沉积至少一个间隔物，以及在至少一个间隔物之后在半导体中提供第二结注入存放至少一个栅极堆叠具有边缘。所述至少一个间隔件的一部分设置在所述至少一个栅极叠层的边缘处。在第三方面，所述方法和系统包括在半导体上提供至少一个栅极堆叠，在半导体中提供至少一个源极注入，在提供至少一个源极植入之后沉积至少一个间隔物，并且提供至少一个在间隔物沉积之后在半导体中的漏极注入。至少一个门具有边缘。所述至少一个间隔物的一部分沿着所述至少一个栅极的边缘设置。

2. 发明授权

US6025240A Method and system for using a spacer to offset implant damage and reduce lateral diffusion in flash memory devices 失效
公开(公告)号：US6025240A
公开(公告)日：2000-02-15
申请号：US993600
申请日：1997-12-18
申请人： Vei-Han Chan , Scott D. Luning , Mark Randolph , Nicholas H. Tripsas , Daniel Sobek , Janet Wang , Timothy J. Thurgate , Sameer Haddad
发明人： Vei-Han Chan , Scott D. Luning , Mark Randolph , Nicholas H. Tripsas , Daniel Sobek , Janet Wang , Timothy J. Thurgate , Sameer Haddad
IPC分类号： H01L21/336 , H01L21/8247
CPC分类号： H01L29/66825
摘要： A system and method for providing a memory cell on a semiconductor is disclosed. In one aspect, the method and system include providing at least one gate stack on the semiconductor, depositing at least one spacer, and providing at least one source implant in the semiconductor. The at least one gate stack has an edge. A portion of the at least one spacer is disposed along the edge of the at least one gate stack. In another aspect, the method and system include providing at least one gate stack on the semiconductor, providing a first junction implant in the semiconductor, depositing at least one spacer, and providing a second junction implant in the semiconductor after the at least one spacer is deposited. The at least one gate stack has an edge. A portion of the at least one spacer is disposed at the edge of the at least one gate stack. In a third aspect, the method and system include providing at least one gate stack on the semiconductor, providing at least one source implant in the semiconductor, depositing at least one spacer after the at least one source implant is provided, and providing at least one drain implant in the semiconductor after the spacer is deposited. The at least one gate has an edge. A portion of the at least one spacer is disposed along the edge of the at least one gate.

3. 发明授权

US6153487A Approach for the formation of semiconductor devices which reduces band-to-band tunneling current and short-channel effects 失效
标题翻译：用于形成减少带对隧道电流和短沟道效应的半导体器件的方法
公开(公告)号：US6153487A
公开(公告)日：2000-11-28
申请号：US40107
申请日：1998-03-17
申请人： Scott D. Luning , Timothy J. Thurgate , Daniel Sobek , Nicholas H. Tripsas
发明人： Scott D. Luning , Timothy J. Thurgate , Daniel Sobek , Nicholas H. Tripsas
IPC分类号： H01L21/265 , H01L21/336 , H01L21/22 , H01L21/38 , H01L29/76
CPC分类号： H01L29/66825 , H01L21/2652
摘要： The present invention provides a method and system for the formation of semiconductor devices which reduces band-to-band tunneling current and short-channel effects. The method and system includes implanting first low-dose arsenic into an area in the substrate, thermally diffusing the first low-dose arsenic through a portion of the substrate, implanting a second higher-dose arsenic into the area in the substrate, and diffusing the second higher-dose arsenic into the area in the substrate. Under the present invention, the combination of the first and second arsenic implants has a graded lateral profile which reduces band-to-band tunneling current and short-channel effects. The method also improves the reliability and performance of the semiconductor devices.
摘要翻译：本发明提供一种用于形成半导体器件的方法和系统，其减少带间隧穿电流和短沟道效应。该方法和系统包括将第一低剂量砷注入到衬底中的区域中，通过衬底的一部分热扩散第一低剂量砷，将第二较高剂量的砷注入到衬底的区域中，第二高剂量砷进入底物区域。在本发明中，第一和第二砷植入物的组合具有梯度横向轮廓，其降低带对隧道电流和短通道效应。该方法还提高了半导体器件的可靠性和性能。

4. 发明授权

US06329257B1 Method for laterally peaked source doping profiles for better erase control in flash memory devices 失效
标题翻译：用于横向峰值源掺杂分布的方法，用于在闪速存储器件中更好的擦除控制
公开(公告)号：US06329257B1
公开(公告)日：2001-12-11
申请号：US08994140
申请日：1997-12-19
申请人： Scott D. Luning , Daniel Sobek , Timothy J. Thurgate
发明人： Scott D. Luning , Daniel Sobek , Timothy J. Thurgate
IPC分类号： H01L21336
CPC分类号： H01L29/0847 , H01L21/26586 , H01L21/28273 , H01L29/36 , H01L29/7883
摘要： A system and method for controlling a characteristic of at least one memory cell on a semiconductor is disclosed. The at least one memory cell includes a gate stack, a source, and a drain. The semiconductor includes a surface. In one aspect, the method and system include providing the gate stack on the semiconductor and providing the source including a source dopant having a local peak in concentration. The local peak in concentration of the source dopant is located under the gate stack and in proximity to a portion of the surface of the semiconductor. In another aspect the method and system includes a memory cell on a semiconductor. The semiconductor includes a surface. The memory cell includes a gate stack on the semiconductor, a source, and a drain. The gate stack has a first edge and a second edge. The source is located in proximity to the first edge of the gate stack. The drain is located in proximity to the second edge of the gate stack. A first portion of the source is disposed under the gate stack. The source includes a source dopant having a local peak in concentration of the source dopant. The local peak in concentration of the source dopant is located under the gate stack and in proximity to a portion of the surface of the semiconductor.
摘要翻译：公开了一种用于控制半导体上的至少一个存储单元的特性的系统和方法。所述至少一个存储单元包括栅极堆叠，源极和漏极。半导体包括表面。在一个方面，所述方法和系统包括在半导体上提供栅极堆叠并且提供源，其包括具有局部峰浓度的源掺杂剂。源掺杂剂的局部峰浓度位于栅极堆叠之下并且靠近半导体表面的一部分。在另一方面，该方法和系统包括半导体上的存储单元。半导体包括表面。存储单元包括半导体上的栅极堆叠，源极和漏极。栅极堆叠具有第一边缘和第二边缘。源极位于栅堆叠的第一边缘附近。漏极位于栅堆叠的第二边缘附近。源极的第一部分设置在栅极堆叠下方。该源包括源掺杂剂，其具有源掺杂剂浓度的局部峰。源掺杂剂的局部峰浓度位于栅极堆叠之下并且靠近半导体表面的一部分。

5. 发明授权

US06168637A Use of a large angle implant and current structure for eliminating a critical mask in flash memory processing 失效
标题翻译：使用大角度注入和电流结构来消除闪存处理中的关键掩模
公开(公告)号：US06168637A
公开(公告)日：2001-01-02
申请号：US08991322
申请日：1997-12-16
申请人： Mark Randolph , Timothy J. Thurgate , Scott D. Luning
发明人： Mark Randolph , Timothy J. Thurgate , Scott D. Luning
IPC分类号： H01L218247
CPC分类号： H01L27/11521 , Y10T29/41
摘要： A method and system for providing a flash memory cell on a semiconductor is disclosed. In one aspect, the method and system include providing a plurality of gate stacks and providing a drain implant at an angle. The plurality of gate stacks define a plurality of drain areas and a plurality of source areas. The angle is measured from a direction perpendicular to the surface of the semiconductor. The angle allows the plurality of gate stacks to block the drain implant from reaching the plurality of source areas. In another aspect, the method and system include providing a plurality of gate stacks and providing a source implant at an angle. The plurality of gate stacks define a plurality of drain areas and a plurality of source areas. The angle is measured from a direction perpendicular to the surface of the semiconductor. The angle allows the plurality of gate stacks to block the source implant from reaching the plurality of drain areas.
摘要翻译：公开了一种用于在半导体上提供闪存单元的方法和系统。在一个方面，该方法和系统包括提供多个栅极堆叠并以一定角度提供漏极注入。多个栅极堆叠限定多个漏极区域和多个源极区域。该角度是从垂直于半导体表面的方向测量的。该角度允许多个栅极堆叠阻挡漏极植入物到达多个源极区域。在另一方面，该方法和系统包括提供多个栅极叠层并以一定角度提供源植入物。多个栅极堆叠限定多个漏极区域和多个源极区域。该角度是从垂直于半导体表面的方向测量的。该角度允许多个栅极堆叠阻挡源植入物到达多个漏极区域。

6. 发明授权

US06456536B1 Method of programming a non-volatile memory cell using a substrate bias 有权
标题翻译：使用衬底偏置来编程非易失性存储单元的方法
公开(公告)号：US06456536B1
公开(公告)日：2002-09-24
申请号：US09884409
申请日：2001-06-19
申请人： Daniel Sobek , Timothy J. Thurgate , Janet Wang , Narbeh Derhacobian
发明人： Daniel Sobek , Timothy J. Thurgate , Janet Wang , Narbeh Derhacobian
IPC分类号： G11C1604
CPC分类号： G11C16/0475 , G11C11/5671 , G11C16/12
摘要： A method of programming a memory cell with a substrate that includes a first region and a second region with a channel therebetween and a gate above the channel, and a charge trapping region that contains a first amount of charge. The method includes applying a constant first voltage across the gate, applying a second constant voltage across the first region and applying a third voltage that is constant and negative to the substrate so that the effect of spillover electrons is substantially reduced when compared with when the third constant voltage is absent.
摘要翻译：一种用衬底编程存储单元的方法，该衬底包括第一区域和具有通道的第二区域和沟道上方的栅极以及包含第一电荷量的电荷捕获区域。该方法包括在栅极上施加恒定的第一电压，在第一区域上施加第二恒定电压，并向衬底施加恒定和负的第三电压，使得当与第三区域相比时，溢出电子的效应显着降低不存在恒定电压。

7. 发明授权

US6103602A Method and system for providing a drain side pocket implant 失效
标题翻译：用于提供排水侧口袋植入物的方法和系统
公开(公告)号：US6103602A
公开(公告)日：2000-08-15
申请号：US992618
申请日：1997-12-17
申请人： Timothy J. Thurgate , Vei-Han Chan
发明人： Timothy J. Thurgate , Vei-Han Chan
IPC分类号： H01L21/8238
CPC分类号： H01L29/7881 , H01L29/0847 , H01L29/66825 , H01L21/823412
摘要： A system and method for providing a memory cell on a semiconductor is disclosed. The memory cell has a source and a drain. The method and system include providing a source implant in the semiconductor, providing a pocket implant in the semiconductor, and providing a drain implant in the semiconductor after the pocket implant is provided. Thus, short channel effects are reduced.
摘要翻译：公开了一种在半导体上提供存储单元的系统和方法。存储单元具有源极和漏极。该方法和系统包括在半导体中提供源植入物，在半导体中提供凹穴注入，以及在提供口袋植入物之后在半导体中提供漏极注入。因此，短通道效应降低。

8. 发明授权

US06387755B1 Method and system for providing localized gate edge rounding with minimal encroachment and gate edge lifting 失效
标题翻译：用于以最小的侵入和门边缘提升提供局部门边缘四舍五入的方法和系统
公开(公告)号：US06387755B1
公开(公告)日：2002-05-14
申请号：US08992616
申请日：1997-12-17
申请人： Timothy J. Thurgate , Scott D. Luning
发明人： Timothy J. Thurgate , Scott D. Luning
IPC分类号： H01L21336
CPC分类号： H01L29/66825
摘要： A system and method for providing a memory cell on a semiconductor is disclosed. The method and system include providing an oxide layer on the semiconductor and providing at least one gate stack disposed above the oxide layer. The at least one gate stack has a corner contacting the oxide layer. The method and system further include exposing at least the corner of the at least one gate stack and rounding at least the corner of the at least one gate stack.
摘要翻译：公开了一种在半导体上提供存储单元的系统和方法。该方法和系统包括在半导体上提供氧化物层并提供设置在氧化物层上方的至少一个栅极堆叠。至少一个栅极堆叠具有与氧化物层接触的拐角。所述方法和系统还包括至少暴露所述至少一个栅极堆叠的角部并至少对所述至少一个栅极叠层的角进行舍入。

9. 发明授权

US07125763B1 Silicided buried bitline process for a non-volatile memory cell 失效
标题翻译：非易失性存储单元的硅化掩埋位线工艺
公开(公告)号：US07125763B1
公开(公告)日：2006-10-24
申请号：US09885426
申请日：2001-06-19
申请人： Daniel Sobek , Timothy J. Thurgate , Mark W. Randolph
发明人： Daniel Sobek , Timothy J. Thurgate , Mark W. Randolph
IPC分类号： H01L21/8238
CPC分类号： H01L27/11568 , H01L27/115 , H01L27/11521
摘要： A process of fabricating a memory cell that includes a substrate that has a first region and a second region with a channel therebetween by forming a gate above the channel of the substrate, forming a bitline and siliciding the bitline.
摘要翻译：一种制造存储单元的方法，该存储单元包括具有第一区域和第二区域的衬底，所述第一区域和第二区域之间具有通道，通过在衬底的沟道上形成栅极，形成位线并硅化位线。

10. 发明授权

US06366501B1 Selective erasure of a non-volatile memory cell of a flash memory device 有权
标题翻译：闪存设备的非易失性存储单元的选择性擦除
公开(公告)号：US06366501B1
公开(公告)日：2002-04-02
申请号：US09686686
申请日：2000-10-11
申请人： Timothy J. Thurgate , Daniel Sobek
发明人： Timothy J. Thurgate , Daniel Sobek
IPC分类号： G11C1134
CPC分类号： G11C16/0475 , G11C11/5671 , G11C16/14
摘要： A method of selectively erasing an individual memory cell of an array of non-volatile memory cells by providing an array of non-volatile memory cells that includes a first non-volatile memory cell that is connected in series with a second non-volatile memory cell and erasing the first non-volatile memory cell while not erasing the second non-volatile memory cell.
摘要翻译：一种通过提供包括与第二非易失性存储器单元串联连接的第一非易失性存储器单元的非易失性存储器单元的阵列来选择性地擦除非易失性存储单元阵列的单独存储单元的方法，以及擦除所述第一非易失性存储单元而不擦除所述第二非易失性存储单元。

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