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1. 发明授权

US06188127B1 Semiconductor packing stack module and method of producing the same 失效
标题翻译：半导体封装堆叠模块及其制造方法
公开(公告)号：US06188127B1
公开(公告)日：2001-02-13
申请号：US08604115
申请日：1996-02-20
申请人： Naoji Senba , Yuzo Shimada , Kazuaki Utsumi , Kenichi Tokuno , Ikushi Morizaki , Akihiro Dohya , Manabu Bonkohara
发明人： Naoji Senba , Yuzo Shimada , Kazuaki Utsumi , Kenichi Tokuno , Ikushi Morizaki , Akihiro Dohya , Manabu Bonkohara
IPC分类号： H01L2302
CPC分类号： H01L24/28 , H01L21/563 , H01L25/105 , H01L2224/16225 , H01L2224/29111 , H01L2224/2919 , H01L2224/32225 , H01L2224/48091 , H01L2224/48247 , H01L2224/73203 , H01L2224/73204 , H01L2224/73253 , H01L2224/83102 , H01L2224/92125 , H01L2225/1023 , H01L2225/1058 , H01L2225/1094 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01042 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/0132 , H01L2924/09701 , H01L2924/10253 , H01L2924/12042 , H01L2924/14 , H01L2924/15192 , H01L2924/15311 , H01L2924/1532 , H01L2924/15321 , H01L2924/15331 , H01L2924/15787 , H01L2924/1627 , H01L2924/181 , H01L2924/18161 , H01L2924/19041 , H01L2924/3011 , H01L2924/3511 , H01L2924/00014 , H01L2924/00 , H01L2924/0665 , H01L2924/00012
摘要： In a semiconductor package stack module, an LSI (Large Scale Integrated circuit) is mounted, via fine bumps, on a ceramic carrier substrate or a flexible carrier film on which wiring conductors are formed. After a seal resin has been injected, the chip is thinned by, e.g., grinding. A plurality of such carrier substrates or carrier films are connected to each other by bumps via through holes which are electrically connected to the wiring conductors, thereby completing a tridimensional stack module. The module achieves a miniature, thin, dense, low cost, and reliable structure without resorting to a wire bonding system or a TAB (Tape Automated Bonding) system. In addition, the module has a minimum of wiring length and a desirable electric characteristic.
摘要翻译：在半导体封装堆叠模块中，通过微小的凸块将LSI（大规模集成电路）安装在陶瓷载体基板或形成布线导体的柔性载体膜上。在注入密封树脂之后，通过例如研磨使芯片变薄。多个这样的载体基板或载体膜通过与导线导电连接的通孔而由凸块彼此连接，从而完成三维叠层模块。该模块实现了微型，薄型，致密，低成本和可靠的结构，而不需要使用引线接合系统或TAB（磁带自动接合）系统。此外，该模块具有最小的布线长度和期望的电特性。

2. 发明授权

US5777847A Multichip module having a cover wtih support pillar 失效
标题翻译：多芯片模块具有支撑柱支撑
公开(公告)号：US5777847A
公开(公告)日：1998-07-07
申请号：US812859
申请日：1997-03-06
申请人： Kenichi Tokuno , Akihiro Dohya
发明人： Kenichi Tokuno , Akihiro Dohya
IPC分类号： H01L23/10 , H01L23/367 , H05K7/20
CPC分类号： H01L23/10 , H01L23/3675 , H01L2224/16 , H01L2224/16225 , H01L2224/32225 , H01L2224/32245 , H01L2224/73204 , H01L2224/73253 , H01L25/0655 , H01L2924/09701 , H01L2924/15311 , H01L2924/16152 , H01L2924/3025
摘要： A multichip module comprises a substrate mounting a plurality of circuit chips, a cover plate positioned over the circuit chips, and at least one pillar member for fixing the cover plate to the substrate to support it. The substrate has a plurality of circuit chips fixed in a predetermined pattern of locations on a side thereof. At least one pillar member fixes the cover plate to the substrate such that the cover plate is positioned over the circuit chips. Since the pillar member is fixed to the substrate at a small area to support the cover plate, the substrate can be prevented from deforming due to a temperature change. In order to secure the covering member, the pillar member is preferably fixed by means of an adhesive, a fit, or screwing.
摘要翻译：多芯片模块包括安装多个电路芯片的基板，位于电路芯片上方的盖板以及用于将盖板固定到基板以支撑其的至少一个柱构件。基板具有固定在其侧面上的预定图案位置的多个电路芯片。至少一个柱构件将盖板固定到基板，使得盖板位于电路芯片上方。由于柱构件在小面积上固定在基板上以支撑盖板，所以可以防止基板由于温度变化而变形。为了固定覆盖构件，柱构件优选地通过粘合剂，配合或螺纹固定。

3. 发明授权

US5767689A Bare chip test carrier with an improved holding structure for a semiconductor chip 失效
标题翻译：具有改进的用于半导体芯片的保持结构的裸芯片测试载体
公开(公告)号：US5767689A
公开(公告)日：1998-06-16
申请号：US575480
申请日：1995-12-20
申请人： Kenichi Tokuno , Akihiro Dohya
发明人： Kenichi Tokuno , Akihiro Dohya
IPC分类号： H01L21/66 , G01R1/04 , G01R31/26 , G01R31/02
CPC分类号： G01R1/0408
摘要： A chip tester for holding a semiconductor chip bonded via convex electrodes to a flexible substrate. The tester has a carrier body with a flat surface in contact with the flexible board. The carrier body overlies the flexible substrate so as to press down the flexible substrate. The tester also has a chip plate that underlies and contacts the semiconductor chip so as to urge the semiconductor chip toward the flexible substrate. At least a flat contact surface of the chip plate is made of an elastic material with a high elastic coefficient to obtain an adhesion with the semiconductor chip to prevent lateral displacement of the semiconductor chip. The tester also has a chip plate holder that underlies the flexible substrate and is positioned around both the semiconductor chip and the chip plate. The chip plate holder is spaced apart from the semiconductor chip so that the chip plate holder sandwiches the flexible substrate in cooperation with the carrier body.
摘要翻译：用于将通过凸电极粘合的半导体芯片保持在柔性基板上的芯片测试器。测试仪具有与柔性板接触的平坦表面的承载体。承载体覆盖柔性基板，以便将柔性基板压下。测试仪还具有底板并接触半导体芯片，以将半导体芯片推向柔性基板。芯片板的至少平坦的接触表面由具有高弹性系数的弹性材料制成，以获得与半导体芯片的粘附性，以防止半导体芯片的横向位移。该测试仪还具有一个位于柔性基片下方并位于半导体芯片和芯片板周围的芯片板支架。芯片板保持件与半导体芯片间隔开，使得芯片板保持器与载体主体协作地夹持柔性基板。

4. 发明授权

US5012047A Multilayer wiring substrate 失效
标题翻译：多层布线基板
公开(公告)号：US5012047A
公开(公告)日：1991-04-30
申请号：US481726
申请日：1990-02-16
申请人： Akihiro Dohya
发明人： Akihiro Dohya
IPC分类号： H05K3/46 , H01L23/538 , H01L23/64 , H05K1/00 , H05K1/02 , H05K1/03
CPC分类号： H01L23/5383 , H01L23/642 , H05K1/024 , H01L2924/0002 , H01L2924/09701 , H01L2924/3011 , H05K1/0298 , H05K1/0306 , H05K2201/0154
摘要： A multilayer wiring substrate which includes a plurality of laminated wiring layers, a plurality of insulating layers for providing insulation between the wiring layers, and a plurality of hollows provided within at least one of the insulating layers.
摘要翻译：一种多层布线基板，包括多个层叠布线层，多个用于在布线层之间提供绝缘的绝缘层和设置在至少一个绝缘层内的多个中空部。

5. 发明授权

US07297575B2 System semiconductor device and method of manufacturing the same 有权
标题翻译：系统半导体器件及其制造方法
公开(公告)号：US07297575B2
公开(公告)日：2007-11-20
申请号：US11103469
申请日：2005-04-12
申请人： Masamoto Tago , Akihiro Dohya
发明人： Masamoto Tago , Akihiro Dohya
IPC分类号： H01L21/44
CPC分类号： H01L23/49833 , H01L21/768 , H01L21/76898 , H01L23/147 , H01L23/3114 , H01L23/49827 , H01L23/5389 , H01L24/81 , H01L24/83 , H01L24/90 , H01L24/96 , H01L2224/12105 , H01L2224/29111 , H01L2224/2919 , H01L2224/81191 , H01L2224/81192 , H01L2224/8121 , H01L2224/81815 , H01L2224/83191 , H01L2224/83192 , H01L2224/838 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/0132 , H01L2924/014 , H01L2924/0665 , H01L2924/10253 , H01L2924/10329 , H01L2924/14 , H01L2924/157 , H01L2924/3011 , H01L2924/00 , H01L2924/01031
摘要： A system semiconductor device includes a system LSI cell portion and a global wiring layer. The system LSI cell portion has a plurality of functional blocks for realizing specific functions on a semiconductor chip. The global wiring layer has a wiring layer on a semiconductor substrate. The system LSI cell portion is laminated with the global wiring layer.
摘要翻译：系统半导体器件包括系统LSI单元部分和全局布线层。系统LSI单元部分具有用于在半导体芯片上实现特定功能的多个功能块。全局布线层在半导体衬底上具有布线层。系统LSI单元部分与全局布线层层叠。

6. 发明申请

US20050179057A1 System semiconductor device and method of manufacturing the same 有权
标题翻译：系统半导体器件及其制造方法
公开(公告)号：US20050179057A1
公开(公告)日：2005-08-18
申请号：US11103469
申请日：2005-04-12
申请人： Masamoto Tago , Akihiro Dohya
发明人： Masamoto Tago , Akihiro Dohya
IPC分类号： H01L23/52 , H01L21/02 , H01L21/3205 , H01L21/60 , H01L21/768 , H01L21/822 , H01L23/12 , H01L23/14 , H01L23/31 , H01L23/498 , H01L23/522 , H01L23/538 , H01L25/00 , H01L27/04 , H01L31/0336
CPC分类号： H01L23/49833 , H01L21/768 , H01L21/76898 , H01L23/147 , H01L23/3114 , H01L23/49827 , H01L23/5389 , H01L24/81 , H01L24/83 , H01L24/90 , H01L24/96 , H01L2224/12105 , H01L2224/29111 , H01L2224/2919 , H01L2224/81191 , H01L2224/81192 , H01L2224/8121 , H01L2224/81815 , H01L2224/83191 , H01L2224/83192 , H01L2224/838 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/0132 , H01L2924/014 , H01L2924/0665 , H01L2924/10253 , H01L2924/10329 , H01L2924/14 , H01L2924/157 , H01L2924/3011 , H01L2924/00 , H01L2924/01031
摘要： A system semiconductor device includes a system LSI cell portion and a global wiring layer. The system LSI cell portion has a plurality of functional blocks for realizing specific functions on a semiconductor chip. The global wiring layer has a wiring layer on a semiconductor substrate. The system LSI cell portion is laminated with the global wiring layer.
摘要翻译：系统半导体器件包括系统LSI单元部分和全局布线层。系统LSI单元部分具有用于在半导体芯片上实现特定功能的多个功能块。全局布线层在半导体衬底上具有布线层。系统LSI单元部分与全局布线层层叠。

7. 发明授权

US07098538B1 System semiconductor device and method of manufacturing the same 有权
标题翻译：系统半导体器件及其制造方法
公开(公告)号：US07098538B1
公开(公告)日：2006-08-29
申请号：US09613331
申请日：2000-07-07
申请人： Masamoto Tago , Akihiro Dohya
发明人： Masamoto Tago , Akihiro Dohya
IPC分类号： H01L23/48
CPC分类号： H01L23/49833 , H01L21/768 , H01L21/76898 , H01L23/147 , H01L23/3114 , H01L23/49827 , H01L23/5389 , H01L24/81 , H01L24/83 , H01L24/90 , H01L24/96 , H01L2224/12105 , H01L2224/29111 , H01L2224/2919 , H01L2224/81191 , H01L2224/81192 , H01L2224/8121 , H01L2224/81815 , H01L2224/83191 , H01L2224/83192 , H01L2224/838 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/0132 , H01L2924/014 , H01L2924/0665 , H01L2924/10253 , H01L2924/10329 , H01L2924/14 , H01L2924/157 , H01L2924/3011 , H01L2924/00 , H01L2924/01031
摘要： A system semiconductor device includes a system LSI cell portion and a global wiring layer. The system LSI cell portion has a plurality of functional blocks for realizing specific functions on a semiconductor chip. The global wiring layer has a wiring layer on a semiconductor substrate. The system LSI cell portion is laminated with the global wiring layer.
摘要翻译：系统半导体器件包括系统LSI单元部分和全局布线层。系统LSI单元部分具有用于在半导体芯片上实现特定功能的多个功能块。全局布线层在半导体衬底上具有布线层。系统LSI单元部分与全局布线层层叠。

8. 发明授权

US4736521A Process for manufacturing a ceramic multi-layer substrate 失效
标题翻译：陶瓷多层基板的制造方法
公开(公告)号：US4736521A
公开(公告)日：1988-04-12
申请号：US935499
申请日：1987-02-03
申请人： Akihiro Dohya
发明人： Akihiro Dohya
IPC分类号： H01L23/538 , H05K1/14
CPC分类号： H01L23/5383 , H01L2924/0002 , H01L2924/09701 , H01L2924/15192 , H01L2924/15312 , H01L2924/3011 , Y10T29/49126 , Y10T29/49163 , Y10T29/49165
摘要： A multi-layer comprising a multi-layer glass ceramic substrate and a multi-layer wire line matrix. The multi-layer wired line matrix includes an insulating layer made from a photosensitive insulating layer, amenable to time geometry processing. The insulating layer of the multi-layer wire line matrix has a pad for accommodating variations of the locations of the through holes. The metal is plated in and fills the through holes so that the metal is not cut off at the corners. The wire line matrix is composed of a plurality of layers of a photo-lithographically formed fine conductive pattern. The glass ceramic insulating layer is also formed photo-lithographically, and is formed of the source material of the insulating layers.
摘要翻译：包括多层玻璃陶瓷基板和多层有线线阵的多层。多层有线线阵列包括由感光绝缘层制成的绝缘层，适合于时间几何处理。多层有线线阵列的绝缘层具有用于容纳通孔位置变化的垫。金属被镀在并填充通孔，使金属在角落处不被切断。有线线矩阵由光刻成形的细导电图案的多层构成。玻璃陶瓷绝缘层也是由光刻法形成的，并由绝缘层的源材料形成。

9. 发明授权

US4665468A Module having a ceramic multi-layer substrate and a multi-layer circuit thereupon, and process for manufacturing the same 失效
标题翻译：具有陶瓷多层基板和多层电路的模块及其制造方法
公开(公告)号：US4665468A
公开(公告)日：1987-05-12
申请号：US753481
申请日：1985-07-10
申请人： Akihiro Dohya
发明人： Akihiro Dohya
IPC分类号： H01L23/538 , H05K1/11
CPC分类号： H01L23/5383 , H01L2924/0002 , H01L2924/09701 , H01L2924/15192 , H01L2924/15312 , H01L2924/3011 , Y10T29/49126 , Y10T29/49163 , Y10T29/49165
摘要： A multi-layer comprising a multi-layer glass ceramic substrate and a multi-layer wire line matrix. The multi-layer wired line matrix includes an insulating layer made from a photosensitive insulating layer, amenable to time geometry processing. The insulating layer of the multi-layer wire line matrix has a pad for accommodating variations of the locations of the through holes. The metal is plated in and fills the through holes so that the metal is not cut off at the corners. The wire line matrix is composed of a plurality of layers of a photo-lithographically formed fine conductive pattern. The glass ceramic insulating layer is also formed photo-lithographically, and is formed of the source material of the insulating layers.
摘要翻译：包括多层玻璃陶瓷基板和多层有线线阵的多层。多层有线线阵列包括由感光绝缘层制成的绝缘层，适合于时间几何处理。多层有线线阵列的绝缘层具有用于容纳通孔位置变化的垫。金属被镀在并填充通孔，使金属在角落处不被切断。有线线矩阵由光刻成形的细导电图案的多层构成。玻璃陶瓷绝缘层也是由光刻法形成的，并由绝缘层的源材料形成。

10. 发明授权

US4434544A Multilayer circuit and process for manufacturing the same 失效
标题翻译：多层电路和制造过程相同
公开(公告)号：US4434544A
公开(公告)日：1984-03-06
申请号：US429636
申请日：1982-09-30
申请人： Akihiro Dohya , Yasuhiko Hino , Mitsuo Abe
发明人： Akihiro Dohya , Yasuhiko Hino , Mitsuo Abe
IPC分类号： H01L27/01 , H05K1/03 , H05K1/09 , H05K3/10 , H05K3/24 , H05K3/46 , H01L29/46
CPC分类号： H01L27/016 , H05K3/108 , H05K3/4647 , H05K1/0306 , H05K1/09 , H05K2203/0315 , H05K2203/0733 , H05K2203/1142 , H05K3/243
摘要： A multilayer circuit construction includes a conductive layer formed of an alloy of a noble metal and a small amount of a base metal disposed on a heat resistant insulating substrate. The portion of the substrate not covered with the conductive alloy is covered with an oxide of the base metal constituent of the alloy. The construction may be formed by depositing a base metal layer over the substrate, followed by depositing the noble metal over a part of the base metal layer. By oxidizing at high temperatures, the exposed base metal layer is converted to oxide, while the noble metal and the base metal thereunder diffuse into each other to form the alloy.
摘要翻译：多层电路结构包括由贵金属和少量设置在耐热绝缘基板上的贱金属的合金形成的导电层。没有被导电合金覆盖的基板的部分被合金的贱金属成分的氧化物覆盖。该结构可以通过在衬底上沉积贱金属层，然后将贵金属沉积在基底金属层的一部分上而形成。通过在高温下氧化，露出的基底金属层被转化为氧化物，而贵金属和其后的母体金属彼此扩散以形成合金。

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