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1. 发明授权

US3984814A Retry method and apparatus for use in a magnetic recording and reproducing system 失效
公开(公告)号：US3984814A
公开(公告)日：1976-10-05
申请号：US536281
申请日：1974-12-24
申请人： Myrl Kennedy Bailey, Jr. , George J. Barlow
发明人： Myrl Kennedy Bailey, Jr. , George J. Barlow
IPC分类号： G06F3/06 , G06F11/14 , G11B5/09 , G11B20/18 , G06F11/00 , G06F13/04
CPC分类号： G06F11/141
摘要： A magnetic tape subsystem includes a peripheral controller which processes data signals of a block received during the reading and recording of the block on a magnetic tape medium by a selected one of a plurality of magnetic tape devices in response to commands received from a data processing system. The peripheral controller includes a data recovery unit having a plurality of storage indicators. These indicators are set by the controller in accordance with the characteristics of the block of data signals recovered by the data recovery unit providing indications of the results of the reading or recording operation performed by the selected magnetic tape device during the peripheral controller's execution of the command. The controller divides up the interval of time of an operation into a number of time periods and monitors the characteristics of the signals of a block which should be received by the data recovery unit during those intervals. During execution of a write command, the controller monitors the tape recording or write operation during different time intervals by monitoring the continuity of the signals recorded by the magnetic tape device indications of which the data recovery unit receives during its performance of a read after write checking operation. The various indicators signal whether the block written was normal or was damaged in addition to signaling the extent of damage which occurred during the writing of the block. Signals representative of the indications are grouped to specify at least two types of error conditions which are tested by the controller to establish whether the command is retryable and nonretryable. The peripheral controller initiates a retry of the command executed only when the indicator signal that the extent of damage has not exceeded a predetermined amount thereby ensuring that only commands which can be retried successfully are re-executed. The controller performs similar monitoring operations during the execution of read commands for establishing signal indications used in determining whether the command should be retried upon detection of errors in the block read by the data recovery unit.

2. 发明授权

US4048481A Diagnostic testing apparatus and method 失效
标题翻译：诊断试验装置及方法
公开(公告)号：US4048481A
公开(公告)日：1977-09-13
申请号：US533743
申请日：1974-12-17
申请人： Myrl Kennedy Bailey, Jr. , George J. Barlow
发明人： Myrl Kennedy Bailey, Jr. , George J. Barlow
IPC分类号： G06F11/22 , G06F11/267 , G11B20/18 , G06F11/04
CPC分类号： G06F11/2215 , G06F11/2221
摘要： A microprogrammable peripheral controller in addition to being operative to controlling plurality of input/output devices in response to commands for processing information signals from a magnetic medium also includes apparatus for independently establishing a minimum operating capability within the controller. The apparatus includes a read-only control store arranged to store microinstructions and a limited number of basic bit patterns. The apparatus in response to an external control signal is operative to condition the data recovery apparatus included in the controller to receive the blocks of synchronization and data patterns arranged in a predetermined format and generated from basic bit patterns obtained from the control store. Simultaneously therewith, the apparatus inhibits normal transfer of information from the magnetic medium. Additionally, a plurality of record error indicator circuits included in the data recovery apparatus are operative to be switched during the processing of each of the blocks of bit patterns transferred through the recovery apparatus. The apparatus further includes comparison circuits which compare the state of the record error indicators with a predicted bit pattern for detecting whether the recovery apparatus is operating properly in processing the block of bit patterns transferred thereto. The states of other indicator storage circuits are modified to signals indicative of conditions occurring during the transfer of the generated bit patterns. The comparison circuits also compare the states of these circuits with a predicted bit pattern as further verification of recovery apparatus operation.
摘要翻译：微程序外设控制器除了响应用于处理来自磁介质的信息信号的命令来操作以控制多个输入/输出设备之外，还包括用于在控制器内独立地建立最小操作能力的装置。该装置包括被设置为存储微指令和有限数量的基本位模式的只读控制存储器。响应于外部控制信号的装置可操作以对包括在控制器中的数据恢复装置进行调节，以接收以预定格式布置并从从控制存储器获得的基本位模式生成的同步块和数据模式。与此同时，该装置禁止从磁介质正常传送信息。此外，包括在数据恢复装置中的多个记录错误指示器电路可操作以在处理通过恢复装置传送的每个位模式块期间被切换。该装置还包括比较电路，其将记录错误指示符的状态与用于检测恢复装置在处理传送到其中的位模式块是否正常工作的预测位模式进行比较。其他指示器存储电路的状态被修改为指示在所生成的位模式的传送期间发生的状况的信号。比较电路还将这些电路的状态与预测位模式进行比较，作为恢复装置操作的进一步验证。

3. 发明授权

US5367697A Means for providing a graceful power shut-down capability in a multiprocessor system having certain processors not inherently having a power shut-down capability 失效
标题翻译：用于在具有某些处理器的多处理器系统中提供优雅的电源关闭能力的手段，该处理器本身不具有电源关闭能力
公开(公告)号：US5367697A
公开(公告)日：1994-11-22
申请号：US781513
申请日：1991-10-22
申请人： George J. Barlow , James W. Keeley
发明人： George J. Barlow , James W. Keeley
IPC分类号： G06F11/00 , G06F1/30
CPC分类号： G06F11/1441
摘要： A multiprocessor computer system includes first processors, second processors, a system management means for performing system management functions, including detecting pending power shut-downs and sending power shut-down messages addressed to each of the first processors warning of pending power shut-downs, and a system bus for communication between the first and second processors and the system management means, including the communication of pending power shut-down messages. The first processors include interrupt handling means responsive to pending power shut-down messages for executing power shut-down routines for placing the first processors into a known state before power termination, but the second processors inherently do not include a power shut-down capability. In each of the second processors, a power shut-down means is provided to place the second processors in a known state before a power termination, including a bus monitor connected from the system bus and responsive to any power shut-down message addressed to a first processor for generating an output indicating the occurrence of a power shut-down message to a first processor. The second processor also includes non-maskable interrupt logic connected from the power shut-down message output of the bus monitor and responsive to the power shut-down message output of the bus monitor for generating a non-maskable interrupt output to the second processor. The second processor is in turn responsive to a non-maskable interrupt output of the non-maskable logic for querying the non-maskable logic to determine the nature of the interrupt, and responsive to the indicated occurrence of a power shut-down message to any first processor for executing a power shut-down routine for placing the second processor in a known state before the termination of power.
摘要翻译：多处理器计算机系统包括第一处理器，第二处理器，用于执行系统管理功能的系统管理装置，包括检测待处理的电源关闭，以及发送寻址到每个第一处理器的停电功率停止消息，以及用于在第一和第二处理器与系统管理装置之间进行通信的系统总线，包括待处理的电力关闭消息的通信。第一处理器包括响应于等待的电源关闭消息的中断处理装置，用于执行电源关闭例程，以在电源终止之前将第一处理器置于已知状态，但是第二处理器固有地不包括电源关闭功能。在每个第二处理器中，提供电源关闭装置以在电源终止之前将第二处理器置于已知状态，包括从系统总线连接的总线监视器，并且响应于任何电源关闭消息第一处理器，用于产生指示向第一处理器发出电力关闭消息的输出。第二处理器还包括从总线监视器的电源关闭消息输出连接的不可屏蔽中断逻辑，并且响应于总线监视器的电源关闭消息输出，以产生对第二处理器的不可屏蔽中断输出。第二处理器又响应于不可屏蔽逻辑的不可屏蔽中断输出，用于查询不可屏蔽逻辑以确定中断的性质，并且响应于所指示的电力关闭消息发生到任何第一处理器，用于在电源结束之前执行用于将第二处理器置于已知状态的电源关闭程序。

4. 发明授权

US5241629A Method and apparatus for a high performance round robin distributed bus priority network 失效
标题翻译：高性能循环分布式总线优先级网络的方法和装置
公开(公告)号：US5241629A
公开(公告)日：1993-08-31
申请号：US593407
申请日：1990-10-05
申请人： George J. Barlow , Donald L. Smith
发明人： George J. Barlow , Donald L. Smith
IPC分类号： G06F13/37
CPC分类号： G06F13/37
摘要： A multiprocessor system includes a plurality of identical central subsystem (CSS) units, a plurality of memory subsystem units and input/output units which connect in common to a system bus. Requests are transferred between a pair of units on a priority basis defined by a distributed bus priority network included as part of the system bus. Each CSS unit includes cycle stealer logic circuits which grant bus cycles on a round robin basis. The cycle stealer logic circuits are connected to receive high priority request signals from the network and refuse acceptance of a cycle granted to such CSS unit as a low priority requester thereby passing it along to a next lower priority CSS unit.
摘要翻译：多处理器系统包括多个相同的中央子系统（CSS）单元，多个存储器子系统单元和共同连接到系统总线的输入/输出单元。请求在由作为系统总线的一部分包括的分布式总线优先级网络所限定的优先级基础上在一对单元之间传送。每个CSS单元包括循环窃取逻辑电路，循环窃取逻辑电路以轮询为基础授予总线周期。连接循环窃取逻辑电路以接收来自网络的高优先级请求信号，并拒绝接受授予诸如低优先级请求者的这种CSS单元的周期，从而将其沿着下一个较低优先级的CSS单元传递。

5. 发明授权

US4833601A Cache resiliency in processing a variety of address faults 失效
标题翻译：缓存弹性处理各种地址故障
公开(公告)号：US4833601A
公开(公告)日：1989-05-23
申请号：US55577
申请日：1987-05-28
申请人： George J. Barlow , James W. Keeley , Chester M. Nibby, Jr.
发明人： George J. Barlow , James W. Keeley , Chester M. Nibby, Jr.
IPC分类号： G06F11/00 , G06F11/07 , G06F11/14 , G06F11/16 , G06F12/08 , G06F12/10
CPC分类号： G06F11/073 , G06F11/0724 , G06F11/0793 , G06F12/0815 , G06F11/0757 , G06F11/141
摘要： A cache memory subsystem has multilevel directory memory and buffer memory pipeline stages shared by at least a pair of independently operated central processing units and a first in first out (FIFO) device which connects to a system bus of a tightly coupled data processing system. The cache subsystem includes a number of programmable control circuits which are connected to receive signals representative of the type of operations performable by the cache subsystem. These signals are logically combined for generating an output signal indicating whether or not the contents of the directiory memory should be flushed when any one of a number of types of address or system faults has been detected in order to maintain cache coherency.

6. 发明授权

US4763243A Resilient bus system 失效
标题翻译：弹性总线系统
公开(公告)号：US4763243A
公开(公告)日：1988-08-09
申请号：US623264
申请日：1984-06-21
申请人： George J. Barlow , James W. Keeley
发明人： George J. Barlow , James W. Keeley
IPC分类号： G06F11/00 , G06F13/42 , G06F13/14 , G06F13/38
CPC分类号： G06F13/4213 , G06F11/00
摘要： A data processing system includes a plurality of units which are coupled to transfer requests including data, command and integrity signals between units over a system bus during allocated bus transfer cycles. Each unit includes response apparatus for acknowledging requests received from other units. Each of a number of units further includes retry apparatus and checking apparatus for verifying that all of the parts of a request received from such unit over the bus are valid. When less than all of the parts of the request are detected as valid, the receiving unit does not accept the request and inhibits its response apparatus from generating a response. This prevents damage to system integrity and permits each unit with retry apparatus to retry the request during a subsequent bus transfer cycle.
摘要翻译：数据处理系统包括多个单元，其被耦合以在分配的总线传送周期期间通过系统总线在单元之间传送包括数据，命令和完整性信号的请求。每个单元包括用于确认从其他单元接收的请求的响应装置。多个单元中的每一个还包括重试设备和检查装置，用于验证从总线上接收到的单元的所有请求的所有部分都是有效的。当小于所有请求的部分被检测为有效时，接收单元不接受该请求并且禁止其响应装置产生响应。这样可以防止系统完整性受到损害，并允许每个重试设备的单元在随后的总线传输周期内重试该请求。

7. 发明授权

US4096569A Data processing system having distributed priority network with logic for deactivating information transfer requests 失效
标题翻译：具有分布式优先级网络的数据处理系统具有用于停用信息传送请求的逻辑
公开(公告)号：US4096569A
公开(公告)日：1978-06-20
申请号：US754480
申请日：1976-12-27
申请人： George J. Barlow
发明人： George J. Barlow
IPC分类号： G06F13/368 , G06F3/04
CPC分类号： G06F13/368
摘要： A common electrical bus for coupling a plurality of units in a data processing system for the transfer of information therebetween. The units are coupled in a priority arrangement which is distributed thereby providing priority logic in each of the units and allowing bus transfer cycles to be generated in an asynchronous manner. Each of the units includes priority logic which includes logic elements for requesting a bus cycle, such request being granted if no other higher priority unit has also requested a bus cycle. The request for and an indication of the grant of the bus cycle are stored in each unit so requesting and being granted the bus cycle respectively, only one such unit being capable of having the grant of a bus cycle at any given time, whereas any number of such units may have its request pending at any particular time. Upon completion of the bus cycle, the priority logic is coupled to deactivate the indication of the grant of the bus cycle, and in response thereto, to deactivate the request of the particular unit which has just had access to the bus.
摘要翻译：一种用于耦合数据处理系统中的多个单元以用于在其间传送信息的公共电气总线。这些单元以分配的优先级布置耦合，从而在每个单元中提供优先级逻辑，并允许以异步方式生成总线传送周期。每个单元包括优先级逻辑，其包括用于请求总线周期的逻辑元件，如果没有其他较高优先级单元也请求了总线周期，则该请求被授权。总线周期的请求和授权指示被存储在每个单元中，从而请求并被分配给总线周期，只有一个这样的单元能够在任何给定的时间允许总线周期，而任何数量的这些单位可能会在任何特定的时间要求其请求。在总线周期完成时，优先级逻辑被耦合以去激活总线周期授权的指示，并且响应于此，去激活刚刚访问总线的特定单元的请求。

8. 发明授权

US5243702A Minimum contention processor and system bus system 失效
标题翻译：最小限度处理器和系统总线系统
公开(公告)号：US5243702A
公开(公告)日：1993-09-07
申请号：US593437
申请日：1990-10-05
申请人： George J. Barlow , Donald L. Smith
发明人： George J. Barlow , Donald L. Smith
IPC分类号： G06F13/362 , G06F13/36 , G06F13/368 , G06F13/376
CPC分类号： G06F13/376
摘要： A multiprocessor system includes a plurality of central subsystem (CSS) units, a plurality of memory units and input/output units which connect in common to a system bus for transferring requests between a pair of units on a priority basis defined by a distributed bus priority network included as part of the system bus. A private bus (P bus) connects all of the CSS units and memory units in common for high speed block data transfers. Each CSS unit includes input circuits which couple to the priority network for detecting when the system bus is in an idle state. P bus logic circuits couple to the P bus and generate a transfer request in response to a request from its CSS unit only when the P bus is detected to be in an idle state. The idle signals from both buses are used to generate a system bus request for P bus access only when both buses are in an idle state so as to eliminate the need to contend for system bus use.

9. 发明授权

US5099420A Method and apparatus for limiting the utilization of an asynchronous bus with distributed controlled access 失效
标题翻译：限制使用分布式控制访问的异步总线的方法和装置
公开(公告)号：US5099420A
公开(公告)日：1992-03-24
申请号：US295639
申请日：1989-01-10
申请人： George J. Barlow , John W. Bradley , Edward F. Getson, Jr.
发明人： George J. Barlow , John W. Bradley , Edward F. Getson, Jr.
IPC分类号： G06F13/368
CPC分类号： G06F13/368
摘要： A plurality of units which are coupled to transfer requests, transfer data over an asynchronous bus network during allocated bus transfer cycles. The network has a tie-breaking bus priority network which is distributed to a common interface portion of each of the plurality of units and grants bus cycles and resolves simultaneous requests on a priority basis. At least one unit includes bus saturation detection apparatus included within its common interface portion for monitoring bus activity over established intervals of time. The detection of the occurrence of at least one available cycle over the given interval of time signals that the bus network is not in a saturated state. When the indicator specifies that the bus network is saturated, the unit throttles down its operation by increasing the amount of time between issuing data requests. Throttling continues until the bus is no longer being saturated.

10. 发明授权

US4764862A Resilient bus system 失效
标题翻译：弹性总线系统
公开(公告)号：US4764862A
公开(公告)日：1988-08-16
申请号：US717201
申请日：1985-03-28
申请人： George J. Barlow , James W. Keeley
发明人： George J. Barlow , James W. Keeley
IPC分类号： G06F11/00 , G06F13/42 , G06F13/14
CPC分类号： G06F13/4213 , G06F11/00
摘要： A data processing system includes a plurality of units which are coupled to transfer requests including data, command and integrity signals between units over a system bus during allocated bus transfer cycles. Each unit includes response apparatus for acknowledging requests received from other units. Each of a number of units further includes retry apparatus and like checking apparatus for verifying that the different parts of a request received from such unit over the bus are valid based upon the states of accompanying function identification signals. When less than all of the parts of the request defined as requiring verification are detected as valid, the receiving unit does not accept the request and inhibits its response apparatus from generating a response. This prevents damage to system integrity and permits each unit with retry apparatus to retry the request during a subsequent bus transfer cycle.
摘要翻译：数据处理系统包括多个单元，其被耦合以在分配的总线传送周期期间通过系统总线在单元之间传送包括数据，命令和完整性信号的请求。每个单元包括用于确认从其他单元接收的请求的响应装置。多个单元中的每一个还包括重试设备和类似的检查装置，用于根据伴随的功能识别信号的状态来验证从该单元接收的请求的不同部分是否有效。当被检测为需要验证的请求的全部部分被检测为有效时，接收单元不接受该请求并禁止其响应装置产生响应。这样可以防止系统完整性受到损害，并允许每个重试设备的单元在随后的总线传输周期内重试该请求。

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