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1. 发明授权

US07689806B2 Method and system to indicate an exception-triggering page within a microprocessor 有权
标题翻译：用于指示微处理器内的异常触发页面的方法和系统
公开(公告)号：US07689806B2
公开(公告)日：2010-03-30
申请号：US11487284
申请日：2006-07-14
申请人： Lucian Codrescu , Erich Plondke , Muhammad Ahmed , Vijaya Kumar Janjanam
发明人： Lucian Codrescu , Erich Plondke , Muhammad Ahmed , Vijaya Kumar Janjanam
IPC分类号： G06F12/00 , G06F9/00
CPC分类号： G06F12/1009 , G06F12/1027 , G06F2212/684
摘要： A method and system to indicate which page within a software-managed page table triggers an exception within a microprocessor, such as, for example, a digital signal processor, wherein a software-managed translation lookaside buffer (TLB) module receives a virtual address produced by an instruction within a Very Long Instruction Word (VLIW) packet, such as, for example, a fetch instruction, and further compares the virtual address to each stored TLB entry. If a match exists, then the TLB module outputs a corresponding mapped physical address for the instruction. Otherwise, if the VLIW packet spans two pages, where a first page is present as a TLB entry within the TLB module and the second page is missing from the stored TLB entries, an indication bit within a data field of a control register is set to identify the TLB miss exception to a software management unit. The software management unit retrieves the indication bit information from the register and further performs a page table look-up within the software-managed page table using the indication bit information in order to retrieve the missing page information. Subsequently, the missing page information is written into a new TLB entry within the TLB module for subsequent virtual address translation and execution of the packet of instructions.
摘要翻译：一种方法和系统，用于指示软件管理的页表内的哪个页面在微处理器（例如数字信号处理器）内触发异常，其中软件管理的翻译后备缓冲器（TLB）模块接收产生的虚拟地址通过超长指令字（VLIW）分组（例如，取指令）中的指令，并且还将虚拟地址与每个存储的TLB条目进行比较。如果匹配存在，则TLB模块输出相应的映射物理地址。否则，如果VLIW分组跨越两页，其中第一页作为TLB模块中的TLB条目存在，并且第二页从存储的TLB条目丢失，则将控制寄存器的数据字段内的指示位设置为识别软件管理单元的TLB错误异常。软件管理单元从寄存器检索指示位信息，并使用指示位信息进一步在软件管理的页表中执行页表查找，以便检索丢失页信息。随后，丢失的页面信息被写入TLB模块中的新TLB条目，用于随后的虚拟地址转换和指令分组的执行。

2. 发明授权

US07523295B2 Processor and method of grouping and executing dependent instructions in a packet 有权
标题翻译：分组和执行分组中的相关指令的处理器和方法
公开(公告)号：US07523295B2
公开(公告)日：2009-04-21
申请号：US11086475
申请日：2005-03-21
申请人： Lucian Codrescu , Erich Plondke , Muhammad Ahmed , Sujat Jamil , William C. Anderson
发明人： Lucian Codrescu , Erich Plondke , Muhammad Ahmed , Sujat Jamil , William C. Anderson
IPC分类号： G06F9/30 , G06F9/40
CPC分类号： G06F9/3885 , G06F9/3851 , G06F9/3853
摘要： An interleaved multithreading pipeline operating method comprises reading an instruction packet containing at least two instructions, steering a first instruction of the instruction packet to a first execution unit for execution and generating a first result, steering a second instruction of the instruction packet to a second execution unit for execution using the first result and generating a second result, and storing the second result.
摘要翻译：交错多线程流水线操作方法包括读取包含至少两个指令的指令分组，将指令分组的第一指令转向第一执行单元以执行并产生第一结果，将指令分组的第二指令转向第二执行使用第一结果执行的单元并产生第二结果，并存储第二结果。

3. 发明申请

US20070271416A1 Method and system for maximum residency replacement of cache memory 有权
标题翻译：用于高速缓存存储器最大驻留替换的方法和系统
公开(公告)号：US20070271416A1
公开(公告)日：2007-11-22
申请号：US11437501
申请日：2006-05-17
申请人： Muhammad Ahmed
发明人： Muhammad Ahmed
IPC分类号： G06F12/00
CPC分类号： G06F12/123 , G06F12/0859 , G06F12/126 , G06F12/128 , Y02D10/13
摘要： Techniques for use in CDMA-based products and services, including replacing cache memory allocation so as to maximize residency of a plurality of set ways following a tag-miss allocation. Herein, steps forming a first-in, first-out (FIFO) replacement listing of victim ways for the cache memory, wherein the depth of the FIFO replacement listing approximately equals the number of ways in the cache set. The method and system place a victim way on the FIFO replacement listing only in the event that a tag-miss results in a tag-miss allocation, the victim way is placed at the tail of the FIFO replacement listing after any previously selected victim way. Use of a victim way on the FIFO replacement listing is prevented in the event of an incomplete prior allocation of the victim way by, for example, stalling a reuse request until such initial allocation of the victim way completes or replaying a reuse request until such initial allocation of the victim way completes.
摘要翻译：在基于CDMA的产品和服务中使用的技术，包括替换高速缓冲存储器分配，以便在标签错失分配之后最大化多个设置路径的驻留。这里，形成用于高速缓冲存储器的受害方式的先入先出（FIFO）替换列表的步骤，其中FIFO替换列表的深度近似等于高速缓存集中的路数。只有在标签错失导致标签错失分配的情况下，该方法和系统才会将受害者的方式置于FIFO替换列表中，受害者的方式将放置在先前选择的受害方式之后的FIFO替换列表的尾部。在受害者方式的不完整的先前分配的情况下，通过停止重用请求直到受害方的初始分配完成或重放重用请求直到这样的初始化受害方的分配完成。

4. 发明申请

US20070266229A1 Encoding hardware end loop information onto an instruction 审中-公开
标题翻译：将硬件结束循环信息编码到指令上
公开(公告)号：US20070266229A1
公开(公告)日：2007-11-15
申请号：US11431732
申请日：2006-05-10
申请人： Erich Plondke , Robert Lester , Lucian Codrescu , Muhammad Ahmed
发明人： Erich Plondke , Robert Lester , Lucian Codrescu , Muhammad Ahmed
IPC分类号： G06F9/44
CPC分类号： G06F9/30149 , G06F9/325 , G06F9/3853 , G06F9/3885
摘要： Methods and apparatus for encoding information regarding a hardware loop of a set of packets is provided, each packet (400) containing instructions. The information is encoded into one or more bits of at least one instruction (300) in the set of packets. The information may indicate whether a packet is or is not an end packet of the loop. Information regarding two hardware loops may be encoded where information regarding the first loop is encoded into an instruction at a first position in each packet and information regarding the second loop is encoded into an instruction at a second position in each packet. End instruction information may be encoded into an instruction not having encoded loop information at the same bit positions reserved for the encoded loop information, the end instruction information indicating whether an instruction is the last instruction of a packet and the length of a packet.
摘要翻译：提供了用于编码关于一组分组的硬件循环的信息的方法和装置，每个分组（400）包含指令。信息被编码成该组分组中的至少一个指令（300）的一个或多个位。信息可以指示分组是否是循环的结束分组。关于两个硬件循环的信息可以被编码，其中关于第一循环的信息被编码为每个分组中的第一位置处的指令，并且关于第二循环的信息被编码为每个分组中的第二位置处的指令。结束指令信息可以被编码为在编码环路信息保留的相同位位置处不具有编码环路信息的指令，表示指令是分组的最后指令还是分组长度的结束指令信息。

5. 发明申请

US20060268592A1 Low power microprocessor cache memory and method of operation 有权
公开(公告)号：US20060268592A1
公开(公告)日：2006-11-30
申请号：US11137183
申请日：2005-05-25
申请人： Baker Mohammad , Muhammad Ahmed , Paul Bassett , Sujat Jamil , Ajay Ingle
发明人： Baker Mohammad , Muhammad Ahmed , Paul Bassett , Sujat Jamil , Ajay Ingle
IPC分类号： G11C15/00
CPC分类号： G06F12/0895 , G06F12/0864 , G06F12/0893
摘要： Techniques for processing transmissions in a communications (e.g., CDMA) system including the use of a digital signal processor. The digital signal processor includes a cache memory system and associates a plurality of cache memory match lines with addressable memory lines of an addressable memory. Each of the cache memory match lines associates with one of corresponding sets of the cache memory. The method and system maintain each of the cache memory match lines at a low voltage. Once the digital signal processor initiates a search of the cache memory for retrieving data from a selected one of the corresponding sets of the cache memory, a match line drive circuit drives one of the cache memory match lines from a low voltage to a high voltage. The selected one of the cache memory match lines corresponds to the selected one of the corresponding sets of the cache memory. The digital signal processor compares the selected one of the cache memory match lines to an associated one of the addressable memory lines. Following the comparison step, the process returns the one of the cache memory match lines to the low voltage.

6. 发明申请

US20060230259A1 Instruction memory unit and method of operation 有权
标题翻译：指令存储单元和操作方法
公开(公告)号：US20060230259A1
公开(公告)日：2006-10-12
申请号：US11104115
申请日：2005-04-11
申请人： Muhammad Ahmed , Lucian Codrescu , Erich Plondke , William Anderson , Robert Lester , Phillip Jones
发明人： Muhammad Ahmed , Lucian Codrescu , Erich Plondke , William Anderson , Robert Lester , Phillip Jones
IPC分类号： G06F9/00
CPC分类号： G06F9/325 , G06F9/3802 , G06F9/3804 , G06F9/381
摘要： An instruction memory unit comprises a first memory structure operable to store program instructions, and a second memory structure operable to store program instructions fetched from the first memory structure, and to issue stored program instructions for execution. The second memory structure is operable to identify a repeated issuance of a forward program redirect construct, and issue a next program instruction already stored in the second memory structure if a resolution of the forward branching instruction is identical to a last resolution of the same. The second memory structure is further operable to issue a backward program redirect construct, determine whether a target instruction is stored in the second memory structure, issue the target instruction if the target instruction is stored in the second memory structure, and fetch the target instruction from the first memory structure if the target instruction is not stored in the second memory structure.
摘要翻译：指令存储单元包括可操作以存储程序指令的第一存储器结构，以及可操作以存储从第一存储器结构提取的程序指令并且发出用于执行的存储的程序指令的第二存储器结构。如果前向分支指令的分辨率与其最后一个分辨率相同，则第二存储器结构可操作以识别正向程序重定向构造的重复发出，并发出已经存储在第二存储器结构中的下一个程序指令。第二存储器结构还可操作以发出反向程序重定向结构，确定目标指令是否存储在第二存储器结构中，如果目标指令存储在第二存储器结构中，则发出目标指令，并从如果目标指令没有存储在第二存储器结构中的第一存储器结构。

7. 发明申请

US20060224862A1 Mixed superscalar and VLIW instruction issuing and processing method and system 有权
公开(公告)号：US20060224862A1
公开(公告)日：2006-10-05
申请号：US11093375
申请日：2005-03-29
申请人： Muhammad Ahmed , Erich Plondke , Lucian Codrescu , William Anderson
发明人： Muhammad Ahmed , Erich Plondke , Lucian Codrescu , William Anderson
IPC分类号： G06F9/30
CPC分类号： G06F9/3853 , G06F9/3836 , G06F9/3838 , G06F9/3857
摘要： Techniques for processing transmissions in a communications (e.g., CDMA) system. A method and system for issuing and executing mixed architecture instructions in a multiple-issue digital signal processor receives in a mixed instruction listing a plurality of digital signal processor instructions. The plurality of digital signal processor instructions includes a plurality of parallel executable instructions (e.g., VLIW instructions or instruction packets) mixed among a plurality of series executable instructions (e.g., superscalar instructions). The series executable instructions are associated by various instruction dependencies. The method and system further identify in the mixed instruction listing the plurality of parallel executable instructions. Once identified, the parallel executable instructions are first executed in parallel irrespective of any such instruction's relative order in the mixed instruction listing. Then, the series executable instructions are executed serially according to said various instruction dependencies.

8. 发明授权

US08713286B2 Register files for a digital signal processor operating in an interleaved multi-threaded environment 有权
标题翻译：为交错多线程环境中的数字信号处理器注册文件
公开(公告)号：US08713286B2
公开(公告)日：2014-04-29
申请号：US11115916
申请日：2005-04-26
申请人： Muhammad Ahmed , Erich Plondke , Lucian Codrescu , William C. Anderson
发明人： Muhammad Ahmed , Erich Plondke , Lucian Codrescu , William C. Anderson
IPC分类号： G06F7/57
CPC分类号： G06F9/30149 , G06F9/3012 , G06F9/3851 , G06F9/3885
摘要： A processor device is disclosed and includes a memory and a sequencer that is responsive to the memory. The sequencer supports very long instruction word (VLIW) type instructions and at least one VLIW instruction packet uses a number of operands during execution. The processor device further includes a plurality of instruction execution units responsive to the sequencer and a plurality of register files. Each of the plurality of register files includes a plurality of registers and the plurality of register files are coupled to the plurality of instruction execution units. Further, each of the plurality of register files includes a number of data read ports and the number of data read ports of each of the plurality of register files is less than the number of operands used by the at least one VLIW instruction packet.
摘要翻译：公开了处理器设备，并且包括响应于存储器的存储器和定序器。定序器支持非常长的指令字（VLIW）类型指令，并且至少一个VLIW指令分组在执行期间使用多个操作数。处理器设备还包括响应于定序器的多个指令执行单元和多个寄存器文件。多个寄存器文件中的每一个包括多个寄存器，并且多个寄存器文件耦合到多个指令执行单元。此外，多个寄存器文件中的每一个包括多个数据读取端口，并且多个寄存器堆栈中的每一个的数据读取端口的数量小于由至少一个VLIW指令包使用的操作数的数量。

9. 发明申请

US20120083912A1 ARITHMETIC LOGIC AND SHIFTING DEVICE FOR USE IN A PROCESSOR 有权
标题翻译：用于处理器的算术逻辑和移位装置
公开(公告)号：US20120083912A1
公开(公告)日：2012-04-05
申请号：US13314530
申请日：2011-12-08
申请人： Muhammad Ahmed , Ajay Anant Ingle , Sujat Jamil
发明人： Muhammad Ahmed , Ajay Anant Ingle , Sujat Jamil
IPC分类号： G06F17/00 , G06F9/305 , G06F9/38 , G06F9/302 , G06F9/315
CPC分类号： G06F9/30181 , G06F9/30032 , G06F9/3012 , G06F9/30189 , G06F9/3802 , G06F9/3851 , G06F9/3885
摘要： An arithmetic logic and shifting device is disclosed and includes an arithmetic logic unit that has a first input to receive a first operand from a first register port, a second input to receive a second operand from a second register port, and an output to selectively provide a memory address to a memory unit in a first mode of operation and to selectively provide an arithmetic output in a second mode of operation. Further, the arithmetic logic and shifting device includes a programmable shifter device that has a first input to receive data from the memory unit, a second input to receive the arithmetic output, a third input to receive an operation code of a computer execution instruction, and a shifted output to provide shifted data.
摘要翻译：公开了算术逻辑和移位装置，并且包括算术逻辑单元，该算术逻辑单元具有从第一寄存器端口接收第一操作数的第一输入端，从第二寄存器端口接收第二操作数的第二输入端和选择性地提供以第一操作模式向存储器单元提供存储器地址，并且在第二操作模式中选择性地提供算术输出。此外，算术逻辑和移位装置包括可编程移位器装置，其具有用于从存储器单元接收数据的第一输入端，用于接收算术输出的第二输入端，接收计算机执行指令的操作码的第三输入端，以及移位输出以提供移位数据。

10. 发明授权

US07917907B2 Method and system for variable thread allocation and switching in a multithreaded processor 有权
标题翻译：多线程处理器中可变线程分配和切换的方法和系统
公开(公告)号：US07917907B2
公开(公告)日：2011-03-29
申请号：US11089474
申请日：2005-03-23
申请人： Muhammad Ahmed , Sujat Jamil , Erich Plondke , Lucian Codrescu , William C. Anderson
发明人： Muhammad Ahmed , Sujat Jamil , Erich Plondke , Lucian Codrescu , William C. Anderson
IPC分类号： G06F9/46 , G06F15/76
CPC分类号： G06F9/3851
摘要： Techniques for processing transmissions in a communications (e.g., CDMA) system. An aspect of the disclosed subject matter includes a method for processing instructions on a multithreaded processor. The multithreaded processor processes a plurality of threads via a plurality of processor pipelines. The method includes the step determining the operating frequency, F, at which the multithreaded processor operates. Then, the method determines a variable thread switch timeout state for triggering the switching of the processing among the plurality of active threads. The variable thread switch timeout state varies so that each of the plurality of active threads operates at a frequency of an allocated portion of the frequency, F. The allocated portion at which the active threads operate is determined at least in part in order to optimize the operation of the multithreaded processor. The method further switches the processing from a first one of the active threads to a next one of the active threads upon the occurrence of the variable thread switch timeout state.
摘要翻译：用于在通信（例如，CDMA）系统中处理传输的技术。所公开的主题的一个方面包括用于在多线程处理器上处理指令的方法。多线程处理器经由多个处理器管线处理多个线程。该方法包括确定多线程处理器工作的工作频率F的步骤。然后，该方法确定用于触发多个活动线程之间的处理切换的可变线程切换超时状态。可变线程切换超时状态改变，使得多个活动线程中的每一个以所分配的频率部分F的频率运行。活动线程运行的分配部分至少部分地被确定，以便优化操作多线程处理器。在发生可变线程切换超时状态时，该方法还将处理从主动线程中的第一个切换到下一个活动线程。

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