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1. 发明申请

US20060268592A1 Low power microprocessor cache memory and method of operation 有权
公开(公告)号：US20060268592A1
公开(公告)日：2006-11-30
申请号：US11137183
申请日：2005-05-25
申请人： Baker Mohammad , Muhammad Ahmed , Paul Bassett , Sujat Jamil , Ajay Ingle
发明人： Baker Mohammad , Muhammad Ahmed , Paul Bassett , Sujat Jamil , Ajay Ingle
IPC分类号： G11C15/00
CPC分类号： G06F12/0895 , G06F12/0864 , G06F12/0893
摘要： Techniques for processing transmissions in a communications (e.g., CDMA) system including the use of a digital signal processor. The digital signal processor includes a cache memory system and associates a plurality of cache memory match lines with addressable memory lines of an addressable memory. Each of the cache memory match lines associates with one of corresponding sets of the cache memory. The method and system maintain each of the cache memory match lines at a low voltage. Once the digital signal processor initiates a search of the cache memory for retrieving data from a selected one of the corresponding sets of the cache memory, a match line drive circuit drives one of the cache memory match lines from a low voltage to a high voltage. The selected one of the cache memory match lines corresponds to the selected one of the corresponding sets of the cache memory. The digital signal processor compares the selected one of the cache memory match lines to an associated one of the addressable memory lines. Following the comparison step, the process returns the one of the cache memory match lines to the low voltage.

2. 发明授权

US07620778B2 Low power microprocessor cache memory and method of operation 有权
标题翻译：低功耗微处理器缓存存储器和操作方法
公开(公告)号：US07620778B2
公开(公告)日：2009-11-17
申请号：US11137183
申请日：2005-05-25
申请人： Baker Mohammad , Muhammad Ahmed , Paul Bassett , Sujat Jamil , Ajay Anant Ingle
发明人： Baker Mohammad , Muhammad Ahmed , Paul Bassett , Sujat Jamil , Ajay Anant Ingle
IPC分类号： G06F12/00
CPC分类号： G06F12/0895 , G06F12/0864 , G06F12/0893
摘要： Techniques for processing transmissions in a communications (e.g., CDMA) system including the use of a digital signal processor. The digital signal processor includes a cache memory system and associates a plurality of cache memory match lines with addressable memory lines of an addressable memory. Each of the cache memory match lines associates with one of corresponding sets of the cache memory. The method and system maintain each of the cache memory match lines at a low voltage. Once the digital signal processor initiates a search of the cache memory for retrieving data from a selected one of the corresponding sets of the cache memory, a match line drive circuit drives one of the cache memory match lines from a low voltage to a high voltage. The selected one of the cache memory match lines corresponds to the selected one of the corresponding sets of the cache memory. The digital signal processor compares the selected one of the cache memory match lines to an associated one of the addressable memory lines. Following the comparison step, the process returns the one of the cache memory match lines to the low voltage.
摘要翻译：用于处理包括使用数字信号处理器的通信（例如，CDMA）系统中的传输的技术。数字信号处理器包括高速缓冲存储器系统，并将多个高速缓冲存储器匹配线与可寻址存储器的可寻址存储器线相关联。每个高速缓存存储器匹配行与高速缓冲存储器的相应组中的一个相关联。该方法和系统将每个缓存存储器匹配线保持在低电压。一旦数字信号处理器启动对高速缓冲存储器的搜索，以从相应的高速缓冲存储器组中的选定的一个中选出一个数据，则匹配线驱动电路将高速缓冲存储器匹配线之一从低电压驱动到高电压。高速缓存存储器匹配行中所选择的一个对应于高速缓冲存储器的所选择的相应组中的一个。数字信号处理器将所选择的一个高速缓冲存储器匹配线与可寻址存储器线中的相关联的一个进行比较。在比较步骤之后，该过程将高速缓存存储器匹配行之一返回到低电压。

3. 发明申请

US20090058463A1 Sequential Circuit Element Including A Single Clocked Transistor 有权
标题翻译：包括单时钟晶体管的顺序电路元件
公开(公告)号：US20090058463A1
公开(公告)日：2009-03-05
申请号：US11845950
申请日：2007-08-28
申请人： Martin Saint-Laurent , Baker Mohammad , Paul Bassett
发明人： Martin Saint-Laurent , Baker Mohammad , Paul Bassett
IPC分类号： H03K3/02
CPC分类号： H03K3/356121 , G06F9/3869
摘要： A method is disclosed that includes propagating data via a first data path of a sequential circuit element in response to a clock signal received at a single clocked transistor of the sequential circuit element. The method also includes retaining information related to the data propagated via the first path at a retention circuit element of a second data path, where the first data path includes a first transistor that is responsive to an output of the single clocked transistor. The first transistor has a higher current flow capacity than a second transistor associated with the second data path.
摘要翻译：公开了一种方法，其包括响应于在顺序电路元件的单个时钟晶体管处接收的时钟信号，经由时序电路元件的第一数据路径传播数据。该方法还包括保持与在第二数据路径的保持电路元件处经由第一路径传播的数据有关的信息，其中第一数据路径包括响应于单个时钟晶体管的输出的第一晶体管。第一晶体管具有比与第二数据路径相关联的第二晶体管更高的电流流动能力。

4. 发明授权

US07466620B2 System and method for low power wordline logic for a memory 有权
标题翻译：用于存储器的低功率字线逻辑的系统和方法
公开(公告)号：US07466620B2
公开(公告)日：2008-12-16
申请号：US11402483
申请日：2006-04-11
申请人： Baker Mohammad , Paul Bassett
发明人： Baker Mohammad , Paul Bassett
IPC分类号： G11C8/00
CPC分类号： G11C5/147 , G11C8/08 , G11C8/10
摘要： A method of reducing power consumption of a memory is provided. A request is received to access a memory device, including a decoder, a plurality of wordline drivers and a plurality of wordlines. Each wordline is associated with a wordline driver of the plurality of wordline drivers. The request is decoded by a decoder to determine an address associated with the request. A wordline driver of the plurality of wordline drivers is selectively powered to access the address of the memory device, where the wordline driver is associated with a particular wordline of the plurality of wordlines that is related to the address bits, without powering other wordlines of the plurality of wordlines.
摘要翻译：提供了降低存储器功耗的方法。接收到访问包括解码器，多个字线驱动器和多个字线的存储器设备的请求。每个字线与多个字线驱动器的字线驱动器相关联。该请求由解码器解码以确定与请求相关联的地址。选择性地供电多个字线驱动器的字线驱动器以访问存储器件的地址，其中字线驱动器与多个字线中与地址位相关的特定字线相关联，而不为其提供其他字线多个字线。

5. 发明申请

US20080231322A1 Circuit Device and Method of Controlling a Voltage Swing 有权
标题翻译：控制电压摆动的电路装置及方法
公开(公告)号：US20080231322A1
公开(公告)日：2008-09-25
申请号：US11843696
申请日：2007-08-23
申请人： Baker Mohammad , Martin Saint-Laurent , Paul Bassett
发明人： Baker Mohammad , Martin Saint-Laurent , Paul Bassett
IPC分类号： H03K19/0175
CPC分类号： H03K19/0016 , H03K19/001
摘要： In particular illustrative embodiments, circuit devices and methods of controlling a voltage swing are disclosed. The method includes receiving a signal at an input of a digital circuit device including a capacitive node. The method also includes selectively activating a voltage level adjustment element to regulate an electrical discharge path from the capacitive node to an electrical ground to prevent complete discharge of the capacitive node. In a particular illustrative embodiment, the received signal may be a clock signal.
摘要翻译：在具体说明性实施例中，公开了电路装置和控制电压摆幅的方法。该方法包括在包括电容性节点的数字电路装置的输入处接收信号。该方法还包括选择性地激活电压电平调节元件以调节从电容节点到电接地的放电路径，以防止电容性节点的完全放电。在特定说明性实施例中，接收信号可以是时钟信号。

6. 发明授权

US07567096B2 Circuit device and method of controlling a voltage swing 有权
标题翻译：控制电压摆幅的电路装置及方法
公开(公告)号：US07567096B2
公开(公告)日：2009-07-28
申请号：US11843696
申请日：2007-08-23
申请人： Baker Mohammad , Martin Saint-Laurent , Paul Bassett
发明人： Baker Mohammad , Martin Saint-Laurent , Paul Bassett
IPC分类号： H03K19/096
CPC分类号： H03K19/0016 , H03K19/001
摘要： In particular illustrative embodiments, circuit devices and methods of controlling a voltage swing are disclosed. The method includes receiving a signal at an input of a digital circuit device including a capacitive node. The method also includes selectively activating a voltage level adjustment element to regulate an electrical discharge path from the capacitive node to an electrical ground to prevent complete discharge of the capacitive node. In a particular illustrative embodiment, the received signal may be a clock signal.
摘要翻译：在具体说明性实施例中，公开了电路装置和控制电压摆幅的方法。该方法包括在包括电容性节点的数字电路装置的输入处接收信号。该方法还包括选择性地激活电压电平调节元件以调节从电容节点到电接地的放电路径，以防止电容性节点的完全放电。在特定说明性实施例中，接收信号可以是时钟信号。

7. 发明授权

US07746137B2 Sequential circuit element including a single clocked transistor 有权
标题翻译：顺序电路元件包括单个时钟晶体管
公开(公告)号：US07746137B2
公开(公告)日：2010-06-29
申请号：US11845950
申请日：2007-08-28
申请人： Martin Saint-Laurent , Baker Mohammad , Paul Bassett
发明人： Martin Saint-Laurent , Baker Mohammad , Paul Bassett
IPC分类号： H03K3/356
CPC分类号： H03K3/356121 , G06F9/3869
摘要： A method is disclosed that includes propagating data via a first data path of a sequential circuit element in response to a clock signal received at a single clocked transistor of the sequential circuit element. The method also includes retaining information related to the data propagated via the first path at a retention circuit element of a second data path, where the first data path includes a first transistor that is responsive to an output of the single clocked transistor. The first transistor has a higher current flow capacity than a second transistor associated with the second data path.
摘要翻译：公开了一种方法，其包括响应于在顺序电路元件的单个时钟晶体管处接收的时钟信号，经由时序电路元件的第一数据路径传播数据。该方法还包括保持与在第二数据路径的保持电路元件处经由第一路径传播的数据有关的信息，其中第一数据路径包括响应于单个时钟晶体管的输出的第一晶体管。第一晶体管具有比与第二数据路径相关联的第二晶体管更高的电流流动能力。

8. 发明申请

US20070153584A1 System and method for low power wordline logic for a memory 有权
标题翻译：用于存储器的低功率字线逻辑的系统和方法
公开(公告)号：US20070153584A1
公开(公告)日：2007-07-05
申请号：US11402483
申请日：2006-04-11
申请人： Baker Mohammad , Paul Bassett
发明人： Baker Mohammad , Paul Bassett
IPC分类号： G11C11/34
CPC分类号： G11C5/147 , G11C8/08 , G11C8/10
摘要： A method of reducing power consumption of a memory is provided. A request is received to access a memory device, including a decoder, a plurality of wordline drivers and a plurality of wordlines. Each wordline is associated with a wordline driver of the plurality of wordline drivers. The request is decoded by a decoder to determine an address associated with the request. A wordline driver of the plurality of wordline drivers is selectively powered to access the address of the memory device, where the wordline driver is associated with a particular wordline of the plurality of wordlines that is related to the address bits, without powering other wordlines of the plurality of wordlines.
摘要翻译：提供了降低存储器功耗的方法。接收到访问包括解码器，多个字线驱动器和多个字线的存储器设备的请求。每个字线与多个字线驱动器的字线驱动器相关联。该请求由解码器解码以确定与请求相关联的地址。选择性地供电多个字线驱动器的字线驱动器以访问存储器件的地址，其中字线驱动器与多个字线中与地址位相关的特定字线相关联，而不为其提供其他字线多个字线。

9. 发明申请

US20100131812A1 Resizable Cache Memory 有权
标题翻译：可调整大小的缓存内存
公开(公告)号：US20100131812A1
公开(公告)日：2010-05-27
申请号：US12323932
申请日：2008-11-26
申请人： Baker Mohammad
发明人： Baker Mohammad
IPC分类号： G11C29/12 , G11C29/04 , G06F11/00
CPC分类号： G11C29/44 , G11C29/4401 , G11C2029/0401 , G11C2029/4402
摘要： A resizable cache memory is disclosed. In a particular embodiment, a system is disclosed and includes a Built-In Self Test (BIST) circuit configured to test a cache memory. The system further includes a non-volatile storage device including an E-fuse array to store one or more indicators. Each indicator identifies a corresponding memory address of a failed location of the cache memory that has been detected by the BIST circuit.
摘要翻译：公开了一种可调整大小的缓存存储器。在特定实施例中，公开了一种系统，并且包括被配置为测试高速缓存存储器的内置自测（BIST）电路。该系统还包括非易失性存储装置，其包括用于存储一个或多个指示符的电子熔丝阵列。每个指示符标识由BIST电路检测到的高速缓冲存储器的故障位置的对应存储器地址。

10. 发明授权

US07760576B2 Systems and methods for low power, high yield memory 有权
标题翻译：低功耗，高产量存储器的系统和方法
公开(公告)号：US07760576B2
公开(公告)日：2010-07-20
申请号：US12036554
申请日：2008-02-25
申请人： Baker Mohammad
发明人： Baker Mohammad
IPC分类号： G11C8/00
CPC分类号： G11C5/14 , G11C11/413
摘要： A system for low power, high yield memory is described. The system includes a memory cell configured to receive a memory supply voltage. The system further includes a memory supply voltage control circuit configured to modify the memory supply voltage from a first memory supply voltage level to a second memory supply voltage level for a write to the memory cell.
摘要翻译：描述了一种用于低功率，高产量存储器的系统。该系统包括被配置为接收存储器电源电压的存储单元。该系统还包括存储器电源电压控制电路，配置为将存储器电源电压从第一存储器电源电压电平修改到用于对存储器单元的写入的第二存储器电源电压电平。

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