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1. 发明申请

US20120083912A1 ARITHMETIC LOGIC AND SHIFTING DEVICE FOR USE IN A PROCESSOR 有权
标题翻译：用于处理器的算术逻辑和移位装置
公开(公告)号：US20120083912A1
公开(公告)日：2012-04-05
申请号：US13314530
申请日：2011-12-08
申请人： Muhammad Ahmed , Ajay Anant Ingle , Sujat Jamil
发明人： Muhammad Ahmed , Ajay Anant Ingle , Sujat Jamil
IPC分类号： G06F17/00 , G06F9/305 , G06F9/38 , G06F9/302 , G06F9/315
CPC分类号： G06F9/30181 , G06F9/30032 , G06F9/3012 , G06F9/30189 , G06F9/3802 , G06F9/3851 , G06F9/3885
摘要： An arithmetic logic and shifting device is disclosed and includes an arithmetic logic unit that has a first input to receive a first operand from a first register port, a second input to receive a second operand from a second register port, and an output to selectively provide a memory address to a memory unit in a first mode of operation and to selectively provide an arithmetic output in a second mode of operation. Further, the arithmetic logic and shifting device includes a programmable shifter device that has a first input to receive data from the memory unit, a second input to receive the arithmetic output, a third input to receive an operation code of a computer execution instruction, and a shifted output to provide shifted data.
摘要翻译：公开了算术逻辑和移位装置，并且包括算术逻辑单元，该算术逻辑单元具有从第一寄存器端口接收第一操作数的第一输入端，从第二寄存器端口接收第二操作数的第二输入端和选择性地提供以第一操作模式向存储器单元提供存储器地址，并且在第二操作模式中选择性地提供算术输出。此外，算术逻辑和移位装置包括可编程移位器装置，其具有用于从存储器单元接收数据的第一输入端，用于接收算术输出的第二输入端，接收计算机执行指令的操作码的第三输入端，以及移位输出以提供移位数据。

2. 发明申请

US20100228944A1 Apparatus and Method to Translate Virtual Addresses to Physical Addresses in a Base Plus Offset Addressing Mode 失效
标题翻译：在Base Plus偏移寻址模式中将虚拟地址转换为物理地址的装置和方法
公开(公告)号：US20100228944A1
公开(公告)日：2010-09-09
申请号：US12397438
申请日：2009-03-04
申请人： Paul Douglas Bassett , Ajay Anant Ingle , Sujat Jamil , Lucian Codrescu , Muhammad Ahmed
发明人： Paul Douglas Bassett , Ajay Anant Ingle , Sujat Jamil , Lucian Codrescu , Muhammad Ahmed
IPC分类号： G06F12/10 , G06F12/00
CPC分类号： G06F12/1027 , G06F2212/1016 , G06F2212/652 , G06F2212/654 , G06F2212/655
摘要： An apparatus and method to translate virtual addresses to physical addresses in a base plus offset addressing mode are disclosed. In an embodiment, a method includes performing a first translation lookaside buffer (TLB) lookup based on a base address value to retrieve a speculative physical address. While performing the TLB lookup based on the base address value, the base address value is added to an offset value to generate an effective address value. The method also includes performing a comparison of the base address value and the effective address value based on a variable page size to determine whether the speculative physical address corresponds to the effective address.
摘要翻译：公开了一种将虚拟地址转换为基本加偏移寻址模式的物理地址的装置和方法。在一个实施例中，一种方法包括基于基地址值执行第一翻译后备缓冲器（TLB）查找以检索推测性物理地址。在基于基地址值执行TLB查找的同时，将基地址值添加到偏移值以生成有效的地址值。该方法还包括基于可变页大小执行基地址值与有效地址值的比较，以确定推测物理地址是否对应于有效地址。

3. 发明授权

US07620778B2 Low power microprocessor cache memory and method of operation 有权
标题翻译：低功耗微处理器缓存存储器和操作方法
公开(公告)号：US07620778B2
公开(公告)日：2009-11-17
申请号：US11137183
申请日：2005-05-25
申请人： Baker Mohammad , Muhammad Ahmed , Paul Bassett , Sujat Jamil , Ajay Anant Ingle
发明人： Baker Mohammad , Muhammad Ahmed , Paul Bassett , Sujat Jamil , Ajay Anant Ingle
IPC分类号： G06F12/00
CPC分类号： G06F12/0895 , G06F12/0864 , G06F12/0893
摘要： Techniques for processing transmissions in a communications (e.g., CDMA) system including the use of a digital signal processor. The digital signal processor includes a cache memory system and associates a plurality of cache memory match lines with addressable memory lines of an addressable memory. Each of the cache memory match lines associates with one of corresponding sets of the cache memory. The method and system maintain each of the cache memory match lines at a low voltage. Once the digital signal processor initiates a search of the cache memory for retrieving data from a selected one of the corresponding sets of the cache memory, a match line drive circuit drives one of the cache memory match lines from a low voltage to a high voltage. The selected one of the cache memory match lines corresponds to the selected one of the corresponding sets of the cache memory. The digital signal processor compares the selected one of the cache memory match lines to an associated one of the addressable memory lines. Following the comparison step, the process returns the one of the cache memory match lines to the low voltage.
摘要翻译：用于处理包括使用数字信号处理器的通信（例如，CDMA）系统中的传输的技术。数字信号处理器包括高速缓冲存储器系统，并将多个高速缓冲存储器匹配线与可寻址存储器的可寻址存储器线相关联。每个高速缓存存储器匹配行与高速缓冲存储器的相应组中的一个相关联。该方法和系统将每个缓存存储器匹配线保持在低电压。一旦数字信号处理器启动对高速缓冲存储器的搜索，以从相应的高速缓冲存储器组中的选定的一个中选出一个数据，则匹配线驱动电路将高速缓冲存储器匹配线之一从低电压驱动到高电压。高速缓存存储器匹配行中所选择的一个对应于高速缓冲存储器的所选择的相应组中的一个。数字信号处理器将所选择的一个高速缓冲存储器匹配线与可寻址存储器线中的相关联的一个进行比较。在比较步骤之后，该过程将高速缓存存储器匹配行之一返回到低电压。

4. 发明授权

US08688761B2 Arithmetic logic and shifting device for use in a processor 有权
标题翻译：用于处理器的算术逻辑和移位装置
公开(公告)号：US08688761B2
公开(公告)日：2014-04-01
申请号：US13314530
申请日：2011-12-08
申请人： Muhammad Ahmed , Ajay Anant Ingle , Sujat Jamil
发明人： Muhammad Ahmed , Ajay Anant Ingle , Sujat Jamil
IPC分类号： G06F7/00 , G06F15/00 , G06F7/38 , G06F12/00 , G06F9/26 , G06F9/34
CPC分类号： G06F9/30181 , G06F9/30032 , G06F9/3012 , G06F9/30189 , G06F9/3802 , G06F9/3851 , G06F9/3885
摘要： An arithmetic logic and shifting device is disclosed and includes an arithmetic logic unit that has a first input to receive a first operand from a first register port, a second input to receive a second operand from a second register port, and an output to selectively provide a memory address to a memory unit in a first mode of operation and to selectively provide an arithmetic output in a second mode of operation. Further, the arithmetic logic and shifting device includes a programmable shifter device that has a first input to receive data from the memory unit, a second input to receive the arithmetic output, a third input to receive an operation code of a computer execution instruction, and a shifted output to provide shifted data.
摘要翻译：公开了算术逻辑和移位装置，并且包括算术逻辑单元，该算术逻辑单元具有从第一寄存器端口接收第一操作数的第一输入端，从第二寄存器端口接收第二操作数的第二输入端和选择性地提供以第一操作模式向存储器单元提供存储器地址，并且在第二操作模式中选择性地提供算术输出。此外，算术逻辑和移位装置包括可编程移位器装置，其具有用于从存储器单元接收数据的第一输入端，用于接收算术输出的第二输入端，接收计算机执行指令的操作码的第三输入端，以及移位输出以提供移位数据。

5. 发明授权

US08195916B2 Apparatus and method to translate virtual addresses to physical addresses in a base plus offset addressing mode 失效
标题翻译：将虚拟地址转换为基本加偏移寻址模式的物理地址的装置和方法
公开(公告)号：US08195916B2
公开(公告)日：2012-06-05
申请号：US12397438
申请日：2009-03-04
申请人： Paul Douglas Bassett , Ajay Anant Ingle , Sujat Jamil , Lucian Codrescu , Muhammad Ahmed
发明人： Paul Douglas Bassett , Ajay Anant Ingle , Sujat Jamil , Lucian Codrescu , Muhammad Ahmed
IPC分类号： G06F12/00
CPC分类号： G06F12/1027 , G06F2212/1016 , G06F2212/652 , G06F2212/654 , G06F2212/655
摘要： An apparatus and method to translate virtual addresses to physical addresses in a base plus offset addressing mode are disclosed. In an embodiment, a method includes performing a first translation lookaside buffer (TLB) lookup based on a base address value to retrieve a speculative physical address. While performing the TLB lookup based on the base address value, the base address value is added to an offset value to generate an effective address value. The method also includes performing a comparison of the base address value and the effective address value based on a variable page size to determine whether the speculative physical address corresponds to the effective address.
摘要翻译：公开了一种将虚拟地址转换为基本加偏移寻址模式的物理地址的装置和方法。在一个实施例中，一种方法包括基于基地址值执行第一翻译后备缓冲器（TLB）查找以检索推测性物理地址。在基于基地址值执行TLB查找的同时，将基地址值添加到偏移值以生成有效的地址值。该方法还包括基于可变页大小执行基地址值与有效地址值的比较，以确定推测物理地址是否对应于有效地址。

6. 发明授权

US08099448B2 Arithmetic logic and shifting device for use in a processor 有权
标题翻译：用于处理器的算术逻辑和移位装置
公开(公告)号：US08099448B2
公开(公告)日：2012-01-17
申请号：US11266076
申请日：2005-11-02
申请人： Muhammad Ahmed , Ajay Anant Ingle , Sujat Jamil
发明人： Muhammad Ahmed , Ajay Anant Ingle , Sujat Jamil
IPC分类号： G06F7/00 , G06F15/00 , G06F7/38 , G06F9/26 , G06F9/34
CPC分类号： G06F9/30181 , G06F9/30032 , G06F9/3012 , G06F9/30189 , G06F9/3802 , G06F9/3851 , G06F9/3885
摘要： An arithmetic logic and shifting device is disclosed and includes an arithmetic logic unit that has a first input to receive a first operand from a first register port, a second input to receive a second operand from a second register port, and an output to selectively provide a memory address to a memory unit in a first mode of operation and to selectively provide an arithmetic output in a second mode of operation. Further, the arithmetic logic and shifting device includes a programmable shifter device that has a first input to receive data from the memory unit, a second input to receive the arithmetic output, a third input to receive an operation code of a computer execution instruction, and a shifted output to provide shifted data.
摘要翻译：公开了算术逻辑和移位装置，并且包括算术逻辑单元，该算术逻辑单元具有从第一寄存器端口接收第一操作数的第一输入端，从第二寄存器端口接收第二操作数的第二输入端和选择性地提供以第一操作模式向存储器单元提供存储器地址，并且在第二操作模式中选择性地提供算术输出。此外，算术逻辑和移位装置包括可编程移位器装置，其具有用于从存储器单元接收数据的第一输入端，用于接收算术输出的第二输入端，接收计算机执行指令的操作码的第三输入端，以及移位输出以提供移位数据。

7. 发明授权

US07523295B2 Processor and method of grouping and executing dependent instructions in a packet 有权
标题翻译：分组和执行分组中的相关指令的处理器和方法
公开(公告)号：US07523295B2
公开(公告)日：2009-04-21
申请号：US11086475
申请日：2005-03-21
申请人： Lucian Codrescu , Erich Plondke , Muhammad Ahmed , Sujat Jamil , William C. Anderson
发明人： Lucian Codrescu , Erich Plondke , Muhammad Ahmed , Sujat Jamil , William C. Anderson
IPC分类号： G06F9/30 , G06F9/40
CPC分类号： G06F9/3885 , G06F9/3851 , G06F9/3853
摘要： An interleaved multithreading pipeline operating method comprises reading an instruction packet containing at least two instructions, steering a first instruction of the instruction packet to a first execution unit for execution and generating a first result, steering a second instruction of the instruction packet to a second execution unit for execution using the first result and generating a second result, and storing the second result.
摘要翻译：交错多线程流水线操作方法包括读取包含至少两个指令的指令分组，将指令分组的第一指令转向第一执行单元以执行并产生第一结果，将指令分组的第二指令转向第二执行使用第一结果执行的单元并产生第二结果，并存储第二结果。

8. 发明申请

US20060268592A1 Low power microprocessor cache memory and method of operation 有权
公开(公告)号：US20060268592A1
公开(公告)日：2006-11-30
申请号：US11137183
申请日：2005-05-25
申请人： Baker Mohammad , Muhammad Ahmed , Paul Bassett , Sujat Jamil , Ajay Ingle
发明人： Baker Mohammad , Muhammad Ahmed , Paul Bassett , Sujat Jamil , Ajay Ingle
IPC分类号： G11C15/00
CPC分类号： G06F12/0895 , G06F12/0864 , G06F12/0893
摘要： Techniques for processing transmissions in a communications (e.g., CDMA) system including the use of a digital signal processor. The digital signal processor includes a cache memory system and associates a plurality of cache memory match lines with addressable memory lines of an addressable memory. Each of the cache memory match lines associates with one of corresponding sets of the cache memory. The method and system maintain each of the cache memory match lines at a low voltage. Once the digital signal processor initiates a search of the cache memory for retrieving data from a selected one of the corresponding sets of the cache memory, a match line drive circuit drives one of the cache memory match lines from a low voltage to a high voltage. The selected one of the cache memory match lines corresponds to the selected one of the corresponding sets of the cache memory. The digital signal processor compares the selected one of the cache memory match lines to an associated one of the addressable memory lines. Following the comparison step, the process returns the one of the cache memory match lines to the low voltage.

9. 发明申请

US20060218559A1 Method and system for variable thread allocation and switching in a multithreaded processor 有权
标题翻译：多线程处理器中可变线程分配和切换的方法和系统
公开(公告)号：US20060218559A1
公开(公告)日：2006-09-28
申请号：US11089474
申请日：2005-03-23
申请人： Muhammad Ahmed , Sujat Jamil , Erich Plondke , Lucian Codrescu , William Anderson
发明人： Muhammad Ahmed , Sujat Jamil , Erich Plondke , Lucian Codrescu , William Anderson
IPC分类号： G06F9/46
CPC分类号： G06F9/3851
摘要： Techniques for processing transmissions in a communications (e.g., CDMA) system. An aspect of the disclosed subject matter includes a method for processing instructions on a multithreaded processor. The multithreaded processor processes a plurality of threads via a plurality of processor pipelines. The method includes the step determining the operating frequency, F, at which the multithreaded processor operates. Then, the method determines a variable thread switch timeout state for triggering the switching of the processing among the plurality of active threads. The variable thread switch timeout state varies so that each of the plurality of active threads operates at a frequency of an allocated portion of the frequency, F. The allocated portion at which the active threads operate is determined at least in part in order to optimize the operation of the multithreaded processor. The method further switches the processing from a first one of the active threads to a next one of the active threads upon the occurrence of the variable thread switch timeout state.
摘要翻译：用于在通信（例如，CDMA）系统中处理传输的技术。所公开的主题的一个方面包括用于在多线程处理器上处理指令的方法。多线程处理器经由多个处理器管线处理多个线程。该方法包括确定多线程处理器工作的工作频率F的步骤。然后，该方法确定用于触发多个活动线程之间的处理切换的可变线程切换超时状态。可变线程切换超时状态改变，使得多个活动线程中的每一个以所分配的频率部分F的频率运行。活动线程运行的分配部分至少部分地被确定，以便优化操作多线程处理器。在发生可变线程切换超时状态时，该方法还将处理从主动线程中的第一个切换到下一个活动线程。

10. 发明申请

US20060212681A1 Processor and method of grouping and executing dependent instructions in a packet 有权
公开(公告)号：US20060212681A1
公开(公告)日：2006-09-21
申请号：US11086475
申请日：2005-03-21
申请人： Lucian Codrescu , Erich Plondke , Muhammad Ahmed , Sujat Jamil , William Anderson
发明人： Lucian Codrescu , Erich Plondke , Muhammad Ahmed , Sujat Jamil , William Anderson
IPC分类号： G06F9/30
CPC分类号： G06F9/3885 , G06F9/3851 , G06F9/3853
摘要： An interleaved multithreading pipeline operating method comprises reading an instruction packet containing at least two instructions, steering a first instruction of the instruction packet to a first execution unit for execution and generating a first result, steering a second instruction of the instruction packet to a second execution unit for execution using the first result and generating a second result, and storing the second result.

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