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1. 发明授权

US07928002B2 Method of forming wiring layer of semiconductor device 有权
标题翻译：形成半导体器件布线层的方法
公开(公告)号：US07928002B2
公开(公告)日：2011-04-19
申请号：US12396632
申请日：2009-03-03
申请人： Mu-kyeng Jung , Sun-jung Lee , Ki-chul Park
发明人： Mu-kyeng Jung , Sun-jung Lee , Ki-chul Park
IPC分类号： H01L21/4763
CPC分类号： H01L21/76895 , H01L21/76816 , H01L21/76877 , H01L23/485 , H01L23/53252 , H01L2924/0002 , H01L2924/00
摘要： A method of forming a wiring layer of a semiconductor device, includes forming a first interlayer insulating layer to have a first thickness corresponding to a part of the thickness of an interlayer insulating layer that is to be formed on a support layer and forming a first contact plug in the first interlayer insulating layer. The method further includes forming a second interlayer insulating layer to have a second thickness on the first contact plug and the first interlayer insulating layer, thereby forming the interlayer insulating layer, wherein the second thickness corresponds to the rest of the thickness of the interlayer insulating layer, and forming a second contact plug connected to the first contact plug in the second interlayer insulating layer, thereby forming a local wiring layer including the first contact plug and the second contact plug.
摘要翻译：一种形成半导体器件的布线层的方法，包括形成第一层间绝缘层，以具有对应于待形成在支撑层上的层间绝缘层的厚度的一部分的第一厚度并形成第一接触插入第一层间绝缘层。该方法还包括在第一接触插塞和第一层间绝缘层上形成具有第二厚度的第二层间绝缘层，从而形成层间绝缘层，其中第二厚度对应于层间绝缘层的其余厚度并且形成与所述第二层间绝缘层中的所述第一接触插塞连接的第二接触插塞，由此形成包括所述第一接触插塞和所述第二接触插塞的局部布线层。

2. 发明申请

US20060154465A1 Method for fabricating interconnection line in semiconductor device 审中-公开
标题翻译：在半导体器件中制造互连线的方法
公开(公告)号：US20060154465A1
公开(公告)日：2006-07-13
申请号：US11330581
申请日：2006-01-12
申请人： Bong-seok Suh , Sun-jung Lee , Hong-jae Shin , Soo-geun Lee
发明人： Bong-seok Suh , Sun-jung Lee , Hong-jae Shin , Soo-geun Lee
IPC分类号： H01L21/44 , H01L21/4763
CPC分类号： H01L21/76846 , H01L21/76849 , H01L21/76858 , H01L21/76871 , H01L21/76877 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： Provided is a method for fabricating an interconnection line in a semiconductor device. The method includes forming a dielectric layer pattern including a region for forming the interconnection line on a semiconductor substrate, forming a diffusion barrier layer on the dielectric layer pattern, forming a first adhesion layer on the diffusion barrier layer, forming a seed layer on the first adhesion layer, forming a conductive layer to fill the region for forming the interconnection line, performing grain growth of the conductive layer by performing a first annealing process, planarizing the conductive layer to expose the top surface of the dielectric layer pattern, and forming an interface layer through reaction between the first adhesion layer and the conductive layer by performing a second annealing process at a temperature higher than that of the first annealing process.
摘要翻译：提供一种在半导体器件中制造互连线的方法。该方法包括在半导体衬底上形成包括用于形成互连线的区域的电介质层图案，在电介质层图案上形成扩散阻挡层，在扩散阻挡层上形成第一粘附层，在第一层上形成晶种层形成导电层以填充用于形成互连线的区域，通过执行第一退火工艺来执行导电层的晶粒生长，使导电层平坦化以暴露电介质层图案的顶表面，以及形成界面通过在高于第一退火处理的温度下进行第二退火处理，在第一粘附层和导电层之间反应层。

3. 发明申请

US20060177630A1 Method of forming a metal interconnection of a semiconductor device, and metal interconnection formed by such method 有权
标题翻译：形成半导体器件的金属互连的方法以及通过这种方法形成的金属互连
公开(公告)号：US20060177630A1
公开(公告)日：2006-08-10
申请号：US11336905
申请日：2006-01-23
申请人： Sun-jung Lee , Soo-geun Lee , Hong-jae Shin , Andrew-tae Kim , Seung-man Choi , Bong-seok Suh
发明人： Sun-jung Lee , Soo-geun Lee , Hong-jae Shin , Andrew-tae Kim , Seung-man Choi , Bong-seok Suh
IPC分类号： B32B3/04
CPC分类号： H01L21/76877 , H01L21/7684 , H01L21/76883 , Y10T428/24207
摘要： A metal interconnection of a semiconductor device, formed using a damascene process, has large grains and yet a smooth surface. First, a barrier layer and a metal layer are sequentially formed in an opening in an interlayer dielectric layer. A CMP process is carried out on the metal layer to form a metal interconnection remaining within the opening. Then, the metal interconnection is treated with plasma. The plasma treatment creates compressive stress in the metal interconnection, which stress produces hillocks at the surface of the metal interconnection. In addition, the plasma treatment process causes grains of the metal to grow, especially when the design rule is small, to thereby decrease the resistivity of the metal interconnection. The hillocks are then removed by a CMP process aimed at polishing the portion of the barrier layer that extends over the upper surface of the interlayer dielectric layer. Finally, a capping insulating layer is formed. The intentional forming of hillocks by the plasma treatment process at weak portions of the metal interconnection and the subsequent removal of the hillocks greatly reduces the possibility of any additional hillocks being produced at the surface of the metal interconnection, especially when the capping layer is formed.
摘要翻译：使用镶嵌工艺形成的半导体器件的金属互连具有大的晶粒并且具有光滑的表面。首先，在层间电介质层的开口中依次形成阻挡层和金属层。在金属层上进行CMP工艺以形成残留在开口内的金属互连。然后，用等离子体处理金属互连。等离子体处理在金属互连中产生压应力，该应力在金属互连表面产生小丘。此外，等离子体处理工艺使得金属晶粒生长，特别是当设计规则小时，从而降低金属互连的电阻率。然后通过CMP工艺去除小丘，目的是抛光在层间电介质层的上表面上延伸的阻挡层的部分。最后，形成封盖绝缘层。通过等离子体处理在金属互连的弱部分和随后的小丘的移除中有意形成小丘大大减少了在金属互连表面产生任何额外的小丘的可能性，特别是当形成覆盖层时。

4. 发明授权

US07446033B2 Method of forming a metal interconnection of a semiconductor device, and metal interconnection formed by such method 有权
标题翻译：形成半导体器件的金属互连的方法以及通过这种方法形成的金属互连
公开(公告)号：US07446033B2
公开(公告)日：2008-11-04
申请号：US11336905
申请日：2006-01-23
申请人： Sun-jung Lee , Soo-geun Lee , Hong-jae Shin , Andrew-tae Kim , Seung-man Choi , Bong-seok Suh
发明人： Sun-jung Lee , Soo-geun Lee , Hong-jae Shin , Andrew-tae Kim , Seung-man Choi , Bong-seok Suh
IPC分类号： H01L21/4763 , H01L21/44
CPC分类号： H01L21/76877 , H01L21/7684 , H01L21/76883 , Y10T428/24207
摘要： A metal interconnection of a semiconductor device, formed using a damascene process, has large grains and yet a smooth surface. First, a barrier layer and a metal layer are sequentially formed in an opening in an interlayer dielectric layer. A CMP process is carried out on the metal layer to form a metal interconnection remaining within the opening. Then, the metal interconnection is treated with plasma. The plasma treatment creates compressive stress in the metal interconnection, which stress produces hillocks at the surface of the metal interconnection. In addition, the plasma treatment process causes grains of the metal to grow, especially when the design rule is small, to thereby decrease the resistivity of the metal interconnection. The hillocks are then removed by a CMP process aimed at polishing the portion of the barrier layer that extends over the upper surface of the interlayer dielectric layer. Finally, a capping insulating layer is formed. The intentional forming of hillocks by the plasma treatment process at weak portions of the metal interconnection and the subsequent removal of the hillocks greatly reduces the possibility of any additional hillocks being produced at the surface of the metal interconnection, especially when the capping layer is formed.
摘要翻译：使用镶嵌工艺形成的半导体器件的金属互连具有大的晶粒并且具有光滑的表面。首先，在层间电介质层的开口中依次形成阻挡层和金属层。在金属层上进行CMP工艺以形成残留在开口内的金属互连。然后，用等离子体处理金属互连。等离子体处理在金属互连中产生压应力，该应力在金属互连表面产生小丘。此外，等离子体处理工艺使得金属晶粒生长，特别是当设计规则小时，从而降低金属互连的电阻率。然后通过CMP工艺去除小丘，目的是抛光在层间电介质层的上表面上延伸的阻挡层的部分。最后，形成封盖绝缘层。通过等离子体处理在金属互连的弱部分和随后的小丘的移除中有意形成小丘大大减少了在金属互连表面产生任何额外的小丘的可能性，特别是当形成覆盖层时。

5. 发明授权

US07488688B2 Method of removing oxide layer and semiconductor manufacturing apparatus for removing oxide layer 有权
标题翻译：去除氧化物层的方法和用于去除氧化物层的半导体制造装置
公开(公告)号：US07488688B2
公开(公告)日：2009-02-10
申请号：US10997902
申请日：2004-11-29
申请人： Seung-pil Chung , Kyu-whan Chang , Sun-jung Lee , Kun-tack Lee , Im-soo Park , Kwang-wook Lee , Moon-hee Lee
发明人： Seung-pil Chung , Kyu-whan Chang , Sun-jung Lee , Kun-tack Lee , Im-soo Park , Kwang-wook Lee , Moon-hee Lee
IPC分类号： H01L21/302
CPC分类号： H01L21/02057 , H01L21/31116
摘要： A method for removing an oxide layer such as a natural oxide layer and a semiconductor manufacturing apparatus which uses the method to remove the oxide layer. A vertically movable susceptor is installed at the lower portion in a processing chamber and a silicon wafer is loaded onto the susceptor when it is at the lower portion of the processing chamber. The air is exhausted from the processing chamber to form a vacuum condition therein. A hydrogen gas in a plasma state and a fluorine-containing gas are supplied into the processing chamber to induce a chemical reaction with the oxide layer on the silicon wafer, resulting in a reaction layer. Then, the susceptor is moved up to the upper portion of the processing chamber, to anneal the silicon wafer on the susceptor with a heater installed at the upper portion of the processing chamber, thus vaporizing the reaction layer. The vaporized reaction layer is exhausted out of the chamber. The oxide layer can be removed with a high selectivity while avoiding damage or contamination of the underlying layer.
摘要翻译：用于除去氧化物层的方法，例如天然氧化物层和使用该方法去除氧化物层的半导体制造装置。垂直移动的基座安装在处理室的下部处，并且当硅晶片位于处理室的下部时，将硅晶片装载到基座上。空气从处理室排出，在其中形成真空条件。将等离子体状态的氢气和含氟气体供给到处理室，以引起与硅晶片上的氧化物层的化学反应，产生反应层。然后，将基座向上移动到处理室的上部，通过安装在处理室上部的加热器对基座上的硅晶片退火，从而使反应层蒸发。蒸发的反应层被排出室外。可以以高选择性去除氧化物层，同时避免下层的损坏或污染。

6. 发明授权

US06607654B2 Copper-plating elecrolyte containing polyvinylpyrrolidone and method for forming a copper interconnect 有权
标题翻译：含有电解质电解质的聚乙烯吡咯烷酮和形成铜互连的方法
公开(公告)号：US06607654B2
公开(公告)日：2003-08-19
申请号：US09899228
申请日：2001-07-06
申请人： Sun-jung Lee , Kyu-hwan Chang , Hyeon-deok Lee
发明人： Sun-jung Lee , Kyu-hwan Chang , Hyeon-deok Lee
IPC分类号： C25D338
CPC分类号： H01L21/76877 , C25D3/38 , C25D7/12 , H01L21/2885 , Y10T428/12528
摘要： A copper-plating electrolyte includes an aqueous copper salt solution, a water-soluble &bgr;-naphtholethoxylate compound having the formula wherein n is an integer from 10 to 24, one selected from the group consisting of a disulfide having the formula XO3S(CH2)3SS(CH2)3SOX3 and a water-soluble mercaptopropanesulfonic acid or salt thereof having the formula HS(CH2)3SO3X, where X is sodium, potassium, or hydrogen, a water-soluble polyethylene glycol having a molecular weight ranging from about 4,600 to about 10,000, and a water-soluble polyvinylpyrrolidone having a molecular weight ranging from about 10,000 to about 1,300,000.
摘要翻译：镀铜电解质包括铜盐水溶液，具有方解石的水溶性β-萘基乙氧基化合物，n为10-24的整数，选自具有式XO 3 S（CH 2）3 SS的二硫化物 CH2）3SOX3和具有式HS（CH2）3SO3X的水溶性巯基丙磺酸或其盐，其中X为钠，钾或氢，分子量范围为约4,600至约10,000的水溶性聚乙二醇，和分子量范围为约10,000至约1,300,000的水溶性聚乙烯吡咯烷酮。

7. 发明授权

US07655525B2 Semiconductor device free of gate spacer stress and method of manufacturing the same 有权
标题翻译：没有栅间隔应力的半导体器件及其制造方法
公开(公告)号：US07655525B2
公开(公告)日：2010-02-02
申请号：US11848991
申请日：2007-08-31
申请人： Sun-jung Lee , Hong-jae Shin , Bong-seok Suh
发明人： Sun-jung Lee , Hong-jae Shin , Bong-seok Suh
IPC分类号： H01L21/336 , H01L21/8238 , H01L21/4763
CPC分类号： H01L29/66515 , H01L29/665 , H01L29/6653 , H01L29/6656
摘要： A semiconductor device that prevents gate spacer stress and physical and chemical damages on a silicide region, and a method of manufacturing the same, according to an exemplary embodiment of the present invention, includes a substrate, isolation regions formed in the substrate, a gate pattern formed between the isolation regions on the substrate, an L-type spacer adjacent to the sidewall of the gate pattern and extended to the surface of the substrate, source/drain silicide regions formed on the substrate between the end of the L-type spacer extended to the surface of the substrate and the isolation regions, via plugs electrically connected with the source/drain silicide regions, an interlayer dielectric layer which is adjacent to the L-type spacer and which fills the space between the via plugs layer formed on the gate pattern and the substrate, and a signal-transfer line formed on the interlayer dielectric layer.
摘要翻译：根据本发明的示例性实施例的防止栅极间隔物应力和硅化物区域的物理和化学损伤的半导体器件及其制造方法包括：衬底，形成在衬底中的隔离区域，栅极图案形成在衬底上的隔离区域之间，与栅极图案的侧壁相邻并延伸到衬底表面的L型衬垫，形成在衬底上的L型间隔物延伸的端部之间的源极/漏极硅化物区域通过与源极/漏极硅化物区域电连接的插塞到衬底的表面和隔离区域，与L型间隔物相邻并填充形成在栅极上的通孔塞层之间的空间的层间电介质层图案和衬底，以及形成在层间电介质层上的信号传输线。

8. 发明申请

US20070298600A1 Method of Fabricating Semiconductor Device and Semiconductor Device Fabricated Thereby 审中-公开
标题翻译：由此制造半导体器件和半导体器件的方法
公开(公告)号：US20070298600A1
公开(公告)日：2007-12-27
申请号：US11425841
申请日：2006-06-22
申请人： Bong-seok Suh , Hong-jae Shin , Sun-jung Lee , Min-chul Sun , Jung-hoon Lee
发明人： Bong-seok Suh , Hong-jae Shin , Sun-jung Lee , Min-chul Sun , Jung-hoon Lee
IPC分类号： H01L21/3205
CPC分类号： H01L21/76846
摘要： A method of fabricating a semiconductor device and a semiconductor device fabricated thereby. The method of fabricating the semiconductor device includes forming gate electrodes on a semiconductor substrate; forming source/drain regions within the semiconductor substrate so as to be located at both sides of each of the gate electrodes; forming a nickel silicide layer on surfaces of the gate electrodes and the source/drain regions by evaporating nickel or nickel alloy on the semiconductor substrate formed with the gate electrodes and the source/drain regions and then performing a thermal process on the nickel or the nickel alloy; forming an interlayer insulating layer, which is formed with contact holes through which a surface of the nickel silicide layer is exposed, on a surface obtained after the above processes have been performed; forming an ohmic layer by evaporating a refractory metal conformably along the contact holes, the refractory metal being converted to silicide at a temperature of 500° C. or more; forming a diffusion barrier on the ohmic layer conformably along the contact holes; and forming a metal layer by burying a metal material within the contact holes.
摘要翻译：一种制造半导体器件的方法及其制造的半导体器件。制造半导体器件的方法包括在半导体衬底上形成栅电极; 在半导体衬底内形成源/漏区，以便位于每个栅电极的两侧; 通过在形成有栅电极和源极/漏极区域的半导体衬底上蒸发镍或镍合金，然后在镍或镍上进行热处理，在栅电极和源/漏区的表面上形成硅化镍层合金; 形成层间绝缘层，所述层间绝缘层在进行上述处理后得到的表面上形成有暴露所述镍硅化物层的表面的接触孔; 通过沿着接触孔顺应蒸发难熔金属形成欧姆层，难熔金属在500℃或更高的温度下转化为硅化物; 在欧姆层上沿着接触孔顺应地形成扩散阻挡层; 以及通过在接触孔内埋入金属材料来形成金属层。

9. 发明申请

US20050087893A1 Method of removing oxide layer and semiconductor manufacturing apparatus for removing oxide layer 有权
标题翻译：去除氧化物层的方法和用于去除氧化物层的半导体制造装置
公开(公告)号：US20050087893A1
公开(公告)日：2005-04-28
申请号：US10997902
申请日：2004-11-29
申请人： Seung-pil Chung , Kyu-whan Chang , Sun-jung Lee , Kun-tack Lee , Im-soo Park , Kwang-wook Lee , Moon-hee Lee
发明人： Seung-pil Chung , Kyu-whan Chang , Sun-jung Lee , Kun-tack Lee , Im-soo Park , Kwang-wook Lee , Moon-hee Lee
IPC分类号： H01L21/302 , H01L21/306 , H01L21/3065 , H01L21/31 , H01L21/311 , H01L21/3213
CPC分类号： H01L21/02057 , H01L21/31116
摘要： A method for removing an oxide layer such as a natural oxide layer and a semiconductor manufacturing apparatus which uses the method to remove the oxide layer. A vertically movable susceptor is installed at the lower portion in a processing chamber and a silicon wafer is loaded onto the susceptor when it is at the lower portion of the processing chamber. The air is exhausted from the processing chamber to form a vacuum condition therein. A hydrogen gas in a plasma state and a fluorine-containing gas are supplied into the processing chamber to induce a chemical reaction with the oxide layer on the silicon wafer, resulting in a reaction layer. Then, the susceptor is moved up to the upper portion of the processing chamber, to anneal the silicon wafer on the susceptor with a heater installed at the upper portion of the processing chamber, thus vaporizing the reaction layer. The vaporized reaction layer is exhausted out of the chamber. The oxide layer can be removed with a high selectivity while avoiding damage or contamination of the underlying layer.
摘要翻译：用于除去氧化物层的方法，例如天然氧化物层和使用该方法去除氧化物层的半导体制造装置。垂直移动的基座安装在处理室的下部处，并且当硅晶片位于处理室的下部时，将硅晶片装载到基座上。空气从处理室排出，在其中形成真空条件。将等离子体状态的氢气和含氟气体供给到处理室，以引起与硅晶片上的氧化物层的化学反应，产生反应层。然后，将基座向上移动到处理室的上部，通过安装在处理室上部的加热器对基座上的硅晶片退火，从而使反应层蒸发。蒸发的反应层被排出室外。可以以高选择性去除氧化物层，同时避免下层的损坏或污染。

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