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1. 发明授权

US07446033B2 Method of forming a metal interconnection of a semiconductor device, and metal interconnection formed by such method 有权
标题翻译：形成半导体器件的金属互连的方法以及通过这种方法形成的金属互连
公开(公告)号：US07446033B2
公开(公告)日：2008-11-04
申请号：US11336905
申请日：2006-01-23
申请人： Sun-jung Lee , Soo-geun Lee , Hong-jae Shin , Andrew-tae Kim , Seung-man Choi , Bong-seok Suh
发明人： Sun-jung Lee , Soo-geun Lee , Hong-jae Shin , Andrew-tae Kim , Seung-man Choi , Bong-seok Suh
IPC分类号： H01L21/4763 , H01L21/44
CPC分类号： H01L21/76877 , H01L21/7684 , H01L21/76883 , Y10T428/24207
摘要： A metal interconnection of a semiconductor device, formed using a damascene process, has large grains and yet a smooth surface. First, a barrier layer and a metal layer are sequentially formed in an opening in an interlayer dielectric layer. A CMP process is carried out on the metal layer to form a metal interconnection remaining within the opening. Then, the metal interconnection is treated with plasma. The plasma treatment creates compressive stress in the metal interconnection, which stress produces hillocks at the surface of the metal interconnection. In addition, the plasma treatment process causes grains of the metal to grow, especially when the design rule is small, to thereby decrease the resistivity of the metal interconnection. The hillocks are then removed by a CMP process aimed at polishing the portion of the barrier layer that extends over the upper surface of the interlayer dielectric layer. Finally, a capping insulating layer is formed. The intentional forming of hillocks by the plasma treatment process at weak portions of the metal interconnection and the subsequent removal of the hillocks greatly reduces the possibility of any additional hillocks being produced at the surface of the metal interconnection, especially when the capping layer is formed.
摘要翻译：使用镶嵌工艺形成的半导体器件的金属互连具有大的晶粒并且具有光滑的表面。首先，在层间电介质层的开口中依次形成阻挡层和金属层。在金属层上进行CMP工艺以形成残留在开口内的金属互连。然后，用等离子体处理金属互连。等离子体处理在金属互连中产生压应力，该应力在金属互连表面产生小丘。此外，等离子体处理工艺使得金属晶粒生长，特别是当设计规则小时，从而降低金属互连的电阻率。然后通过CMP工艺去除小丘，目的是抛光在层间电介质层的上表面上延伸的阻挡层的部分。最后，形成封盖绝缘层。通过等离子体处理在金属互连的弱部分和随后的小丘的移除中有意形成小丘大大减少了在金属互连表面产生任何额外的小丘的可能性，特别是当形成覆盖层时。

2. 发明申请

US20080067612A1 Semiconductor Device Including Nickel Alloy Silicide Layer Having Uniform Thickness and Method of Manufacturing the Same 审中-公开
标题翻译：包括具有均匀厚度的镍合金硅化物层的半导体器件及其制造方法
公开(公告)号：US20080067612A1
公开(公告)日：2008-03-20
申请号：US11775089
申请日：2007-07-09
申请人： Sun Jung Lee , Bong-seok Suh , Hong-jae Shin , Kee-young Jun , Jung-hoon Lee
发明人： Sun Jung Lee , Bong-seok Suh , Hong-jae Shin , Kee-young Jun , Jung-hoon Lee
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L21/324 , H01L21/28052 , H01L21/28518 , H01L21/288 , H01L29/165 , H01L29/665 , H01L29/66636 , H01L29/7833
摘要： A semiconductor device including a nickel alloy silicide layer having a uniform thickness includes isolation regions formed in a substrate, gate electrodes respectively formed on the substrate between the isolation regions, source/drain regions respectively formed between the gate electrodes and the isolation regions, spacers formed on lateral surfaces of the gate electrodes, and a nickel alloy silicide layer formed on upper portions of the source/drain regions.
摘要翻译：包括具有均匀厚度的镍合金硅化物层的半导体器件包括形成在衬底中的隔离区域，分别形成在隔离区域之间的衬底上的栅电极，分别形成在栅极电极和隔离区域之间的源极/漏极区域，形成间隔物在栅电极的侧表面上形成的镍合金硅化物层和形成在源/漏区上部的镍合金硅化物层。

3. 发明申请

US20060177630A1 Method of forming a metal interconnection of a semiconductor device, and metal interconnection formed by such method 有权
标题翻译：形成半导体器件的金属互连的方法以及通过这种方法形成的金属互连
公开(公告)号：US20060177630A1
公开(公告)日：2006-08-10
申请号：US11336905
申请日：2006-01-23
申请人： Sun-jung Lee , Soo-geun Lee , Hong-jae Shin , Andrew-tae Kim , Seung-man Choi , Bong-seok Suh
发明人： Sun-jung Lee , Soo-geun Lee , Hong-jae Shin , Andrew-tae Kim , Seung-man Choi , Bong-seok Suh
IPC分类号： B32B3/04
CPC分类号： H01L21/76877 , H01L21/7684 , H01L21/76883 , Y10T428/24207
摘要： A metal interconnection of a semiconductor device, formed using a damascene process, has large grains and yet a smooth surface. First, a barrier layer and a metal layer are sequentially formed in an opening in an interlayer dielectric layer. A CMP process is carried out on the metal layer to form a metal interconnection remaining within the opening. Then, the metal interconnection is treated with plasma. The plasma treatment creates compressive stress in the metal interconnection, which stress produces hillocks at the surface of the metal interconnection. In addition, the plasma treatment process causes grains of the metal to grow, especially when the design rule is small, to thereby decrease the resistivity of the metal interconnection. The hillocks are then removed by a CMP process aimed at polishing the portion of the barrier layer that extends over the upper surface of the interlayer dielectric layer. Finally, a capping insulating layer is formed. The intentional forming of hillocks by the plasma treatment process at weak portions of the metal interconnection and the subsequent removal of the hillocks greatly reduces the possibility of any additional hillocks being produced at the surface of the metal interconnection, especially when the capping layer is formed.
摘要翻译：使用镶嵌工艺形成的半导体器件的金属互连具有大的晶粒并且具有光滑的表面。首先，在层间电介质层的开口中依次形成阻挡层和金属层。在金属层上进行CMP工艺以形成残留在开口内的金属互连。然后，用等离子体处理金属互连。等离子体处理在金属互连中产生压应力，该应力在金属互连表面产生小丘。此外，等离子体处理工艺使得金属晶粒生长，特别是当设计规则小时，从而降低金属互连的电阻率。然后通过CMP工艺去除小丘，目的是抛光在层间电介质层的上表面上延伸的阻挡层的部分。最后，形成封盖绝缘层。通过等离子体处理在金属互连的弱部分和随后的小丘的移除中有意形成小丘大大减少了在金属互连表面产生任何额外的小丘的可能性，特别是当形成覆盖层时。

4. 发明申请

US20060154465A1 Method for fabricating interconnection line in semiconductor device 审中-公开
标题翻译：在半导体器件中制造互连线的方法
公开(公告)号：US20060154465A1
公开(公告)日：2006-07-13
申请号：US11330581
申请日：2006-01-12
申请人： Bong-seok Suh , Sun-jung Lee , Hong-jae Shin , Soo-geun Lee
发明人： Bong-seok Suh , Sun-jung Lee , Hong-jae Shin , Soo-geun Lee
IPC分类号： H01L21/44 , H01L21/4763
CPC分类号： H01L21/76846 , H01L21/76849 , H01L21/76858 , H01L21/76871 , H01L21/76877 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： Provided is a method for fabricating an interconnection line in a semiconductor device. The method includes forming a dielectric layer pattern including a region for forming the interconnection line on a semiconductor substrate, forming a diffusion barrier layer on the dielectric layer pattern, forming a first adhesion layer on the diffusion barrier layer, forming a seed layer on the first adhesion layer, forming a conductive layer to fill the region for forming the interconnection line, performing grain growth of the conductive layer by performing a first annealing process, planarizing the conductive layer to expose the top surface of the dielectric layer pattern, and forming an interface layer through reaction between the first adhesion layer and the conductive layer by performing a second annealing process at a temperature higher than that of the first annealing process.
摘要翻译：提供一种在半导体器件中制造互连线的方法。该方法包括在半导体衬底上形成包括用于形成互连线的区域的电介质层图案，在电介质层图案上形成扩散阻挡层，在扩散阻挡层上形成第一粘附层，在第一层上形成晶种层形成导电层以填充用于形成互连线的区域，通过执行第一退火工艺来执行导电层的晶粒生长，使导电层平坦化以暴露电介质层图案的顶表面，以及形成界面通过在高于第一退火处理的温度下进行第二退火处理，在第一粘附层和导电层之间反应层。

5. 发明授权

US07655525B2 Semiconductor device free of gate spacer stress and method of manufacturing the same 有权
标题翻译：没有栅间隔应力的半导体器件及其制造方法
公开(公告)号：US07655525B2
公开(公告)日：2010-02-02
申请号：US11848991
申请日：2007-08-31
申请人： Sun-jung Lee , Hong-jae Shin , Bong-seok Suh
发明人： Sun-jung Lee , Hong-jae Shin , Bong-seok Suh
IPC分类号： H01L21/336 , H01L21/8238 , H01L21/4763
CPC分类号： H01L29/66515 , H01L29/665 , H01L29/6653 , H01L29/6656
摘要： A semiconductor device that prevents gate spacer stress and physical and chemical damages on a silicide region, and a method of manufacturing the same, according to an exemplary embodiment of the present invention, includes a substrate, isolation regions formed in the substrate, a gate pattern formed between the isolation regions on the substrate, an L-type spacer adjacent to the sidewall of the gate pattern and extended to the surface of the substrate, source/drain silicide regions formed on the substrate between the end of the L-type spacer extended to the surface of the substrate and the isolation regions, via plugs electrically connected with the source/drain silicide regions, an interlayer dielectric layer which is adjacent to the L-type spacer and which fills the space between the via plugs layer formed on the gate pattern and the substrate, and a signal-transfer line formed on the interlayer dielectric layer.
摘要翻译：根据本发明的示例性实施例的防止栅极间隔物应力和硅化物区域的物理和化学损伤的半导体器件及其制造方法包括：衬底，形成在衬底中的隔离区域，栅极图案形成在衬底上的隔离区域之间，与栅极图案的侧壁相邻并延伸到衬底表面的L型衬垫，形成在衬底上的L型间隔物延伸的端部之间的源极/漏极硅化物区域通过与源极/漏极硅化物区域电连接的插塞到衬底的表面和隔离区域，与L型间隔物相邻并填充形成在栅极上的通孔塞层之间的空间的层间电介质层图案和衬底，以及形成在层间电介质层上的信号传输线。

6. 发明申请

US20070298600A1 Method of Fabricating Semiconductor Device and Semiconductor Device Fabricated Thereby 审中-公开
标题翻译：由此制造半导体器件和半导体器件的方法
公开(公告)号：US20070298600A1
公开(公告)日：2007-12-27
申请号：US11425841
申请日：2006-06-22
申请人： Bong-seok Suh , Hong-jae Shin , Sun-jung Lee , Min-chul Sun , Jung-hoon Lee
发明人： Bong-seok Suh , Hong-jae Shin , Sun-jung Lee , Min-chul Sun , Jung-hoon Lee
IPC分类号： H01L21/3205
CPC分类号： H01L21/76846
摘要： A method of fabricating a semiconductor device and a semiconductor device fabricated thereby. The method of fabricating the semiconductor device includes forming gate electrodes on a semiconductor substrate; forming source/drain regions within the semiconductor substrate so as to be located at both sides of each of the gate electrodes; forming a nickel silicide layer on surfaces of the gate electrodes and the source/drain regions by evaporating nickel or nickel alloy on the semiconductor substrate formed with the gate electrodes and the source/drain regions and then performing a thermal process on the nickel or the nickel alloy; forming an interlayer insulating layer, which is formed with contact holes through which a surface of the nickel silicide layer is exposed, on a surface obtained after the above processes have been performed; forming an ohmic layer by evaporating a refractory metal conformably along the contact holes, the refractory metal being converted to silicide at a temperature of 500° C. or more; forming a diffusion barrier on the ohmic layer conformably along the contact holes; and forming a metal layer by burying a metal material within the contact holes.
摘要翻译：一种制造半导体器件的方法及其制造的半导体器件。制造半导体器件的方法包括在半导体衬底上形成栅电极; 在半导体衬底内形成源/漏区，以便位于每个栅电极的两侧; 通过在形成有栅电极和源极/漏极区域的半导体衬底上蒸发镍或镍合金，然后在镍或镍上进行热处理，在栅电极和源/漏区的表面上形成硅化镍层合金; 形成层间绝缘层，所述层间绝缘层在进行上述处理后得到的表面上形成有暴露所述镍硅化物层的表面的接触孔; 通过沿着接触孔顺应蒸发难熔金属形成欧姆层，难熔金属在500℃或更高的温度下转化为硅化物; 在欧姆层上沿着接触孔顺应地形成扩散阻挡层; 以及通过在接触孔内埋入金属材料来形成金属层。

7. 发明授权

US07341908B2 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07341908B2
公开(公告)日：2008-03-11
申请号：US11344550
申请日：2006-01-30
申请人： Bong-seok Suh , Seung-man Choi , Hong-jae Shin , Young-jin Wee
发明人： Bong-seok Suh , Seung-man Choi , Hong-jae Shin , Young-jin Wee
IPC分类号： H01L21/8242
CPC分类号： H01L21/76846 , H01L21/76843 , H01L21/76864 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： Provided are a semiconductor device including a reliable interconnect and a method of manufacturing the same. The semiconductor device includes a substrate, an inter-metal dielectric (IMD) pattern having an opening, an amorphous metallic nitride layer formed on the inner surface of the opening, a diffusion barrier layer formed on the amorphous metallic nitride layer, and a conductive layer filled into the opening having the diffusion barrier layer.
摘要翻译：提供了包括可靠互连的半导体器件及其制造方法。半导体器件包括衬底，具有开口的金属间电介质（IMD）图案，形成在开口的内表面上的非晶金属氮化物层，形成在非晶金属氮化物层上的扩散阻挡层，以及导电层填充到具有扩散阻挡层的开口中。

8. 发明申请

US20080079089A1 Semiconductor Device Free of Gate Spacer Stress and Method of Manufacturing the Same 有权
标题翻译：没有栅极间隔应力的半导体器件及其制造方法
公开(公告)号：US20080079089A1
公开(公告)日：2008-04-03
申请号：US11848991
申请日：2007-08-31
申请人： Sung-jung Lee , Hong-jae Shin , Bong-seok Suh
发明人： Sung-jung Lee , Hong-jae Shin , Bong-seok Suh
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/66515 , H01L29/665 , H01L29/6653 , H01L29/6656
摘要： A semiconductor device that prevents gate spacer stress and physical and chemical damages on a silicide region, and a method of manufacturing the same, according to an exemplary embodiment of the present invention, includes a substrate, isolation regions formed in the substrate, a gate pattern formed between the isolation regions on the substrate, an L-type spacer adjacent to the sidewall of the gate pattern and extended to the surface of the substrate, source/drain silicide regions formed on the substrate between the end of the L-type spacer extended to the surface of the substrate and the isolation regions, via plugs electrically connected with the source/drain silicide regions, an interlayer dielectric layer which is adjacent to the L-type spacer and which fills the space between the via plugs layer formed on the gate pattern and the substrate, and a signal-transfer line formed on the interlayer dielectric layer.
摘要翻译：根据本发明的示例性实施例的防止栅极间隔物应力和硅化物区域的物理和化学损伤的半导体器件及其制造方法包括：衬底，形成在衬底中的隔离区域，栅极图案形成在衬底上的隔离区域之间，与栅极图案的侧壁相邻并延伸到衬底表面的L型衬垫，形成在衬底上的L型间隔物延伸的端部之间的源极/漏极硅化物区域通过与源极/漏极硅化物区域电连接的插塞到衬底的表面和隔离区域，与L型间隔物相邻并填充形成在栅极上的通孔塞层之间的空间的层间电介质层图案和衬底，以及形成在层间电介质层上的信号传输线。

9. 发明授权

US07687915B2 Semiconductor device having crack stop structure 有权
标题翻译：具有裂纹停止结构的半导体器件
公开(公告)号：US07687915B2
公开(公告)日：2010-03-30
申请号：US12216097
申请日：2008-06-30
申请人： Kyoung-woo Lee , Hong-jae Shin
发明人： Kyoung-woo Lee , Hong-jae Shin
IPC分类号： H01L23/522
CPC分类号： H01L23/585 , H01L23/564 , H01L2924/0002 , H01L2924/00
摘要： Example embodiments relate to semiconductor devices having a single body crack stop structure configured to reduce or prevent crack propagation and/or moisture penetration. A semiconductor substrate according to example embodiments may include an active region and a crack stop region surrounding the active region. Interlayer insulating layers may be sequentially stacked on the semiconductor substrate. The interlayer insulating layers may include first dual damascene patterns and a first opening. The first dual damascene patterns may be formed in the interlayer insulating layers so as to be perpendicular to the surface of the semiconductor substrate while exposing a first portion of the semiconductor substrate. The first opening may be formed in the crack stop region and may extend through the interlayer insulating layers to expose a second portion of the semiconductor substrate. First dual damascene metal wirings may be formed in the first dual damascene patterns and may contact the exposed first portion of the semiconductor substrate. A single body first crack stop structure may be formed in the first opening so as to contact the exposed second portion of the semiconductor substrate.
摘要翻译：示例实施例涉及具有单体裂纹停止结构的半导体器件，其被配置为减少或防止裂纹扩展和/或湿气穿透。根据示例性实施例的半导体衬底可以包括有源区和围绕有源区的裂纹停止区。层间绝缘层可以顺序堆叠在半导体衬底上。层间绝缘层可以包括第一双镶嵌图案和第一开口。可以在层间绝缘层中形成第一双镶嵌图案，以便在暴露半导体基板的第一部分的同时垂直于半导体基板的表面。第一开口可以形成在裂纹停止区域中并且可以延伸穿过层间绝缘层以暴露半导体衬底的第二部分。第一双镶嵌金属布线可以形成在第一双镶嵌图案中并且可以接触半导体基板的暴露的第一部分。可以在第一开口中形成单体第一裂纹阻挡结构，以与半导体衬底的暴露的第二部分接触。

10. 发明申请

US20100065919A1 Semiconductor Devices Including Multiple Stress Films in Interface Area 失效
标题翻译：在接口区域包括多个应力薄膜的半导体器件
公开(公告)号：US20100065919A1
公开(公告)日：2010-03-18
申请号：US12621079
申请日：2009-11-18
申请人： Seo-woo Nam , Ki-chul Kim , Young-joon Moon , Jae-ouk Choo , Hong-jae Shin , Nae-in Lee
发明人： Seo-woo Nam , Ki-chul Kim , Young-joon Moon , Jae-ouk Choo , Hong-jae Shin , Nae-in Lee
IPC分类号： H01L27/092
CPC分类号： H01L21/823412 , H01L21/823807 , H01L27/088 , H01L27/092 , H01L29/665 , H01L29/6659 , H01L29/7843 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor substrate includes a first transistor area having a first gate electrode and first source/drain areas, a second transistor area having a second gate electrode and second source/drain areas, and an interface area provided at an interface of the first transistor area and the second transistor area and having a third gate electrode. A first stress film is on the first gate electrode and the first source/drain areas of the first transistor area and at least a portion of the third gate electrode of the interface area. A second stress film is on the second gate electrode and the second source/drain areas of the second transistor area and not overlapping the first stress film on the third gate electrode of the interface area or overlapping at least a portion of the first stress film. The second stress film overlapping at least the portion of the first stress film is thinner than the second stress film in the second transistor area. Related methods are also described.
摘要翻译：半导体衬底包括具有第一栅极电极和第一源极/漏极区域的第一晶体管区域，具有第二栅极电极和第二源极/漏极区域的第二晶体管区域，以及设置在第一晶体管区域和第二晶体管区域并具有第三栅电极。第一应力膜位于第一栅极电极和第一晶体管区域的第一源极/漏极区域和界面区域的第三栅极电极的至少一部分之间。第二应力膜位于第二晶体管区域的第二栅极电极和第二源极/漏极区域上，并且不与界面区域的第三栅电极上的第一应力膜重叠或与第一应力膜的至少一部分重叠。与第一应力膜的至少部分重叠的第二应力膜比第二晶体管区域中的第二应力膜更薄。还描述了相关方法。

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