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1. 发明申请

US20050245042A1 Fabrication method for a semiconductor structure 有权
标题翻译：半导体结构的制造方法
公开(公告)号：US20050245042A1
公开(公告)日：2005-11-03
申请号：US11099962
申请日：2005-04-06
申请人： Moritz Haupt , Andreas Klipp , Hans-Peter Sperlich , Momtchil Stavrev , Stephan Wege
发明人： Moritz Haupt , Andreas Klipp , Hans-Peter Sperlich , Momtchil Stavrev , Stephan Wege
IPC分类号： H01L21/3065 , H01L21/762 , H01L21/8234 , H01L21/8242
CPC分类号： H01L21/76232
摘要： The present invention provides a fabrication method for a semiconductor structure having the steps of providing a semiconductor substrate (1); providing and patterning a silicon nitride layer (3) on the semiconductor substrate (1) as topmost layer of a trench etching mask; forming a trench (5) in a first etching step by means of the trench etching mask; conformally depositing a liner layer (10) made of silicon oxide above the resulting structure, which leaves a gap (SP) reaching into the depth in the trench (5); carrying out a V plasma etching step for forming a V profile of the line layer (10) in the trench (5); wherein the liner layer (10) is pulled back to below the top side of the silicon nitride layer (3); an etching gas mixture comprises C5F8, O2 and an inert gas is used in the V plasma etching step; the ratio (V) of C5F8/O2 lies between 2.5 and 3.5; and the selectivity of the V plasma etching step between silicon oxide and silicon nitride is at least 10.
摘要翻译：本发明提供一种半导体结构的制造方法，其具有提供半导体衬底（1）的步骤。在半导体衬底（1）上提供和图案化氮化硅层（3）作为沟槽蚀刻掩模的最顶层; 在第一蚀刻步骤中通过沟槽蚀刻掩模形成沟槽（5）; 在所得结构上保形地沉积由氧化硅制成的衬垫层（10），留下在沟槽（5）中深入的间隙（SP）; 执行V等离子体蚀刻步骤，用于在沟槽（5）中形成线层（10）的V轮廓; 其中所述衬垫层（10）被拉回到所述氮化硅层（3）的顶侧的下方; 蚀刻气体混合物包括C 5 C 8 O 2 O 2，在V等离子体蚀刻步骤中使用惰性气体; C 5 / C 2 O 2的比例（V）在2.5和3.5之间; 并且氧化硅和氮化硅之间的V等离子体蚀刻步骤的选择性为至少10。

2. 发明授权

US07265023B2 Fabrication method for a semiconductor structure 有权
标题翻译：半导体结构的制造方法
公开(公告)号：US07265023B2
公开(公告)日：2007-09-04
申请号：US11099962
申请日：2005-04-06
申请人： Moritz Haupt , Andreas Klipp , Hans-Peter Sperlich , Momtchill Stavrev , Stephan Wege
发明人： Moritz Haupt , Andreas Klipp , Hans-Peter Sperlich , Momtchill Stavrev , Stephan Wege
IPC分类号： H01L21/76
CPC分类号： H01L21/76232
摘要： The present invention provides a fabrication method for a semiconductor structure having the steps of providing a semiconductor substrate (1); providing and patterning a silicon nitride layer (3) on the semiconductor substrate (1) as topmost layer of a trench etching mask; forming a trench (5) in a first etching step by means of the trench etching mask; conformally depositing a liner layer (10) made of silicon oxide above the resulting structure, which leaves a gap (SP) reaching into the depth in the trench (5); carrying out a V plasma etching step for forming a V profile of the line layer (10) in the trench (5); wherein the liner layer (10) is pulled back to below the top side of the silicon nitride layer (3); an etching gas mixture comprises C5F8, O2 and an inert gas is used in the V plasma etching step; the ratio (V) of C5F8/O2 lies between 2.5 and 3.5; and the selectivity of the V plasma etching step between silicon oxide and silicon nitride is at least 10.
摘要翻译：本发明提供一种半导体结构的制造方法，其具有提供半导体衬底（1）的步骤。在半导体衬底（1）上提供和图案化氮化硅层（3）作为沟槽蚀刻掩模的最顶层; 在第一蚀刻步骤中通过沟槽蚀刻掩模形成沟槽（5）; 在所得结构上保形地沉积由氧化硅制成的衬垫层（10），留下在沟槽（5）中深入的间隙（SP）; 进行用于在沟槽（5）中形成线层（10）的V轮廓的V等离子体蚀刻步骤; 其中所述衬垫层（10）被拉回到所述氮化硅层（3）的顶侧的下方; 蚀刻气体混合物包括C 5 C 8 O 2 O 2，在V等离子体蚀刻步骤中使用惰性气体; C 5 / C 2 O 2的比例（V）在2.5和3.5之间; 并且氧化硅和氮化硅之间的V等离子体蚀刻步骤的选择性为至少10。

3. 发明申请

US20060003546A1 Gap-filling for isolation 审中-公开
标题翻译：间隙填充隔离
公开(公告)号：US20060003546A1
公开(公告)日：2006-01-05
申请号：US10881717
申请日：2004-06-30
申请人： Andreas Klipp , Momtchil Stavrev , Moritz Haupt
发明人： Andreas Klipp , Momtchil Stavrev , Moritz Haupt
IPC分类号： H01L21/76
CPC分类号： H01L21/76235 , H01L21/76224
摘要： A method of filling high ratio trenches on a substrate is described. First, an oxidizable layer is deposited on the substrate. Thereafter, a trench fill oxide is deposited on the substrate and on the oxidizable layer. Afterwards, the resulting structure is annealed using an oxygen containing gas such that the oxidizable layer is oxidized.
摘要翻译：描述了在衬底上填充高比率沟槽的方法。首先，将可氧化层沉积在基板上。此后，沟槽填充氧化物沉积在衬底和可氧化层上。然后，使用含氧气体使得到的结构退火，使得可氧化层被氧化。

4. 发明授权

US07718475B2 Method for manufacturing an integrated circuit including a transistor 有权
标题翻译：一种用于制造包括晶体管的集成电路的方法
公开(公告)号：US07718475B2
公开(公告)日：2010-05-18
申请号：US11786822
申请日：2007-04-13
申请人： Matthias Goldbach , Erhard Landgraf , Michael Stadtmueller , Moritz Haupt , Sven Schmidbauer , Tobias Mono , Jorg Radecker
发明人： Matthias Goldbach , Erhard Landgraf , Michael Stadtmueller , Moritz Haupt , Sven Schmidbauer , Tobias Mono , Jorg Radecker
IPC分类号： H01L21/335 , H01L29/76
CPC分类号： H01L21/28061 , H01L29/4941 , H01L29/78 , H01L29/7845
摘要： The present invention relates to a transistor comprising a gate channel area and a gate stack having mechanical stress arranged on the gate channel area.
摘要翻译：本发明涉及一种晶体管，其包括栅极沟道区和具有布置在栅极沟道区上的机械应力的栅极叠层。

5. 发明申请

US20060003523A1 Void free, silicon filled trenches in semiconductors 有权
标题翻译：半导体中无空隙硅填充沟槽
公开(公告)号：US20060003523A1
公开(公告)日：2006-01-05
申请号：US10882752
申请日：2004-07-01
申请人： Moritz Haupt
发明人： Moritz Haupt
IPC分类号： H01L21/8242 , H01L21/8244 , H01L21/8234
CPC分类号： H01L21/02667 , H01L21/02532 , H01L21/02595 , H01L21/2022 , H01L21/763 , H01L27/1087 , H01L29/66181
摘要： The present invention provides methods of producing substantially void-free trench structures. After deposition of an a-Si or polysilicon layer in a trench formed in a semiconductor, the a-Si or polysilicon is exposed to hydrogen at an elevated temperature.
摘要翻译：本发明提供了生产基本上无空隙的沟槽结构的方法。在形成在半导体中的沟槽中沉积a-Si或多晶硅层之后，a-Si或多晶硅在升高的温度下暴露于氢气。

6. 发明授权

US06528384B2 Method for manufacturing a trench capacitor 失效
标题翻译：沟槽电容器的制造方法
公开(公告)号：US06528384B2
公开(公告)日：2003-03-04
申请号：US09811800
申请日：2001-03-19
申请人： Gustav Beckmann , Moritz Haupt , Anke Krasemann , Alexandra Lamprecht , Dietmar Ottenwälder , Jens-Uwe Sachse , Martin Schrems
发明人： Gustav Beckmann , Moritz Haupt , Anke Krasemann , Alexandra Lamprecht , Dietmar Ottenwälder , Jens-Uwe Sachse , Martin Schrems
IPC分类号： H01L2120
CPC分类号： H01L27/1087 , H01L21/223
摘要： A method for manufacturing a trench capacitor uses a low-pressure gas phase doping for forming a buried plate as a capacitor plate. The use of the low-pressure gas phase doping reduces process costs and improves capacitor properties.
摘要翻译：用于制造沟槽电容器的方法使用低压气相掺杂来形成掩埋板作为电容器板。使用低压气相掺杂降低了工艺成本并改善了电容器性能。

7. 发明授权

US06645839B2 Method for improving a doping profile for gas phase doping 有权
标题翻译：改善气相掺杂掺杂特性的方法
公开(公告)号：US06645839B2
公开(公告)日：2003-11-11
申请号：US10139165
申请日：2002-05-06
申请人： Moritz Haupt , Anja Morgenschweis , Dietmar Ottenwälder , Uwe Schröder
发明人： Moritz Haupt , Anja Morgenschweis , Dietmar Ottenwälder , Uwe Schröder
IPC分类号： H01L2138
CPC分类号： H01L21/223 , H01L27/1087 , Y10S438/914 , Y10S438/923
摘要： A method for improving a doping profile using gas phase doping is described. In the method, silicon nitride and/or products of decomposition from a silicon nitride deposition are introduced in a process chamber before or during the actual gas phase doping. This allows the doping profile to be significantly improved.
摘要翻译：描述了使用气相掺杂改善掺杂分布的方法。在该方法中，氮化硅和/或氮化硅沉积的分解产物在实际气相掺杂之前或期间被引入处理室中。这允许显着改善掺杂分布。

8. 发明申请

US20080251815A1 Method for manufacturing a transistor 有权
标题翻译：制造晶体管的方法
公开(公告)号：US20080251815A1
公开(公告)日：2008-10-16
申请号：US11786822
申请日：2007-04-13
申请人： Matthias Goldbach , Erhard Landgraf , Michael Stadtmueller , Moritz Haupt , Sven Schmidbauer , Tobias Mono , Jorg Radecker
发明人： Matthias Goldbach , Erhard Landgraf , Michael Stadtmueller , Moritz Haupt , Sven Schmidbauer , Tobias Mono , Jorg Radecker
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L21/28061 , H01L29/4941 , H01L29/78 , H01L29/7845
摘要： The present invention relates to a transistor comprising a gate channel area and a gate stack having mechanical stress arranged on the gate channel area.
摘要翻译：本发明涉及一种晶体管，其包括栅极沟道区和具有布置在栅极沟道区上的机械应力的栅极叠层。

9. 发明申请

US20080067568A1 Capacitor with hemispherical silicon-germanium grains and a method for making the same 审中-公开
标题翻译：具有半球形硅锗晶粒的电容器及其制造方法
公开(公告)号：US20080067568A1
公开(公告)日：2008-03-20
申请号：US11521607
申请日：2006-09-15
申请人： Saad Abbasi , Moritz Haupt
发明人： Saad Abbasi , Moritz Haupt
IPC分类号： H01L29/94 , H01L21/20
CPC分类号： H01L29/945 , H01L27/1087 , H01L28/84 , H01L29/66181
摘要： A method of forming hemispherical silicon-germanium grains within a capacitor which includes providing the semiconductor substrate and forming the capacitor surface in the substrate is provided. The method also includes forming a layer of grained silicon-germanium on the surface of the capacitor. Another aspect of the present invention is seen in a capacitor formed in the substrate of a semiconductor device. A trench is formed in the substrate having a surface and a first capacitor electrode is formed in the semiconductor substrate around the trench. A layer of grained silicon-germanium is formed on the surface of the trench. A dielectric layer is formed on the grained silicon-germanium layer and a second capacitor electrode is formed on the dielectric layer.
摘要翻译：提供了一种在电容器内形成半球形硅 - 锗晶粒的方法，该方法包括提供半导体衬底并在衬底中形成电容器表面。该方法还包括在电容器的表面上形成粒状硅 - 锗层。在形成在半导体器件的衬底中的电容器中可以看到本发明的另一方面。在具有表面的基板中形成沟槽，并且在沟槽周围的半导体衬底中形成第一电容器电极。在沟槽的表面上形成一层粒状硅 - 锗。在晶粒硅锗层上形成电介质层，在电介质层上形成第二电容电极。

10. 发明授权

US06777303B2 Method for fabricating an insulation collar in a trench capacitor 失效
标题翻译：在沟槽电容器中制造绝缘套环的方法
公开(公告)号：US06777303B2
公开(公告)日：2004-08-17
申请号：US10153045
申请日：2002-05-22
申请人： Martin Schrems , Anke Krasemann , Moritz Haupt , Sabine Steck , Daniel Köhler
发明人： Martin Schrems , Anke Krasemann , Moritz Haupt , Sabine Steck , Daniel Köhler
IPC分类号： H01L2120
CPC分类号： H01L27/10861 , H01L29/66181
摘要： A trench capacitor is formed with an insulation collar. After the formation of the trench, firstly an insulating layer is deposited, from which layer the insulation collar will be subsequently formed. Afterward, the trench is partly filled with a sacrificial filling material and a thin patterning layer is deposited thereon. Spacers are formed from that layer and cover the insulating layer in the upper region of the trench. Afterward, the sacrificial filling material and the insulating layer are completely removed in the lower region of the trench. As a result, the insulation collar is produced in the upper region of the trench.
摘要翻译：沟槽电容器形成有绝缘套环。在形成沟槽之后，首先沉积绝缘层，从该层将形成绝缘套环。之后，沟槽部分地填充有牺牲填充材料，并且在其上沉积薄图案层。间隔由该层形成并覆盖沟槽上部区域中的绝缘层。之后，牺牲填充材料和绝缘层在沟槽的下部区域被完全去除。结果，在沟槽的上部区域中产生绝缘套环。

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