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    • 4. 发明申请
    • Fabrication method for a semiconductor structure
    • 半导体结构的制造方法
    • US20050245042A1
    • 2005-11-03
    • US11099962
    • 2005-04-06
    • Moritz HauptAndreas KlippHans-Peter SperlichMomtchil StavrevStephan Wege
    • Moritz HauptAndreas KlippHans-Peter SperlichMomtchil StavrevStephan Wege
    • H01L21/3065H01L21/762H01L21/8234H01L21/8242
    • H01L21/76232
    • The present invention provides a fabrication method for a semiconductor structure having the steps of providing a semiconductor substrate (1); providing and patterning a silicon nitride layer (3) on the semiconductor substrate (1) as topmost layer of a trench etching mask; forming a trench (5) in a first etching step by means of the trench etching mask; conformally depositing a liner layer (10) made of silicon oxide above the resulting structure, which leaves a gap (SP) reaching into the depth in the trench (5); carrying out a V plasma etching step for forming a V profile of the line layer (10) in the trench (5); wherein the liner layer (10) is pulled back to below the top side of the silicon nitride layer (3); an etching gas mixture comprises C5F8, O2 and an inert gas is used in the V plasma etching step; the ratio (V) of C5F8/O2 lies between 2.5 and 3.5; and the selectivity of the V plasma etching step between silicon oxide and silicon nitride is at least 10.
    • 本发明提供一种半导体结构的制造方法,其具有提供半导体衬底(1)的步骤。 在半导体衬底(1)上提供和图案化氮化硅层(3)作为沟槽蚀刻掩模的最顶层; 在第一蚀刻步骤中通过沟槽蚀刻掩模形成沟槽(5); 在所得结构上保形地沉积由氧化硅制成的衬垫层(10),留下在沟槽(5)中深入的间隙(SP); 执行V等离子体蚀刻步骤,用于在沟槽(5)中形成线层(10)的V轮廓; 其中所述衬垫层(10)被拉回到所述氮化硅层(3)的顶侧的下方; 蚀刻气体混合物包括C 5 C 8 O 2 O 2,在V等离子体蚀刻步骤中使用惰性气体; C 5 / C 2 O 2的比例(V)在2.5和3.5之间; 并且氧化硅和氮化硅之间的V等离子体蚀刻步骤的选择性为至少10。
    • 6. 发明授权
    • Fabrication method for a semiconductor structure
    • 半导体结构的制造方法
    • US07265023B2
    • 2007-09-04
    • US11099962
    • 2005-04-06
    • Moritz HauptAndreas KlippHans-Peter SperlichMomtchill StavrevStephan Wege
    • Moritz HauptAndreas KlippHans-Peter SperlichMomtchill StavrevStephan Wege
    • H01L21/76
    • H01L21/76232
    • The present invention provides a fabrication method for a semiconductor structure having the steps of providing a semiconductor substrate (1); providing and patterning a silicon nitride layer (3) on the semiconductor substrate (1) as topmost layer of a trench etching mask; forming a trench (5) in a first etching step by means of the trench etching mask; conformally depositing a liner layer (10) made of silicon oxide above the resulting structure, which leaves a gap (SP) reaching into the depth in the trench (5); carrying out a V plasma etching step for forming a V profile of the line layer (10) in the trench (5); wherein the liner layer (10) is pulled back to below the top side of the silicon nitride layer (3); an etching gas mixture comprises C5F8, O2 and an inert gas is used in the V plasma etching step; the ratio (V) of C5F8/O2 lies between 2.5 and 3.5; and the selectivity of the V plasma etching step between silicon oxide and silicon nitride is at least 10.
    • 本发明提供一种半导体结构的制造方法,其具有提供半导体衬底(1)的步骤。 在半导体衬底(1)上提供和图案化氮化硅层(3)作为沟槽蚀刻掩模的最顶层; 在第一蚀刻步骤中通过沟槽蚀刻掩模形成沟槽(5); 在所得结构上保形地沉积由氧化硅制成的衬垫层(10),留下在沟槽(5)中深入的间隙(SP); 进行用于在沟槽(5)中形成线层(10)的V轮廓的V等离子体蚀刻步骤; 其中所述衬垫层(10)被拉回到所述氮化硅层(3)的顶侧的下方; 蚀刻气体混合物包括C 5 C 8 O 2 O 2,在V等离子体蚀刻步骤中使用惰性气体; C 5 / C 2 O 2的比例(V)在2.5和3.5之间; 并且氧化硅和氮化硅之间的V等离子体蚀刻步骤的选择性为至少10。