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1. 发明授权

US08642419B2 Methods of forming isolation structures for semiconductor devices 有权
标题翻译：形成半导体器件隔离结构的方法
公开(公告)号：US08642419B2
公开(公告)日：2014-02-04
申请号：US13400407
申请日：2012-02-20
申请人： Stephan Kronholz , Jorg Radecker , Hans-Juergen Thees , Peter Javorka
发明人： Stephan Kronholz , Jorg Radecker , Hans-Juergen Thees , Peter Javorka
IPC分类号： H01L21/8238
CPC分类号： H01L21/76232
摘要： Disclosed herein are various methods of forming isolation structures, such as trench isolation structures, for semiconductor devices. In one example, the method includes forming a trench in a semiconducting substrate, forming a lower isolation structure in the trench, wherein the lower isolation structure has an upper surface that is below an upper surface of the substrate, and forming an upper isolation structure above the lower isolation structure, wherein a portion of the upper isolation structure is positioned within the trench.
摘要翻译：本文公开了形成用于半导体器件的隔离结构，例如沟槽隔离结构的各种方法。在一个示例中，该方法包括在半导体衬底中形成沟槽，在沟槽中形成较低的隔离结构，其中下部隔离结构具有位于衬底上表面下方的上表面，并且形成上部隔离结构所述下隔离结构，其中所述上隔离结构的一部分位于所述沟槽内。

2. 发明申请

US20070105302A1 Integrated circuit formed on a semiconductor substrate 审中-公开
标题翻译：集成电路形成在半导体衬底上
公开(公告)号：US20070105302A1
公开(公告)日：2007-05-10
申请号：US11269897
申请日：2005-11-09
申请人： Albert Birner , Andreas Weber , Frank Ludwig , Jorg Radecker , Kimberly Wilson , Kerstin Mothes
发明人： Albert Birner , Andreas Weber , Frank Ludwig , Jorg Radecker , Kimberly Wilson , Kerstin Mothes
IPC分类号： H01L21/76 , H01L21/8242
CPC分类号： H01L27/10861 , H01L27/10844 , H01L27/1087
摘要： An integrated circuit is provided, which is formed on a semiconductor substrate. The integrated circuit comprises electronic elements and isolation elements, wherein the electronic elements and the isolation elements are arranged at a top surface of the semiconductor substrate. The isolation elements each are arranged between electronic elements and electrically isolate the electronic elements from each other. Furthermore, the isolation elements comprise an upper part and a lower part, wherein the upper part is broader than the lower part.
摘要翻译：提供了形成在半导体衬底上的集成电路。集成电路包括电子元件和隔离元件，其中电子元件和隔离元件布置在半导体衬底的顶表面。隔离元件各自布置在电子元件之间并将电子元件彼此电隔离。此外，隔离元件包括上部和下部，其中上部比下部更宽。

3. 发明申请

US20130221478A1 METHODS OF FORMING ISOLATION STRUCTURES FOR SEMICONDUCTOR DEVICES BY EMPLOYING A SPIN-ON GLASS MATERIAL OR A FLOWABLE OXIDE MATERIAL 审中-公开
标题翻译：通过使用旋转玻璃材料或可流动的氧化物材料形成半导体器件的隔离结构的方法
公开(公告)号：US20130221478A1
公开(公告)日：2013-08-29
申请号：US13405713
申请日：2012-02-27
申请人： Stephan Kronholz , Jorg Radecker , Hans-Juergen Thees , Peter Javorka
发明人： Stephan Kronholz , Jorg Radecker , Hans-Juergen Thees , Peter Javorka
IPC分类号： H01L29/06 , H01L21/762
CPC分类号： H01L21/76232
摘要： Disclosed herein are various methods of forming isolation structures, such as trench isolation structures, for semiconductor devices using a spin-on glass material or a flowable oxide material. In one example, the method includes forming a trench in a semiconducting substrate, forming a lower isolation structure comprised of an insulating material in at least the trench, wherein the lower isolation structure has an upper surface that is below an upper surface of the substrate, and forming an upper isolation structure above the lower isolation structure, wherein a portion of the upper isolation structure is positioned within the trench.
摘要翻译：本文公开了用于使用旋涂玻璃材料或可流动氧化物材料的半导体器件形成隔离结构（例如沟槽隔离结构）的各种方法。在一个示例中，该方法包括在半导体衬底中形成沟槽，在至少沟槽中形成由绝缘材料构成的下隔离结构，其中下隔离结构具有位于衬底上表面下方的上表面，以及在所述下隔离结构之上形成上隔离结构，其中所述上隔离结构的一部分位于所述沟槽内。

4. 发明申请

US20080251815A1 Method for manufacturing a transistor 有权
标题翻译：制造晶体管的方法
公开(公告)号：US20080251815A1
公开(公告)日：2008-10-16
申请号：US11786822
申请日：2007-04-13
申请人： Matthias Goldbach , Erhard Landgraf , Michael Stadtmueller , Moritz Haupt , Sven Schmidbauer , Tobias Mono , Jorg Radecker
发明人： Matthias Goldbach , Erhard Landgraf , Michael Stadtmueller , Moritz Haupt , Sven Schmidbauer , Tobias Mono , Jorg Radecker
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L21/28061 , H01L29/4941 , H01L29/78 , H01L29/7845
摘要： The present invention relates to a transistor comprising a gate channel area and a gate stack having mechanical stress arranged on the gate channel area.
摘要翻译：本发明涉及一种晶体管，其包括栅极沟道区和具有布置在栅极沟道区上的机械应力的栅极叠层。

5. 发明申请

US20050095788A1 METHOD FOR FABRICATING A SEMICONDUCTOR STRUCTURE WITH AN ENCAPSULATION OF A FILLING WHICH IS USED FOR FILLING TRENCHES 失效
标题翻译：用于填充填充物填充物填充半导体结构的方法
公开(公告)号：US20050095788A1
公开(公告)日：2005-05-05
申请号：US10966994
申请日：2004-10-15
申请人： Lincoln O'Riain , Jorg Radecker
发明人： Lincoln O'Riain , Jorg Radecker
IPC分类号： H01L21/762 , H01L29/94
CPC分类号： H01L21/76224
摘要： A method for encapsulating a filling in a trench of a semiconductor substrate includes providing a first barrier layer in a trench and a second barrier layer disposed above the first barrier layer. The trench is filled with a filling, which is subsequently etched back in an upper trench section, so that a hole is produced and a filling residue remains in a lower trench section. Subsequently, a non-conformal cover layer is provided in an upper trench section, so that the cover layer of a bottom region has a first thickness greater than a second thickness of a wall region of the cover layer. The cover layer and the second barrier layer are isotropically etched-back and removed from the upper trench section, and the first barrier layer remains. The bottom region remains covered resulting in the filling residue being encapsulated by the first barrier layer and the residual cover layer.
摘要翻译：一种用于将填充物封装在半导体衬底的沟槽中的方法包括在沟槽中提供第一阻挡层，以及设置在第一阻挡层上方的第二阻挡层。沟槽填充有填充物，其随后在上沟槽部分中被回蚀，使得产生孔并且填充残留物残留在下沟槽部分中。随后，在上沟槽部分中设置非保形覆盖层，使得底部区域的覆盖层具有大于覆盖层的壁区域的第二厚度的第一厚度。覆盖层和第二阻挡层被从上沟槽部分各向同性地回蚀和去除，并且第一阻挡层保留。底部区域保持覆盖，导致填充残余物被第一阻挡层和残余覆盖层封装。

6. 发明授权

US08853051B2 Methods of recessing an active region and STI structures in a common etch process 有权
标题翻译：在普通蚀刻工艺中凹陷有源区和STI结构的方法
公开(公告)号：US08853051B2
公开(公告)日：2014-10-07
申请号：US13445596
申请日：2012-04-12
申请人： Frank Jakubowski , Jorg Radecker , Frank Ludwig
发明人： Frank Jakubowski , Jorg Radecker , Frank Ludwig
IPC分类号： H01L21/76
CPC分类号： H01L21/76232 , H01L21/76283
摘要： Generally, the present disclosure is directed to various methods of recessing an active region and an adjacent isolation structure in a common etch process. One illustrative method disclosed includes forming an isolation structure in a semiconducting substrate, wherein the isolation structure defines an active area in the substrate, forming a patterned masking layer above the substrate, wherein the patterned masking layer exposes the active area and at least a portion of the isolation structure for further processing, and performing a non-selective dry etching process on the exposed active area and the exposed portion of the isolation structure to define a recess in the substrate and to remove at least some of the exposed portions of the isolation structure.
摘要翻译：通常，本公开涉及在公共蚀刻工艺中凹陷有源区和相邻隔离结构的各种方法。所公开的一种示例性方法包括在半导体衬底中形成隔离结构，其中隔离结构限定衬底中的有源区，在衬底上形成图案化掩蔽层，其中图案化掩蔽层暴露有源区和至少部分用于进一步处理的隔离结构，以及在暴露的有源区域和隔离结构的暴露部分上执行非选择性干蚀刻工艺，以限定衬底中的凹部并且去除隔离结构的至少一些暴露部分。

7. 发明申请

US20130214392A1 METHODS OF FORMING STEPPED ISOLATION STRUCTURES FOR SEMICONDUCTOR DEVICES USING A SPACER TECHNIQUE 审中-公开
标题翻译：使用间隔技术形成半导体器件的步进隔离结构的方法
公开(公告)号：US20130214392A1
公开(公告)日：2013-08-22
申请号：US13400422
申请日：2012-02-20
申请人： Stephan Kronholz , Jorg Radecker , Hans-Juergen Thees , Peter Javorka
发明人： Stephan Kronholz , Jorg Radecker , Hans-Juergen Thees , Peter Javorka
IPC分类号： H01L29/06 , H01L21/762
CPC分类号： H01L21/76232
摘要： Disclosed herein are various methods of forming stepped isolation structures for semiconductor devices using a spacer technique. In one example, the method includes forming a first trench in a semiconducting substrate, wherein the first trench has a bottom surface, a width and a depth, the depth of the first trench being less than a target final depth for a stepped trench isolation structure, performing an etching process through the first trench on an exposed portion of the bottom surface of the first trench to form a second trench in the substrate, wherein the second trench has a width and a depth, and wherein the width of the second trench is less than the width of the first trench, and forming the stepped isolation structure in the first and second trenches.
摘要翻译：本文公开了使用间隔物技术形成用于半导体器件的阶梯式隔离结构的各种方法。在一个示例中，该方法包括在半导体衬底中形成第一沟槽，其中第一沟槽具有底表面，宽度和深度，第一沟槽的深度小于阶梯式沟槽隔离结构的目标最终深度，在所述第一沟槽的底表面的暴露部分上通过所述第一沟槽进行蚀刻处理，以在所述衬底中形成第二沟槽，其中所述第二沟槽具有宽度和深度，并且其中所述第二沟槽的宽度为小于第一沟槽的宽度，并且在第一和第二沟槽中形成阶梯式隔离结构。

8. 发明申请

US20130273709A1 METHODS OF RECESSING AN ACTIVE REGION AND STI STRUCTURES IN A COMMON ETCH PROCESS 有权
标题翻译：在常见蚀刻过程中记录活动区域和STI结构的方法
公开(公告)号：US20130273709A1
公开(公告)日：2013-10-17
申请号：US13445596
申请日：2012-04-12
申请人： Frank Jakubowski , Jorg Radecker , Frank Ludwig
发明人： Frank Jakubowski , Jorg Radecker , Frank Ludwig
IPC分类号： H01L21/76
CPC分类号： H01L21/76232 , H01L21/76283
摘要： Generally, the present disclosure is directed to various methods of recessing an active region and an adjacent isolation structure in a common etch process. One illustrative method disclosed includes forming an isolation structure in a semiconducting substrate, wherein the isolation structure defines an active area in the substrate, forming a patterned masking layer above the substrate, wherein the patterned masking layer exposes the active area and at least a portion of the isolation structure for further processing, and performing a non-selective dry etching process on the exposed active area and the exposed portion of the isolation structure to define a recess in the substrate and to remove at least some of the exposed portions of the isolation structure.
摘要翻译：通常，本公开涉及在公共蚀刻工艺中凹陷有源区和相邻隔离结构的各种方法。所公开的一种示例性方法包括在半导体衬底中形成隔离结构，其中隔离结构限定衬底中的有源区，在衬底上形成图案化掩模层，其中图案化掩蔽层暴露有源区和至少部分用于进一步处理的隔离结构，以及在暴露的有源区域和隔离结构的暴露部分上执行非选择性干蚀刻工艺，以限定衬底中的凹部并且去除隔离结构的至少一些暴露部分。

9. 发明申请

US20130214381A1 METHODS OF FORMING ISOLATION STRUCTURES FOR SEMICONDUCTOR DEVICES 有权
标题翻译：形成半导体器件隔离结构的方法
公开(公告)号：US20130214381A1
公开(公告)日：2013-08-22
申请号：US13400407
申请日：2012-02-20
申请人： Stephan Kronholz , Jorg Radecker , Hans-Juergen Thees , Peter Javorka
发明人： Stephan Kronholz , Jorg Radecker , Hans-Juergen Thees , Peter Javorka
IPC分类号： H01L29/06 , H01L21/762
CPC分类号： H01L21/76232
摘要： Disclosed herein are various methods of forming isolation structures, such as trench isolation structures, for semiconductor devices. In one example, the method includes forming a trench in a semiconducting substrate, forming a lower isolation structure in the trench, wherein the lower isolation structure has an upper surface that is below an upper surface of the substrate, and forming an upper isolation structure above the lower isolation structure, wherein a portion of the upper isolation structure is positioned within the trench.
摘要翻译：本文公开了形成用于半导体器件的隔离结构（例如沟槽隔离结构）的各种方法。在一个示例中，该方法包括在半导体衬底中形成沟槽，在沟槽中形成较低的隔离结构，其中下部隔离结构具有位于衬底上表面下方的上表面，并且形成上部隔离结构所述下隔离结构，其中所述上隔离结构的一部分位于所述沟槽内。

10. 发明授权

US07718475B2 Method for manufacturing an integrated circuit including a transistor 有权
标题翻译：一种用于制造包括晶体管的集成电路的方法
公开(公告)号：US07718475B2
公开(公告)日：2010-05-18
申请号：US11786822
申请日：2007-04-13
申请人： Matthias Goldbach , Erhard Landgraf , Michael Stadtmueller , Moritz Haupt , Sven Schmidbauer , Tobias Mono , Jorg Radecker
发明人： Matthias Goldbach , Erhard Landgraf , Michael Stadtmueller , Moritz Haupt , Sven Schmidbauer , Tobias Mono , Jorg Radecker
IPC分类号： H01L21/335 , H01L29/76
CPC分类号： H01L21/28061 , H01L29/4941 , H01L29/78 , H01L29/7845
摘要： The present invention relates to a transistor comprising a gate channel area and a gate stack having mechanical stress arranged on the gate channel area.
摘要翻译：本发明涉及一种晶体管，其包括栅极沟道区和具有布置在栅极沟道区上的机械应力的栅极叠层。

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