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1. 发明授权

US5557568A Non-volatile semiconductor memory device with verify mode for verifying data written to memory cells 失效
标题翻译：具有用于验证写入存储单元的数据的验证模式的非易失性半导体存储器件
公开(公告)号：US5557568A
公开(公告)日：1996-09-17
申请号：US427265
申请日：1995-04-24
申请人： Junichi Miyamoto , Yasuo Itoh , Yoshihisa Iwata
发明人： Junichi Miyamoto , Yasuo Itoh , Yoshihisa Iwata
IPC分类号： G11C17/00 , G11C7/02 , G11C7/10 , G11C16/02 , G11C16/06 , G11C16/10 , G11C16/34 , H01L21/8247 , H01L27/115 , G11C7/00
CPC分类号： G11C16/3459 , G11C16/10 , G11C16/3454 , G11C7/02 , G11C7/1006 , G11C7/1048
摘要： A non-volatile semiconductor memory device includes a flip-flop circuit for holding write data in one of first and second states. A bit line is connected to the flip-flop circuit via a switching element, and a transistor charges the bit line. A non-volatile memory cell, connected to the bit line and having a MOS transistor structure, stores data when a threshold thereof is set in one of first and second threshold ranges, wherein at the time of a write mode the threshold of the memory cell is shifted from the first threshold range towards the second threshold range while the flip-flop circuit remains in the first state and the shift of the threshold is not effected while the flip-flop circuit remains in the second state, and at the time of a verify mode following the write mode the bit line is kept at a charge potential by the charging transistor while the threshold remains in the second threshold range. A data setting circuit for connects one of first and second signal nodes of the flip-flop circuit to a predetermined potential when the bit line is at the charge potential in the verify mode, thereby setting the flip-flop circuit in the second state irrespective of the state prior to the verify mode.
摘要翻译：非挥发性半导体存储器件包括用于保持第一和第二状态之一的写入数据的触发器电路。位线通过开关元件连接到触发器电路，晶体管对位线进行充电。连接到位线并具有MOS晶体管结构的非易失性存储单元将其阈值设置在第一和第二阈值范围中的一个时存储数据，其中在写入模式时，存储单元的阈值在触发器电路保持在第一状态的同时触发器电路保持在第二状态，并且当触发器电路保持在第二状态时阈值的偏移不被影响时，从第一阈值范围向第二阈值范围移位，在写模式之后，当阈值保持在第二阈值范围内时，位线被充电晶体管保持在电荷电位。一种数据设定电路，用于在触发电路的第一和第二信号节点之一连接到预定电位，当位线在验证模式下处于充电电位时，从而将触发器电路设置在第二状态，而与在验证模式之前的状态。

2. 发明授权

US5452249A Non-volatile semiconductor memory device with verify mode for verifying data written to memory cells 失效
标题翻译：具有用于验证写入存储单元的数据的验证模式的非易失性半导体存储器件
公开(公告)号：US5452249A
公开(公告)日：1995-09-19
申请号：US210434
申请日：1994-03-21
申请人： Junichi Miyamoto , Yasuo Itoh , Yoshihisa Iwata
发明人： Junichi Miyamoto , Yasuo Itoh , Yoshihisa Iwata
IPC分类号： G11C17/00 , G11C7/02 , G11C7/10 , G11C16/02 , G11C16/06 , G11C16/10 , G11C16/34 , H01L21/8247 , H01L27/115 , G11C7/00
CPC分类号： G11C16/3459 , G11C16/10 , G11C16/3454 , G11C7/02 , G11C7/1006 , G11C7/1048
摘要： A non-volatile semiconductor memory device includes a flip-flop circuit for holding write data in one of first and second states. A bit line is connected to the flip-flop circuit via a switching element, and a transistor changes the bit line. A non-volatile memory cell, connected to the bit line and having a MOS transistor structure, stores data when a threshold thereof is set in one of first and second threshold ranges, wherein at the time of a write mode the threshold of the memory cell is shifted from the first threshold range towards the second threshold range while the flip-flop circuit remains in the first state and the shift of the threshold is not effected while the flip-flop circuit remains in the second state, and at the time of a verify mode following the write mode the bit line is kept at a charge potential by the charging transistor while the threshold remains in the second threshold range. A data setting circuit connects one of first and second signal nodes of the flip-flop circuit to a predetermined potential when the bit line is at the charge potential in the verify mode, thereby setting the flip-flop circuit in the second state irrespective of the state prior to the verify mode.
摘要翻译：非挥发性半导体存储器件包括用于保持第一和第二状态之一的写入数据的触发器电路。位线通过开关元件连接到触发器电路，并且晶体管改变位线。连接到位线并具有MOS晶体管结构的非易失性存储单元将其阈值设置在第一和第二阈值范围中的一个时存储数据，其中在写入模式时，存储单元的阈值在触发器电路保持在第一状态的同时触发器电路保持在第二状态，并且当触发器电路保持在第二状态时阈值的偏移不被影响时，从第一阈值范围向第二阈值范围移位，在写模式之后，当阈值保持在第二阈值范围内时，位线被充电晶体管保持在电荷电位。数据设定电路在检测模式中位线处于充电电位时，将触发器电路的第一和第二信号节点中的一个连接到预定电位，从而将触发电路设置为第二状态在验证模式之前的状态。

3. 发明授权

US06493267B2 Nonvolatile semiconductor memory device having verify function 失效
标题翻译：具有验证功能的非易失性半导体存储器件
公开(公告)号：US06493267B2
公开(公告)日：2002-12-10
申请号：US09836264
申请日：2001-04-18
申请人： Junichi Miyamoto , Yasuo Itoh , Yoshihisa Iwata
发明人： Junichi Miyamoto , Yasuo Itoh , Yoshihisa Iwata
IPC分类号： G11C1604
CPC分类号： G11C16/3459 , G11C7/1006 , G11C7/1048 , G11C16/10 , G11C16/3454
摘要： A non-volatile semiconductor memory device comprises a flip-flop circuit for holding write data in one of first and second states, a bit line connected to the flip-flop circuit via a switching element, a transistor for charging the bit line, a non-volatile memory cell, connected to the bit line and having a MOS transistor structure, for storing data when a threshold thereof is set in one of first and second threshold ranges, wherein at the time of a write mode said threshold of the memory cell is shifted from the first threshold range towards the second threshold range while the flip-flop circuit remains in the first state and the shift of the threshold is not effected while the flip-flop circuit remains in the second state, and at the time of a verify mode following the write mode the bit line is kept at a charge potential by the charging transistor while the threshold remains in the second threshold range, and a data setting circuit for connecting one of first and second signal nodes of the flip-flop circuit to a predetermined potential when the bit line is at the charge potential in the verify mode, thereby setting the flip-flop circuit in the second state irrespective of the state prior to the verify mode.
摘要翻译：一种非易失性半导体存储器件包括用于保持第一和第二状态之一的写入数据的触发器电路，经由开关元件连接到触发器电路的位线，用于对位线充电的晶体管，连接到位线并具有MOS晶体管结构的非易失性存储单元，用于当其阈值被设置在第一和第二阈值范围中的一个时存储数据，其中在写入模式时，所述存储器单元的阈值为当触发器电路保持在第一状态并且在触发器电路保持在第二状态时阈值的偏移不被影响，并且在验证时，从第一阈值范围向第二阈值范围移动模式下，当阈值保持在第二阈值范围内时，位线由充电晶体管保持在充电电位，并且数据设置电路用于连接第一和第二信号节点之一当位线在验证模式下处于电荷电位时，触发电路的电位达到预定电位，从而将触发器电路设置在第二状态，而与验证模式之前的状态无关。

4. 发明授权

US06240018B1 Nonvolatile semiconductor memory device having verify function 有权
标题翻译：具有验证功能的非易失性半导体存储器件
公开(公告)号：US06240018B1
公开(公告)日：2001-05-29
申请号：US09451142
申请日：1999-11-30
申请人： Junichi Miyamoto , Yasuo Itoh , Yoshihisa Iwata
发明人： Junichi Miyamoto , Yasuo Itoh , Yoshihisa Iwata
IPC分类号： G11C1606
CPC分类号： G11C16/3459 , G11C7/1006 , G11C7/1048 , G11C16/10 , G11C16/3454
摘要： A non-volatile semiconductor memory device comprises a flip-flop circuit for holding write data in one of first and second states, a bit line connected to the flip-flop circuit via a switching element, a transistor for charging the bit line, a non-volatile memory cell, connected to the bit line and having a MOS transistor structure, for storing data when a threshold thereof is set in one of first and second threshold ranges, wherein at the time of a write mode said threshold of the memory cell is shifted from the first threshold range towards the second threshold range while the flip-flop circuit remains in the first state and the shift of the threshold is not effected while the flip-flop circuit remains in the second state, and at the time of a verify mode following the write mode the bit line is kept at a charge potential by the charging transistor while the threshold remains in the second threshold range, and a data setting circuit for connecting one of first and second signal nodes of the flip-flop circuit to a predetermined potential when the bit line is at the charge potential in the verify mode, thereby setting the flip-flop circuit in the second state irrespective of the state prior to the verify mode.
摘要翻译：一种非易失性半导体存储器件包括用于保持第一和第二状态之一的写入数据的触发器电路，经由开关元件连接到触发器电路的位线，用于对位线充电的晶体管，连接到位线并具有MOS晶体管结构的非易失性存储单元，用于当其阈值被设置在第一和第二阈值范围中的一个时存储数据，其中在写入模式时，所述存储器单元的阈值为当触发器电路保持在第一状态并且在触发器电路保持在第二状态时阈值的偏移不被影响，并且在验证时，从第一阈值范围向第二阈值范围移动模式下，当阈值保持在第二阈值范围内时，位线由充电晶体管保持在充电电位，并且数据设置电路用于连接第一和第二信号节点之一当位线在验证模式下处于电荷电位时，触发电路的电位达到预定电位，从而将触发器电路设置在第二状态，而与验证模式之前的状态无关。

5. 发明授权

US5726882A Non-volatile semiconductor memory device with verify mode for verifying data written to memory cells 失效
标题翻译：具有用于验证写入存储单元的数据的验证模式的非易失性半导体存储器件
公开(公告)号：US5726882A
公开(公告)日：1998-03-10
申请号：US659229
申请日：1996-06-05
申请人： Junichi Miyamoto , Yasuo Itoh , Yoshihisa Iwata
发明人： Junichi Miyamoto , Yasuo Itoh , Yoshihisa Iwata
IPC分类号： G11C17/00 , G11C7/02 , G11C7/10 , G11C16/02 , G11C16/06 , G11C16/10 , G11C16/34 , H01L21/8247 , H01L27/115 , G11C7/00
CPC分类号： G11C16/3459 , G11C16/10 , G11C16/3454 , G11C7/02 , G11C7/1006 , G11C7/1048
摘要： A non-volatile semiconductor memory device includes a flip-flop circuit for holding write data in one of first and second states. A bit line is connected to the flip-flop circuit via a switching element and a transistor charges the bit line. A non-volatile memory cell, connected to the bit line and having a MOS transistor structure, stores data when a threshold thereof is set in one of first and second threshold ranges, wherein at the time of a write mode the threshold of the memory cell is shifted from the first threshold range towards the second threshold range while the flip-flop circuit remains in the first state and the shift of the threshold is not effected while the flip-flop circuit remains in the second state, and at the time of a verify mode following the write mode the bit line is kept at a charge potential by the charging transistor while the threshold remains in the second threshold range. A data setting circuit connects one of first and second signal nodes of the flip-flop circuit to a predetermined potential when the bit line is at the charge potential in the verify mode, thereby setting the flip-flop circuit in the second state irrespective of the state prior to the verify mode.
摘要翻译：非挥发性半导体存储器件包括用于保持第一和第二状态之一的写入数据的触发器电路。位线通过开关元件连接到触发器电路，并且晶体管对位线进行充电。连接到位线并具有MOS晶体管结构的非易失性存储单元将其阈值设置在第一和第二阈值范围中的一个时存储数据，其中在写入模式时，存储单元的阈值在触发器电路保持在第一状态的同时触发器电路保持在第二状态，并且当触发器电路保持在第二状态时阈值的偏移不被影响时，从第一阈值范围向第二阈值范围移位，在写模式之后，当阈值保持在第二阈值范围内时，位线被充电晶体管保持在电荷电位。数据设定电路在检测模式中位线处于充电电位时，将触发器电路的第一和第二信号节点之一连接到预定电位，从而将触发器电路设置为第二状态，而与在验证模式之前的状态。

6. 发明授权

US5388084A Non-volatile semiconductor memory device with high voltage generator 失效
标题翻译：具有高压发生器的非易失性半导体存储器件
公开(公告)号：US5388084A
公开(公告)日：1995-02-07
申请号：US128087
申请日：1993-09-29
申请人： Yasuo Itoh , Sumio Tanaka , Junichi Miyamoto , Hiroshi Nakamura , Yoshihisa Iwata , Kenichi Imamiya , Yoshihisa Sugiura
发明人： Yasuo Itoh , Sumio Tanaka , Junichi Miyamoto , Hiroshi Nakamura , Yoshihisa Iwata , Kenichi Imamiya , Yoshihisa Sugiura
IPC分类号： G11C17/00 , G11C5/14 , G11C16/06 , G11C16/30 , H01L21/8247 , H01L27/115 , G11C7/00
CPC分类号： G11C5/147 , G11C16/30
摘要： Disclosed is a semiconductor integrated circuit device, which comprises a booster circuit for boosting a source voltage, a voltage limiter having one end connected to the output terminal of the booster circuit, for limiting the output voltage of the booster circuit to a given value, and a voltage setting circuit, connected to the other end of the voltage limiter, for arbitrarily adjusting a voltage at the other end of the voltage limiter. This design can keep the output voltage of the booster circuit at a constant level and can set that output voltage to an arbitrary voltage.
摘要翻译：公开了一种半导体集成电路装置，其包括用于升压源极电压的升压电路，具有连接到升压电路的输出端子的一端的限压器，用于将升压电路的输出电压限制在给定值，以及连接到限压器的另一端的电压设定电路，用于任意地调节限压器另一端的电压。该设计可以将升压电路的输出电压保持在恒定电平，并可将该输出电压设置为任意电压。

7. 发明授权

US6023424A Nonvolatile semiconductor memory device having verify function 有权
公开(公告)号：US6023424A
公开(公告)日：2000-02-08
申请号：US213411
申请日：1998-12-17
申请人： Junichi Miyamoto , Yasuo Itoh , Yoshihisa Iwata
发明人： Junichi Miyamoto , Yasuo Itoh , Yoshihisa Iwata
IPC分类号： G11C17/00 , G11C7/02 , G11C7/10 , G11C16/02 , G11C16/06 , G11C16/10 , G11C16/34 , H01L21/8247 , H01L27/115 , G11C7/00
CPC分类号： G11C16/3459 , G11C16/10 , G11C16/3454 , G11C7/02 , G11C7/1006 , G11C7/1048
摘要： A non-volatile semiconductor memory device comprises a flip-flop circuit for holding write data in one of first and second states, a bit line connected to the flip-flop circuit via a switching element, a transistor for charging the bit line, a non-volatile memory cell, connected to the bit line and having a MOS transistor structure, for storing data when a threshold thereof is set in one of first and second threshold ranges, wherein at the time of a write mode said threshold of the memory cell is shifted from the first threshold range towards the second threshold range while the flip-flop circuit remains in the first state and the shift of the threshold is not effected while the flip-flop circuit remains in the second state, and at the time of a verify mode following the write mode the bit line is kept at a charge potential by the charging transistor while the threshold remains in the second threshold range, and a data setting circuit for connecting one of first and second signal nodes of the flip-flop circuit to a predetermined potential when the bit line is at the charge potential in the verify mode, thereby setting the flip-flop circuit in the second state irrespective of the state prior to the verify mode.

8. 发明授权

US5880994A Non-volatile semiconductor memory device having verify function 失效
标题翻译：具有验证功能的非易失性半导体存储器件
公开(公告)号：US5880994A
公开(公告)日：1999-03-09
申请号：US909727
申请日：1997-08-12
申请人： Junichi Miyamoto , Yasuo Itoh , Yoshihisa Iwata
发明人： Junichi Miyamoto , Yasuo Itoh , Yoshihisa Iwata
IPC分类号： G11C17/00 , G11C7/02 , G11C7/10 , G11C16/02 , G11C16/06 , G11C16/10 , G11C16/34 , H01L21/8247 , H01L27/115 , G11C7/00
CPC分类号： G11C16/3459 , G11C16/10 , G11C16/3454 , G11C7/02 , G11C7/1006 , G11C7/1048
摘要： A non-volatile semiconductor memory device includes a flip-flop circuit for holding write data in one of first and second states. A bit line is connected to the flip-flop circuit via a switching element and a transistor charges the bit line and line. A non-volatile memory cell, connected to the bit line and having a MOS transistor structure, stores data when a threshold thereof is set in one of first and second threshold ranges, wherein at the time of a write mode the threshold of the memory cell is shifted from the first threshold range towards the second threshold range while the flip-flop circuit remains in the first state and the shift of the threshold is not effected while the flip-flop circuit remains in the second state, and at the time of a verify mode following the write mode the bit line is kept at a charge potential by the charging transistor while the threshold remains in the second threshold range. A data setting circuit connects one of first and second signal nodes of the flip-flop circuit to a predetermined potential when the bit line is at the charge potential in the verify mode, thereby setting the flip-flop circuit in the second state irrespective of the state prior to the verify mode.
摘要翻译：非挥发性半导体存储器件包括用于保持第一和第二状态之一的写入数据的触发器电路。位线通过开关元件连接到触发器电路，晶体管对位线和线进行充电。连接到位线并具有MOS晶体管结构的非易失性存储单元将其阈值设置在第一和第二阈值范围中的一个时存储数据，其中在写入模式时，存储单元的阈值在触发器电路保持在第一状态的同时触发器电路保持在第二状态，并且当触发器电路保持在第二状态时阈值的偏移不被影响时，从第一阈值范围向第二阈值范围移位，在写模式之后，当阈值保持在第二阈值范围内时，位线被充电晶体管保持在电荷电位。数据设定电路在检测模式中位线处于充电电位时，将触发器电路的第一和第二信号节点之一连接到预定电位，从而将触发器电路设置为第二状态，而与在验证模式之前的状态。

9. 发明授权

US07139201B2 Non-volatile semiconductor memory device and memory system using the same 失效
标题翻译：非易失性半导体存储器件和使用其的存储器系统
公开(公告)号：US07139201B2
公开(公告)日：2006-11-21
申请号：US11243985
申请日：2005-10-06
申请人： Tomoharu Tanaka , Masaki Momodomi , Hideo Kato , Hiroto Nakai , Yoshiyuki Tanaka , Riichiro Shirota , Seiichi Aritome , Yasuo Itoh , Yoshihisa Iwata , Hiroshi Nakamura , Hideko Odaira , Yutaka Okamoto , Masamichi Asano , Kaoru Tokushige
发明人： Tomoharu Tanaka , Masaki Momodomi , Hideo Kato , Hiroto Nakai , Yoshiyuki Tanaka , Riichiro Shirota , Seiichi Aritome , Yasuo Itoh , Yoshihisa Iwata , Hiroshi Nakamura , Hideko Odaira , Yutaka Okamoto , Masamichi Asano , Kaoru Tokushige
IPC分类号： G11C11/34
CPC分类号： G11C29/785 , G06F11/1008 , G06F11/1068 , G06F2201/81 , G06F2212/2022 , G11C16/10 , G11C16/12 , G11C16/24 , G11C16/3436 , G11C16/344 , G11C16/3445 , G11C16/3454 , G11C16/3459 , G11C29/34 , G11C29/52
摘要： The time required for the program verify and erase verify operations can be shortened. The change of threshold values of memory cells can be suppressed even if the write and erase operations are executed repetitively. After the program and erase operations, whether the operations were properly executed can be judged simultaneously for all bit lines basing upon a change, after the pre-charge, of the potential at each bit line, without changing the column address. In the data rewrite operation, the rewrite operation is not effected for a memory cell with the data once properly written, by changing the data in the data register.
摘要翻译：可以缩短程序验证和擦除验证操作所需的时间。即使重复执行写入和擦除操作，也可以抑制存储单元的阈值变化。在编程和擦除操作之后，可以根据每个位线上的电位的预充电之后的所有位线同时判断操作，而不改变列地址。在数据重写操作中，通过改变数据寄存器中的数据，对具有一次适当写入的数据的存储单元不进行重写操作。

10. 发明授权

US06781895B1 Non-volatile semiconductor memory device and memory system using the same 失效
标题翻译：非易失性半导体存储器件和使用其的存储器系统
公开(公告)号：US06781895B1
公开(公告)日：2004-08-24
申请号：US09722474
申请日：2000-11-28
申请人： Tomoharu Tanaka , Masaki Momodomi , Hideo Kato , Hiroto Nakai , Yoshiyuki Tanaka , Riichiro Shirota , Seiichi Aritome , Yasuo Itoh , Yoshihisa Iwata , Hiroshi Nakamura , Hideko Odaira , Yutaka Okamoto , Masamichi Asano , Kaoru Tokushige
发明人： Tomoharu Tanaka , Masaki Momodomi , Hideo Kato , Hiroto Nakai , Yoshiyuki Tanaka , Riichiro Shirota , Seiichi Aritome , Yasuo Itoh , Yoshihisa Iwata , Hiroshi Nakamura , Hideko Odaira , Yutaka Okamoto , Masamichi Asano , Kaoru Tokushige
IPC分类号： G11C700
CPC分类号： G11C29/785 , G06F11/1008 , G06F11/1068 , G06F2201/81 , G06F2212/2022 , G11C16/10 , G11C16/12 , G11C16/24 , G11C16/3436 , G11C16/344 , G11C16/3445 , G11C16/3454 , G11C16/3459 , G11C29/34 , G11C29/52
摘要： The time required for the program verify and erase verify operations can be shortened. The change of threshold values of memory cells can be suppressed even if the write and erase operations are executed repetitively. After the program and erase operations, whether the operations were properly executed can be judged simultaneously for all bit lines basing upon a change, after the pre-charge, of the potential at each bit line, without changing the column address. In the data rewrite oepration, the rewrite operation is not effected for a memory cell with the data once properly written, by changing the data in the data register.
摘要翻译：可以缩短程序验证和擦除验证操作所需的时间。即使重复执行写入和擦除操作，也可以抑制存储单元的阈值变化。在编程和擦除操作之后，可以根据每个位线上的电位的预充电之后的所有位线同时判断操作，而不改变列地址。在数据重写过程中，通过改变数据寄存器中的数据，对数据一次正确写入的存储单元不会影响重写操作。

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