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1. 发明申请

US20100145515A1 ROBOT SYSTEM AND CONTROL METHOD 有权
标题翻译：机器人系统与控制方法
公开(公告)号：US20100145515A1
公开(公告)日：2010-06-10
申请号：US12538167
申请日：2009-08-10
申请人： Mitsuaki NAKANISHI , Makoto WADA
发明人： Mitsuaki NAKANISHI , Makoto WADA
IPC分类号： G05B19/04
CPC分类号： B25J9/1676 , G05B2219/42288 , G05B2219/49162 , G05B2219/50103 , G05B2219/50112
摘要： A robot system includes a robot arm driven by a motor, a collision detector that detects a collision between the robot arm and an obstacle, which is provided on the robot arm, and a stopping method selector that controls the robot arm by selecting any one of all stopping methods on the basis of the information obtained by the collision detector, thereby selecting a stopping method in accordance with the status of the collision.
摘要翻译：机器人系统包括由马达驱动的机器人手臂，检测机器人手臂与设置在机器人手臂上的障碍物之间的碰撞的碰撞检测器，以及通过选择任意一个来控制机器人手臂的停止方法选择器基于由碰撞检测器获得的信息的所有停止方法，从而根据碰撞状态选择停止方法。

2. 发明申请

US20170229301A9 METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE 审中-公开
公开(公告)号：US20170229301A9
公开(公告)日：2017-08-10
申请号：US13622089
申请日：2012-09-18
申请人： Masayuki KITAMURA , Atsuko SAKATA , Makoto WADA , Yuichi YAMAZAKI , Masayuki KATAGIRI , Akihiro KAJITA , Tadashi SAKAI , Naoshi SAKUMA , Ichiro MIZUSHIMA
发明人： Masayuki KITAMURA , Atsuko SAKATA , Makoto WADA , Yuichi YAMAZAKI , Masayuki KATAGIRI , Akihiro KAJITA , Tadashi SAKAI , Naoshi SAKUMA , Ichiro MIZUSHIMA
IPC分类号： H01L21/28 , B82Y40/00
CPC分类号： H01L21/76846 , H01L21/02373 , H01L21/76855 , H01L21/76858 , H01L21/76861 , H01L21/76876 , H01L23/53276 , H01L2221/1089 , H01L2924/0002 , H01L2924/00
摘要： According to one embodiment, a method for manufacturing a semiconductor device is disclosed. The method includes forming a co-catalyst layer and catalyst layer above a surface of a semiconductor substrate. The co-catalyst layer and catalyst layer have fcc structure. The fcc structure is formed such that (111) face of the fcc structure is to be oriented parallel to the surface of the semiconductor substrate. The catalyst includes a portion which contacts the co-catalyst layer. The portion has the fcc structure. An exposed surface of the catalyst layer is planarized by oxidation and reduction treatments. A graphene layer is formed on the catalyst layer.

3. 发明申请

US20130217226A1 METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE 审中-公开
标题翻译：制造半导体器件的方法
公开(公告)号：US20130217226A1
公开(公告)日：2013-08-22
申请号：US13622089
申请日：2012-09-18
申请人： Masayuki KITAMURA , Atsuko SAKATA , Makoto WADA , Yuichi YAMAZAKI , Masayuki KATAGIRI , Akihiro KAJITA , Tadashi SAKAI , Naoshi SAKUMA , Ichiro MIZUSHIMA
发明人： Masayuki KITAMURA , Atsuko SAKATA , Makoto WADA , Yuichi YAMAZAKI , Masayuki KATAGIRI , Akihiro KAJITA , Tadashi SAKAI , Naoshi SAKUMA , Ichiro MIZUSHIMA
IPC分类号： H01L21/28 , B82Y40/00
CPC分类号： H01L21/76846 , H01L21/02373 , H01L21/76855 , H01L21/76858 , H01L21/76861 , H01L21/76876 , H01L23/53276 , H01L2221/1089 , H01L2924/0002 , H01L2924/00
摘要： According to one embodiment, a method for manufacturing a semiconductor device is disclosed. The method includes forming a co-catalyst layer and catalyst layer above a surface of a semiconductor substrate. The co-catalyst layer and catalyst layer have fcc structure. The fcc structure is formed such that (111) face of the fcc structure is to be oriented parallel to the surface of the semiconductor substrate. The catalyst includes a portion which contacts the co-catalyst layer. The portion has the fcc structure. An exposed surface of the catalyst layer is planarized by oxidation and reduction treatments. A graphene layer is formed on the catalyst layer.
摘要翻译：根据一个实施例，公开了一种用于制造半导体器件的方法。该方法包括在半导体衬底的表面上方形成助催化剂层和催化剂层。助催化剂层和催化剂层具有fcc结构。 fcc结构形成为使得fcc结构的（111）面平行于半导体衬底的表面定向。催化剂包括与助催化剂层接触的部分。该部分具有fcc结构。通过氧化和还原处理使催化剂层的暴露表面平坦化。在催化剂层上形成石墨烯层。

4. 发明申请

US20120187569A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20120187569A1
公开(公告)日：2012-07-26
申请号：US13336247
申请日：2011-12-23
申请人： Yumi HAYASHI , Akihiro KAJITA , Makoto WADA
发明人： Yumi HAYASHI , Akihiro KAJITA , Makoto WADA
IPC分类号： H01L23/48 , H01L21/768
CPC分类号： H01L21/76877 , H01L21/76819 , H01L21/7682 , H01L21/76885 , H01L23/522 , H01L23/585 , H01L2224/32014
摘要： According to one embodiment, a semiconductor device includes a first insulating film formed on a substrate and including a first area and a second area; a groove formed in the first area of the first insulating film; a plurality of first wiring lines formed in the groove and on the first insulating film, and a second insulating film covering a top surface of the first insulating film and top surfaces of the first wiring lines, the plurality of first wiring lines are parallel to a sidewall of the groove and apart from each other with a first predetermined distance, and the first wiring line closest to the sidewall is apart from the sidewall with a second predetermined distance.
摘要翻译：根据一个实施例，半导体器件包括形成在衬底上并包括第一区域和第二区域的第一绝缘膜; 形成在第一绝缘膜的第一区域中的槽; 形成在所述槽和所述第一绝缘膜上的多个第一布线，以及覆盖所述第一绝缘膜的顶面和所述第一布线的顶面的第二绝缘膜，所述多个第一布线平行于并且第一预定距离彼此分开，并且最靠近侧壁的第一布线与第二预定距离的侧壁分开。

5. 发明申请

US20090085214A1 SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20090085214A1
公开(公告)日：2009-04-02
申请号：US12239236
申请日：2008-09-26
申请人： Makoto WADA , Kazuyuki Higashi
发明人： Makoto WADA , Kazuyuki Higashi
IPC分类号： H01L21/768 , H01L23/522
CPC分类号： H01L23/5226 , H01L21/76801 , H01L21/76829 , H01L21/76832 , H01L21/76834 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device according to one embodiment includes: a semiconductor substrate provided with a semiconductor element; a first conductive member formed on the semiconductor substrate; a first insulating film formed on the same layer as the first conductive member; a second conductive member formed so as to contact with a portion of an upper surface of the first conductive member, a second insulating film formed on the first insulating film so as to contact with a portion of the upper surface of the first conductive member, and including at least one type of element among elements contained in the first insulating film except Si; and an etching stopper film formed on the second insulating film so as to contact with a portion of a side surface of the second conductive member, and having an upper edge located below the upper surface of the second conductive member.
摘要翻译：根据一个实施例的半导体器件包括：设置有半导体元件的半导体衬底; 形成在所述半导体衬底上的第一导电构件; 形成在与所述第一导电构件相同的层上的第一绝缘膜; 形成为与第一导电构件的上表面的一部分接触的第二导电构件，形成在第一绝缘膜上以与第一导电构件的上表面的一部分接触的第二绝缘膜，以及包括除Si之外的第一绝缘膜中包含的元素中的至少一种元素; 以及形成在所述第二绝缘膜上以与所述第二导电构件的侧表面的一部分接触并且具有位于所述第二导电构件的上表面下方的上边缘的蚀刻阻挡膜。

6. 发明申请

US20080088021A1 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件的半导体器件和制造方法
公开(公告)号：US20080088021A1
公开(公告)日：2008-04-17
申请号：US11868011
申请日：2007-10-05
申请人： Makoto WADA , Takamasa Usui , Kazuya Ohuchi
发明人： Makoto WADA , Takamasa Usui , Kazuya Ohuchi
IPC分类号： H01L23/532 , H01L21/4763
CPC分类号： H01L23/485 , H01L21/76831 , H01L21/76843 , H01L21/76858 , H01L21/76864 , H01L21/76867 , H01L21/76873 , H01L2924/0002 , H01L2924/00
摘要： In one aspect of the present invention, a semiconductor device may include a semiconductor substrate, a silicide layer provided on the semiconductor substrate, a dielectric layer provided on the semiconductor substrate, a contact layer provided on the silicide layer, a metal layer provided in the dielectric layer and electrically connected to the silicide layer via the contact layer, a diffusion barrier layer provided between the dielectric layer and the metal layer, wherein the contact layer includes a first metal element provided in the metal layer, a second metal element provided in the diffusion barrier layer and at least one of a third metal provided in the silicide layer and Si element.
摘要翻译：在本发明的一个方面中，半导体器件可以包括半导体衬底，设置在半导体衬底上的硅化物层，设置在半导体衬底上的电介质层，设置在硅化物层上的接触层，设置在该半导体衬底上的金属层电介质层，经由接触层与硅化物层电连接，设置在介电层和金属层之间的扩散阻挡层，其中接触层包括设置在金属层中的第一金属元件，设置在金属层中的第二金属元件扩散阻挡层和设置在硅化物层和Si元件中的第三金属中的至少一个。

7. 发明申请

US20090289281A1 SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING SEMICONDUCTOR DEVICE 有权
标题翻译：用于制造半导体器件的半导体器件和方法
公开(公告)号：US20090289281A1
公开(公告)日：2009-11-26
申请号：US12468504
申请日：2009-05-19
申请人： Makoto WADA , Akihiro KAJITA , Kazuyuki HIGASHI
发明人： Makoto WADA , Akihiro KAJITA , Kazuyuki HIGASHI
IPC分类号： H01L29/66
CPC分类号： H01L23/522 , H01L21/76816 , H01L21/76849 , H01L21/76852 , H01L21/76885 , H01L21/76895 , H01L23/5226 , H01L27/10885 , H01L27/10888 , H01L27/11517 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes a plurality of bit lines repeatedly arranged with a same line width and pitch in a memory device region; a plurality of shunt lines arranged in a same layer as that of the plurality of bit lines, in parallel therewith, and with the same line width and pitch as those of the plurality of bit lines in the memory device region; and an upper-layer contact plug arranged from an upper-layer side so as to be connected to the plurality of shunt lines by extending over two or more shunt lines.
摘要翻译：半导体器件包括在存储器件区域中以相同的线宽和间距重复排列的多个位线; 与多个位线的平行布置在与该多个位线相同层的多个分流线，并且与存储器件区域中的多个位线的线宽和间距相同; 以及从上层侧配置的上层接触插塞，以便通过在两条或多条分路线上延伸而连接到多条分路线。

8. 发明申请

US20110256672A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US20110256672A1
公开(公告)日：2011-10-20
申请号：US13172330
申请日：2011-06-29
申请人： Makoto WADA , Kazuyuki HIGASHI , Naofumi NAKAMURA , Tsuneo UENAKA
发明人： Makoto WADA , Kazuyuki HIGASHI , Naofumi NAKAMURA , Tsuneo UENAKA
IPC分类号： H01L21/8239
CPC分类号： H01L23/481 , H01L21/76808 , H01L21/76816 , H01L23/5226 , H01L27/11551 , H01L27/11556 , H01L27/11578 , H01L29/66825 , H01L29/66833 , H01L29/7881 , H01L29/792 , H01L29/7926 , H01L2924/0002 , H01L2924/00
摘要： A nonvolatile semiconductor memory device comprises a memory string, and a wiring. The memory string comprises a semiconductor layer, a charge storage layer, and a plurality of first conductive layers. The plurality of first conductive layers comprises a stepped portion formed in a stepped shape such that positions of ends of the plurality of first conductive layers differ from one another. The wiring comprises a plurality of second conductive layers extending upwardly from an upper surface of the first conductive layers comprising the stepped portion. The plurality of second conductive layers are formed such that upper ends thereof are aligned with a surface parallel to the substrate, and such that a diameter thereof decreases from the upper end thereof to a lower end thereof. The plurality of second conductive layers are formed such that the greater a length thereof in the perpendicular direction, the larger a diameter of the upper end thereof.
摘要翻译：非易失性半导体存储器件包括存储器串和布线。存储器串包括半导体层，电荷存储层和多个第一导电层。多个第一导电层包括形成为阶梯形状的阶梯部分，使得多个第一导电层的端部的位置彼此不同。布线包括从包括台阶部分的第一导电层的上表面向上延伸的多个第二导电层。多个第二导电层形成为使得其上端与平行于基板的表面对齐，并且其直径从其上端向下端减小。多个第二导电层形成为使得其在垂直方向上的长度越大，其上端的直径越大。

9. 发明申请

US20100213526A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US20100213526A1
公开(公告)日：2010-08-26
申请号：US12615598
申请日：2009-11-10
申请人： Makoto WADA , Kazuyuki HIGASHI , Naofumi NAKAMURA , Tsuneo UENAKA
发明人： Makoto WADA , Kazuyuki HIGASHI , Naofumi NAKAMURA , Tsuneo UENAKA
IPC分类号： H01L29/792 , H01L21/8239
CPC分类号： H01L23/481 , H01L21/76808 , H01L21/76816 , H01L23/5226 , H01L27/11551 , H01L27/11556 , H01L27/11578 , H01L29/66825 , H01L29/66833 , H01L29/7881 , H01L29/792 , H01L29/7926 , H01L2924/0002 , H01L2924/00
摘要： A nonvolatile semiconductor memory device comprises a memory string, and a wiring. The memory string comprises a semiconductor layer, a charge storage layer, and a plurality of first conductive layers. The plurality of first conductive layers comprises a stepped portion formed in a stepped shape such that positions of ends of the plurality of first conductive layers differ from one another. The wiring comprises a plurality of second conductive layers extending upwardly from an upper surface of the first conductive layers comprising the stepped portion. The plurality of second conductive layers are formed such that upper ends thereof are aligned with a surface parallel to the substrate, and such that a diameter thereof decreases from the upper end thereof to a lower end thereof. The plurality of second conductive layers are formed such that the greater a length thereof in the perpendicular direction, the larger a diameter of the upper end thereof.
摘要翻译：非易失性半导体存储器件包括存储器串和布线。存储器串包括半导体层，电荷存储层和多个第一导电层。多个第一导电层包括形成为阶梯形状的阶梯部分，使得多个第一导电层的端部的位置彼此不同。布线包括从包括台阶部分的第一导电层的上表面向上延伸的多个第二导电层。多个第二导电层形成为使得其上端与平行于基板的表面对齐，并且其直径从其上端向下端减小。多个第二导电层形成为使得其在垂直方向上的长度越大，其上端的直径越大。

10. 发明申请

US20120028460A1 SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20120028460A1
公开(公告)日：2012-02-02
申请号：US13270668
申请日：2011-10-11
申请人： Makoto WADA , Kazuyuki Higashi
发明人： Makoto WADA , Kazuyuki Higashi
IPC分类号： H01L21/768
CPC分类号： H01L23/5226 , H01L21/76801 , H01L21/76829 , H01L21/76832 , H01L21/76834 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device according to one embodiment includes: a semiconductor substrate provided with a semiconductor element; a first conductive member formed on the semiconductor substrate; a first insulating film formed on the same layer as the first conductive member; a second conductive member formed so as to contact with a portion of an upper surface of the first conductive member; a second insulating film formed on the first insulating film so as to contact with a portion of the upper surface of the first conductive member, and including at least one type of element among elements contained in the first insulating film except Si; and an etching stopper film formed on the second insulating film so as to contact with a portion of a side surface of the second conductive member, and having an upper edge located below the upper surface of the second conductive member.
摘要翻译：根据一个实施例的半导体器件包括：设置有半导体元件的半导体衬底; 形成在所述半导体衬底上的第一导电构件; 形成在与所述第一导电构件相同的层上的第一绝缘膜; 形成为与所述第一导电构件的上表面的一部分接触的第二导电构件; 形成在所述第一绝缘膜上以与所述第一导电构件的所述上表面的一部分接触并且包括除了Si之外的所述第一绝缘膜中包含的元素中的至少一种元素的第二绝缘膜; 以及形成在所述第二绝缘膜上以与所述第二导电构件的侧表面的一部分接触并且具有位于所述第二导电构件的上表面下方的上边缘的蚀刻阻挡膜。

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