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1. 发明申请

US20170229301A9 METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE 审中-公开
公开(公告)号：US20170229301A9
公开(公告)日：2017-08-10
申请号：US13622089
申请日：2012-09-18
申请人： Masayuki KITAMURA , Atsuko SAKATA , Makoto WADA , Yuichi YAMAZAKI , Masayuki KATAGIRI , Akihiro KAJITA , Tadashi SAKAI , Naoshi SAKUMA , Ichiro MIZUSHIMA
发明人： Masayuki KITAMURA , Atsuko SAKATA , Makoto WADA , Yuichi YAMAZAKI , Masayuki KATAGIRI , Akihiro KAJITA , Tadashi SAKAI , Naoshi SAKUMA , Ichiro MIZUSHIMA
IPC分类号： H01L21/28 , B82Y40/00
CPC分类号： H01L21/76846 , H01L21/02373 , H01L21/76855 , H01L21/76858 , H01L21/76861 , H01L21/76876 , H01L23/53276 , H01L2221/1089 , H01L2924/0002 , H01L2924/00
摘要： According to one embodiment, a method for manufacturing a semiconductor device is disclosed. The method includes forming a co-catalyst layer and catalyst layer above a surface of a semiconductor substrate. The co-catalyst layer and catalyst layer have fcc structure. The fcc structure is formed such that (111) face of the fcc structure is to be oriented parallel to the surface of the semiconductor substrate. The catalyst includes a portion which contacts the co-catalyst layer. The portion has the fcc structure. An exposed surface of the catalyst layer is planarized by oxidation and reduction treatments. A graphene layer is formed on the catalyst layer.

2. 发明申请

US20130217226A1 METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE 审中-公开
标题翻译：制造半导体器件的方法
公开(公告)号：US20130217226A1
公开(公告)日：2013-08-22
申请号：US13622089
申请日：2012-09-18
申请人： Masayuki KITAMURA , Atsuko SAKATA , Makoto WADA , Yuichi YAMAZAKI , Masayuki KATAGIRI , Akihiro KAJITA , Tadashi SAKAI , Naoshi SAKUMA , Ichiro MIZUSHIMA
发明人： Masayuki KITAMURA , Atsuko SAKATA , Makoto WADA , Yuichi YAMAZAKI , Masayuki KATAGIRI , Akihiro KAJITA , Tadashi SAKAI , Naoshi SAKUMA , Ichiro MIZUSHIMA
IPC分类号： H01L21/28 , B82Y40/00
CPC分类号： H01L21/76846 , H01L21/02373 , H01L21/76855 , H01L21/76858 , H01L21/76861 , H01L21/76876 , H01L23/53276 , H01L2221/1089 , H01L2924/0002 , H01L2924/00
摘要： According to one embodiment, a method for manufacturing a semiconductor device is disclosed. The method includes forming a co-catalyst layer and catalyst layer above a surface of a semiconductor substrate. The co-catalyst layer and catalyst layer have fcc structure. The fcc structure is formed such that (111) face of the fcc structure is to be oriented parallel to the surface of the semiconductor substrate. The catalyst includes a portion which contacts the co-catalyst layer. The portion has the fcc structure. An exposed surface of the catalyst layer is planarized by oxidation and reduction treatments. A graphene layer is formed on the catalyst layer.
摘要翻译：根据一个实施例，公开了一种用于制造半导体器件的方法。该方法包括在半导体衬底的表面上方形成助催化剂层和催化剂层。助催化剂层和催化剂层具有fcc结构。 fcc结构形成为使得fcc结构的（111）面平行于半导体衬底的表面定向。催化剂包括与助催化剂层接触的部分。该部分具有fcc结构。通过氧化和还原处理使催化剂层的暴露表面平坦化。在催化剂层上形成石墨烯层。

3. 发明申请

US20130084704A1 METHOD FOR MANUFACTURING MICROSTRUCTURE 有权
标题翻译：制造微结构的方法
公开(公告)号：US20130084704A1
公开(公告)日：2013-04-04
申请号：US13424811
申请日：2012-03-20
申请人： Kei WATANABE , Ichiro MIZUSHIMA
发明人： Kei WATANABE , Ichiro MIZUSHIMA
IPC分类号： H01L21/311
CPC分类号： B81C1/00492 , B81C2201/0149 , B81C2201/0198 , H01L21/0337 , H01L21/3086 , H01L21/31144 , H01L21/32139
摘要： According to one embodiment, a method for manufacturing a microstructure includes forming a guide film on a patterning material, forming a cured film, forming a mask member, and performing processing of the patterning material using the mask member as a mask. An opening is made in the guide film. An upper surface of the guide film is hydrophilic, a side surface of the opening is hydrophobic. The forming the cured film includes applying a solution to cover the patterning material and the guide film, separating the solution into a hydrophobic block and a hydrophilic block, and curing the solution. The solution contains an amphiphilic polymer having a hydrophobic portion and a hydrophilic portion. A length of the hydrophobic portion is longer than a length of the hydrophilic portion. The mask member is formed by removing the hydrophilic block from the cured film.
摘要翻译：根据一个实施例，微结构的制造方法包括在图案形成材料上形成引导膜，形成固化膜，形成掩模部件，并使用掩模部件作为掩模进行图案形成材料的处理。在引导膜中形成一个开口。引导膜的上表面是亲水性的，开口的侧表面是疏水性的。形成固化膜包括施加溶液以覆盖图案形成材料和引导膜，将溶液分离成疏水性嵌段和亲水性嵌段，并固化该溶液。该溶液含有具有疏水部分和亲水部分的两亲性聚合物。疏水部分的长度长于亲水部分的长度。通过从固化膜除去亲水性嵌段形成掩模构件。

4. 发明申请

US20090108412A1 SEMICONDUCTOR SUBSTRATE AND METHOD FOR MANUFACTURING A SEMICONDUCTOR SUBSTRATE 审中-公开
标题翻译：半导体衬底及制造半导体衬底的方法
公开(公告)号：US20090108412A1
公开(公告)日：2009-04-30
申请号：US12258650
申请日：2008-10-27
申请人： Hiroshi ITOKAWA , Ichiro MIZUSHIMA , Akiko NOMACHI , Yoshitaka TSUNASHIMA
发明人： Hiroshi ITOKAWA , Ichiro MIZUSHIMA , Akiko NOMACHI , Yoshitaka TSUNASHIMA
IPC分类号： H01L29/04 , H01L21/18 , H01L21/30
CPC分类号： H01L21/26506 , H01L21/02381 , H01L21/02433 , H01L21/02532 , H01L21/02609 , H01L21/02667 , H01L21/823412 , H01L21/823481 , H01L21/84 , H01L29/045
摘要： A semiconductor substrate includes: a silicon support substrate with a first crystal orientation; a silicon functional substrate which is formed on the silicon support substrate and which has a first crystalline region with a crystal orientation different from the first crystal orientation of the silicon support substrate and a second crystalline region with a crystal orientation equal to the first crystal orientation of the silicon support substrate; and a defect creation-preventing region formed at an interface between the first crystalline region and the second crystalline region of the silicon functional substrate so as to be at least elongated to a main surface of the silicon support substrate.
摘要翻译：半导体衬底包括：具有第一晶体取向的硅支撑衬底; 硅功能基板，其形成在所述硅支撑基板上，并且具有晶体取向不同于所述硅支撑基板的所述第一晶体取向的第一结晶区域和具有与所述第一晶体取向相等的晶体取向的第二晶体区域硅支撑基板; 以及形成在所述硅功能基板的所述第一结晶区域和所述第二结晶区域之间的界面处以至少延伸到所述硅支撑基板的主表面的缺陷创建防止区域。

5. 发明申请

US20080128813A1 Semiconductor Device and Manufacturing Method Thereof 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20080128813A1
公开(公告)日：2008-06-05
申请号：US11947546
申请日：2007-11-29
申请人： Ichiro MIZUSHIMA , Tomoyasu Inoue
发明人： Ichiro MIZUSHIMA , Tomoyasu Inoue
IPC分类号： H01L27/12 , H01L21/84
CPC分类号： H01L27/1203 , H01L21/76256 , H01L21/84 , H01L27/1207 , H01L29/045
摘要： A semiconductor device includes: a semiconductor substrate; and a plurality of crystalline insulation films which are formed on the semiconductor substrate and have at least two crystalline insulation films. Crystal orientations of the at least two crystalline insulation films are different from each other.
摘要翻译：半导体器件包括：半导体衬底; 以及形成在半导体衬底上并具有至少两个结晶绝缘膜的多个结晶绝缘膜。至少两个结晶绝缘膜的晶体取向彼此不同。

6. 发明申请

US20110233646A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME 失效
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US20110233646A1
公开(公告)日：2011-09-29
申请号：US12886135
申请日：2010-09-20
申请人： Ichiro MIZUSHIMA , Shinji Mori , Yoshiaki Fukuzumi , Fumiki Aiso
发明人： Ichiro MIZUSHIMA , Shinji Mori , Yoshiaki Fukuzumi , Fumiki Aiso
IPC分类号： H01L29/792 , H01L21/336
CPC分类号： H01L29/792 , H01L27/11578 , H01L27/11582 , H01L29/66833 , H01L29/7926
摘要： According to one embodiment, a nonvolatile semiconductor memory device is provided in which memory strings, which are formed by providing a plurality of transistors having gate electrode films on sides of columnar semiconductor films in a height direction of the columnar semiconductor films via charge storage layers, are substantially perpendicularly arranged in a matrix shape on a substrate. A coupling section made of a semiconductor material that connects lower portions of the columnar semiconductor films forming a pair of the memory strings adjacent to each other in a predetermined direction is provided. Each of the columnar semiconductor films is formed of a generally single-crystal-like germanium film or silicon germanium film.
摘要翻译：根据一个实施例，提供了一种非易失性半导体存储器件，其中通过在柱状半导体膜的高度方向上经由电荷存储层提供在柱状半导体膜的侧面上具有栅电极膜的多个晶体管形成的存储器串，基本上垂直地以矩阵形式布置在基底上。提供了一种由半导体材料制成的耦合部分，其连接形成在预定方向上彼此相邻的一对存储器串的柱状半导体膜的下部。每个柱状半导体膜由大致单晶状锗膜或硅锗膜形成。

7. 发明申请

US20090152623A1 FIN TRANSISTOR 有权
标题翻译： FIN晶体管
公开(公告)号：US20090152623A1
公开(公告)日：2009-06-18
申请号：US12335701
申请日：2008-12-16
申请人： Masakazu GOTO , Nobutoshi AOKI , Takashi IZUMIDA , Kimitoshi OKANO , Satoshi INABA , Ichiro MIZUSHIMA
发明人： Masakazu GOTO , Nobutoshi AOKI , Takashi IZUMIDA , Kimitoshi OKANO , Satoshi INABA , Ichiro MIZUSHIMA
IPC分类号： H01L29/78
CPC分类号： H01L29/785 , H01L29/7845
摘要： A fin transistor includes: a substrate; a plurality of semiconductor fins formed on the substrate; a gate electrode covering a channel region of the semiconductor fins; and a member as a stress source for the semiconductor fins included in a region of the gate electrode and the region provided between the semiconductor fins, and the member being made of a different material from the gate electrode.
摘要翻译：翅片晶体管包括：衬底; 形成在所述基板上的多个半导体翅片; 覆盖半导体鳍片的沟道区域的栅电极; 以及作为用于包括在栅极电极的区域中的半导体鳍片的应力源的构件和设置在半导体鳍片之间的区域，并且该构件由与栅电极不同的材料制成。

8. 发明申请

US20110237052A1 METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE 审中-公开
标题翻译：制造半导体器件的方法
公开(公告)号：US20110237052A1
公开(公告)日：2011-09-29
申请号：US13047136
申请日：2011-03-14
申请人： Ichiro MIZUSHIMA , Shinji Mori
发明人： Ichiro MIZUSHIMA , Shinji Mori
IPC分类号： H01L21/20
CPC分类号： H01L21/02532 , H01L21/02535 , H01L21/02601 , H01L21/02667
摘要： According to an embodiment of the present invention, a method for manufacturing a semiconductor device includes: forming an epitaxial crystal from a seed crystal exposed between first and second structures; heating the epitaxial crystal at a temperature equal to or less than a melting point of the epitaxial crystal to migrate the epitaxial crystal; and migrating the epitaxial crystal to form plural aggregates between the first and second structures.
摘要翻译：根据本发明的实施例，一种用于制造半导体器件的方法包括：从在第一和第二结构之间暴露的晶种形成外延晶体; 在等于或小于外延晶体的熔点的温度下加热外延晶体以迁移外延晶体; 并且迁移所述外延晶体以在所述第一和第二结构之间形成多个聚集体。

9. 发明申请

US20130020706A1 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20130020706A1
公开(公告)日：2013-01-24
申请号：US13423081
申请日：2012-03-16
申请人： Takashi FURUHASHI , Miyoko SHIMADA , Ichiro MIZUSHIMA , Shinichi NAKAO
发明人： Takashi FURUHASHI , Miyoko SHIMADA , Ichiro MIZUSHIMA , Shinichi NAKAO
IPC分类号： H01L23/52 , H01L21/31
CPC分类号： H01L21/7682 , H01L21/31053 , H01L21/76834 , H01L21/76885
摘要： In accordance with an embodiment, a semiconductor device includes a substrate, a line-and-space structure, a first film and a second film. The line-and-space structure includes line patterns arranged on the substrate parallel to one another at a predetermined distance. The first film is formed on side surfaces and bottom surfaces of the line patterns by an insulating film material. The second film is formed on the line-and-space structure across a space between the line patterns by a material showing low wettability to the first film. Space between the line patterns includes an air gap in which at least a bottom surface of the first film is totally exposed.
摘要翻译：根据实施例，半导体器件包括衬底，线间距结构，第一膜和第二膜。线间空间结构包括以预定距离彼此平行布置在基板上的线图案。第一膜通过绝缘膜材料形成在线图案的侧表面和底表面上。通过对第一膜显示低润湿性的材料，在线图形之间的空间结构上形成第二膜。线图案之间的空间包括其中至少第一膜的底表面完全暴露的气隙。

10. 发明申请

US20090263957A1 METHOD OF FABRICATING SEMICONDUCTOR DEVICE 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20090263957A1
公开(公告)日：2009-10-22
申请号：US12401453
申请日：2009-03-10
申请人： Ichiro MIZUSHIMA , Shinji Mori , Masahiko Murano , Tsutomu Sato , Takashi Nakao , Hiroshi Itokawa
发明人： Ichiro MIZUSHIMA , Shinji Mori , Masahiko Murano , Tsutomu Sato , Takashi Nakao , Hiroshi Itokawa
IPC分类号： H01L21/20
CPC分类号： H01L21/02636 , H01L21/02381 , H01L21/02532 , H01L21/0262
摘要： A method of fabricating a semiconductor device according to one embodiment includes: exposing a surface of a semiconductor substrate to a halogen-containing gas that contains at least one of Si and Ge, the semiconductor substrate being provided with a member comprising an oxide and consisting mainly of Si; and exposing the surface of the semiconductor substrate to an atmosphere containing at least one of a Si-containing gas not containing halogen and a Ge-containing gas not containing halogen after starting exposure of the surface of the semiconductor substrate to the halogen-containing gas, thereby epitaxially growing a crystal film containing at least one of Si and Ge on the surface.
摘要翻译：根据一个实施例的制造半导体器件的方法包括：将半导体衬底的表面暴露于含有Si和Ge中的至少一种的含卤素的气体，所述半导体衬底设置有包含氧化物的构件，主要由的Si; 以及将半导体衬底的表面开始暴露于含卤素气体之后，将半导体衬底的表面暴露于含有不含卤素的含Si气体和不含卤素的含Ge气体中的至少一种的气氛中，从而在表面上外延生长含有Si和Ge中的至少一种的晶体膜。

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