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1. 发明授权

US06281584B1 Integrated circuit with improved adhesion between interfaces of conductive and dielectric surfaces 有权
标题翻译：集成电路，具有改善导电和电介质表面界面之间的粘附性
公开(公告)号：US06281584B1
公开(公告)日：2001-08-28
申请号：US09373482
申请日：1999-08-12
申请人： Minh Van Ngo , Richard J. Huang , Guarionex Morales
发明人： Minh Van Ngo , Richard J. Huang , Guarionex Morales
IPC分类号： H01L2348
CPC分类号： H01L21/31629 , H01L21/76801 , H01L23/5226 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： A method for using low dielectric SiOF in a process to manufacture semiconductor products, comprising the steps of obtaining a layer of SiOF, and depleting fluorine from a surface of the SiOF layer. In a preferred embodiment, the depleting step comprises the step of treating the surface of the layer of SiOF with a plasma containing ammonia. It is further preferred that the treated surface be passivated by a nitrite plasma. The invention also encompasses a semiconductor chip comprising an integrated circuit with at least a first and second layers, and with a dielective layer of SiOF disposed between the layers, wherein the SiOF dielectric layer includes a first region at one edge thereof which is depleted of fluorine to a predetermined depth.
摘要翻译：一种在制造半导体产品的方法中使用低电介质SiOF的方法，包括以下步骤：获得SiOF层，并从SiOF层的表面上消耗氟。在优选的实施方案中，耗尽步骤包括用含有氨的等离子体处理SiOF层的表面的步骤。进一步优选的是，经过处理的表面被亚硝酸盐等离子体钝化。本发明还包括半导体芯片，其包括具有至少第一和第二层的集成电路，以及设置在层之间的SiOF的半导体层，其中SiOF电介质层包括其一个边缘处的第一区域，该第一区域耗尽氟到预定深度。

2. 发明授权

US06444593B1 Surface treatment of low-K SiOF to prevent metal interaction 有权
标题翻译：表面处理低K SiOF以防止金属相互作用
公开(公告)号：US06444593B1
公开(公告)日：2002-09-03
申请号：US09373483
申请日：1999-08-12
申请人： Minh Van Ngo , Richard J. Huang , Guarionex Morales
发明人： Minh Van Ngo , Richard J. Huang , Guarionex Morales
IPC分类号： H01L21425
CPC分类号： H01L21/31629 , H01L21/02131 , H01L21/02274 , H01L21/02332 , H01L21/0234 , H01L21/02362 , H01L21/76801 , H01L21/76807 , H01L21/76814 , H01L21/76826 , H01L21/76831 , H01L21/76832 , H01L21/76834 , H01L23/5226 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： A method for using low dielectric SiOF in a process to manufacture semiconductor products, comprising the steps of obtaining a layer of SiOF, and depleting fluorine from a surface of the SiOF layer. In a preferred embodiment, the depleting step comprises the step of treating the surface of the layer of SiOF with a plasma containing ammonia. It is further preferred that the treated surface be passivated by a nitrite plasma. The invention also encompasses a semiconductor chip comprising an integrated circuit with at least a first and second layers, and with a dielective layer of SiOF disposed between the layers, wherein the SiOF dielectric layer includes a first region at one edge thereof which depleted of fluorine to a predetermined depth.
摘要翻译：一种在制造半导体产品的方法中使用低电介质SiOF的方法，包括以下步骤：获得SiOF层，并从SiOF层的表面上消耗氟。在优选的实施方案中，耗尽步骤包括用含有氨的等离子体处理SiOF层的表面的步骤。进一步优选的是，经过处理的表面被亚硝酸盐等离子体钝化。本发明还包括半导体芯片，其包括具有至少第一和第二层的集成电路，以及设置在层之间的SiOF的半导体层，其中所述SiOF电介质层包括其一个边缘处的第一区域，所述第一区域耗尽氟至预定深度。

3. 发明授权

US06235632B1 Tungsten plug formation 失效
标题翻译：钨塞形成
公开(公告)号：US06235632B1
公开(公告)日：2001-05-22
申请号：US09006495
申请日：1998-01-13
申请人： Takeshi Nogami , Guarionex Morales , Minh Van Ngo
发明人： Takeshi Nogami , Guarionex Morales , Minh Van Ngo
IPC分类号： H01L2144
CPC分类号： H01L21/76864 , H01L21/76841 , H01L21/76843 , H01L21/76855 , H01L21/76877 , H01L21/76895
摘要： In a preferred embodiment, there is disclosed a method of forming a tungsten plug at the via level. A metal line is formed in a top portion of a first insulating layer. A second insulating layer is formed on the first insulating layer and over an exposed surface of the metal line. An etching process is applied to a region of the second insulating layer formed over the exposed surface of the metal line to create a contact hole within the region. The metal line is exposed at the region. A tungsten nitride thin film is deposited over the second insulating layer and the exposed metal line. A blanket tungsten thin film is deposited to fill the contact hole and to form a planar layer successively to the depositing of the tungsten nitride thin film. The tungsten nitride thin film and the blanket tungsten thin film are chemically mechanically polished until the upper surface of the second insulating layer is exposed.
摘要翻译：在优选实施例中，公开了一种在通孔级形成钨丝塞的方法。金属线形成在第一绝缘层的顶部。在第一绝缘层上和金属线的暴露表面上形成第二绝缘层。对形成在金属线的暴露表面上的第二绝缘层的区域施加蚀刻处理，以在该区域内形成接触孔。金属线暴露在该地区。在第二绝缘层和暴露的金属线上沉积氮化钨薄膜。沉积覆盖的钨薄膜以填充接触孔并且连续地形成平坦层以沉积氮化钨薄膜。化学机械抛光氮化钨薄膜和覆盖钨薄膜，直到第二绝缘层的上表面露出。

4. 发明授权

US06033584A Process for reducing copper oxide during integrated circuit fabrication 失效
标题翻译：在集成电路制造期间减少氧化铜的工艺
公开(公告)号：US06033584A
公开(公告)日：2000-03-07
申请号：US995499
申请日：1997-12-22
申请人： Minh Van Ngo , Guarionex Morales , Takeshi Nogami
发明人： Minh Van Ngo , Guarionex Morales , Takeshi Nogami
IPC分类号： H01L21/311 , H01L21/768 , H01L21/00
CPC分类号： H01L21/31122 , H01L21/76838
摘要： A method of integrated circuit fabrication creating copper interconnect structures wherein the formation of copper oxide is reduced or eliminated by etching away the copper oxide performing an H.sub.2 plasma treatment in a plasma enhanced chemical vapor deposition chamber.
摘要翻译：一种形成铜互连结构的集成电路制造方法，其中通过在等离子体增强化学气相沉积室中蚀刻掉执行H 2等离子体处理的氧化铜来减少或消除氧化铜的形成。

5. 发明授权

US06492258B1 METHOD FOR REDUCING STRESS-INDUCED VOIDS FOR 0.25-&mgr;M AND SMALLER SEMICONDUCTOR CHIP TECHNOLOGY BY ANNEALING INTERCONNECT LINES AND USING LOW BIAS VOLTAGE AND LOW INTERLAYER DIELECTRIC DEPOSITION RATE AND SEMICONDUCTOR CHIP MADE THEREBY 有权
标题翻译：用于通过退火互连线和使用低偏置电压和低中间层介电沉积速率和半导体芯片制造来减少0.25微米和小型半导体芯片技术的应力诱发电位的方法
公开(公告)号：US06492258B1
公开(公告)日：2002-12-10
申请号：US09881831
申请日：2001-06-14
申请人： Minh Van Ngo , Paul R. Besser , Matthew Buynoski , John Caffall , Nick Maccrae , Richard J. Huang , Khanh Tran
发明人： Minh Van Ngo , Paul R. Besser , Matthew Buynoski , John Caffall , Nick Maccrae , Richard J. Huang , Khanh Tran
IPC分类号： H01L214763
CPC分类号： H01L21/7685 , H01L21/76837 , H01L21/76858 , H01L21/76885 , H01L23/53223 , H01L2221/1078 , H01L2924/0002 , H01L2924/00
摘要： A method for making 0.25-micron semiconductor chips includes annealing the metal interconnect lines prior to depositing an inter-layer dielectric (ILD) between the lines. During annealing, an alloy of aluminum and titanium forms, which subsequently volumetrically contracts, with the contraction being absorbed by the aluminum. Because the alloy is reacted prior to ILD deposition, however, the aluminum is not constrained by the ILD when it attempts to absorb the contraction of the alloy. Consequently, the likelihood of undesirable void formation. in the interconnect lines is reduced. The likelihood of undesirable void formation is still further reduced during the subsequent ILD gapfill deposition process by using relatively low bias power to reduce vapor deposition temperature. and by using relatively low source gas deposition flow rates to reduce flow-induced compressive stress on the interconnect lines during ILD formation.
摘要翻译：制造0.25微米半导体芯片的方法包括在线之间沉积层间电介质（ILD）之前退火金属互连线。在退火期间，形成铝和钛的合金，其随后容积收缩，铝的收缩被铝吸收。因为合金在ILD沉积之前反应，所以当铝试图吸收合金的收缩时，铝不受ILD的约束。因此，形成不希望的空隙的可能性。在互连线路中减少。在随后的ILD间隙填充沉积过程中，通过使用相对低的偏压功率来降低气相沉积温度，仍然进一步降低了不希望的空隙形成的可能性。并且通过使用相对低的源气体沉积流速来减少在ILD形成期间在互连线上的流动引起的压缩应力。

6. 发明授权

US06472336B1 Forming an encapsulating layer after deposition of a dielectric comprised of corrosive material 有权
标题翻译：在沉积由腐蚀性材料构成的电介质之后形成封装层
公开(公告)号：US06472336B1
公开(公告)日：2002-10-29
申请号：US09511585
申请日：2000-02-23
申请人： Suzette K. Pangrle , Minh Van Ngo , Richard J. Huang
发明人： Suzette K. Pangrle , Minh Van Ngo , Richard J. Huang
IPC分类号： H01L2131
CPC分类号： H01L21/76801 , C23C16/401 , H01L21/31629 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： Insulating material is formed to surround interconnect structures of an integrated circuit. A first semiconductor wafer is placed in a reaction chamber for forming the insulating material surrounding the interconnect structures of the integrated circuit on the first semiconductor wafer. A corrosive dielectric material having low dielectric constant is deposited to surround the interconnect structures, and the corrosive dielectric material fills any gaps between the interconnect structures. Deposition of the corrosive dielectric material is performed within the reaction chamber, and the corrosive dielectric material is deposited on the reaction chamber during deposition of the corrosive dielectric material on the first semiconductor wafer. An encapsulating layer is formed over the corrosive dielectric material on the first semiconductor wafer and on the reaction chamber to prevent contact of the corrosive dielectric material to any exposed structure of a second semiconductor wafer to be subsequently placed into the reaction chamber when such an exposed structure is reactive with the corrosive dielectric material.
摘要翻译：绝缘材料形成为围绕集成电路的互连结构。将第一半导体晶片放置在用于形成围绕第一半导体晶片上的集成电路的互连结构的绝缘材料的反应室中。沉积具有低介电常数的腐蚀介电材料以包围互连结构，并且腐蚀介电材料填充互连结构之间的任何间隙。在反应室内进行腐蚀性电介质材料的沉积，并且在第一半导体晶片上沉积腐蚀性电介质材料期间，腐蚀性电介质材料沉积在反应室上。在第一半导体晶片上和反应室上的腐蚀介质材料上形成封装层，以防止腐蚀性电介质材料与任何暴露的第二半导体晶片的结构接触，随后将其放置在反应室中，与腐蚀性介电材料反应。

7. 发明授权

US06596631B1 Method of forming copper interconnect capping layers with improved interface and adhesion 有权
标题翻译：形成具有改善界面和粘合性的铜互连封盖层的方法
公开(公告)号：US06596631B1
公开(公告)日：2003-07-22
申请号：US09626455
申请日：2000-07-26
申请人： Minh Van Ngo , Hartmut Ruelke , Lothar Mergili , Joerg Hohage , Lu You , Robert A. Huertas , Richard J. Huang
发明人： Minh Van Ngo , Hartmut Ruelke , Lothar Mergili , Joerg Hohage , Lu You , Robert A. Huertas , Richard J. Huang
IPC分类号： H01L244
CPC分类号： H01L21/76883 , H01L21/76834 , Y10S438/913
摘要： The integrity of the interface and adhesion between a barrier or capping layer and a Cu or Cu alloy interconnect member is significantly enhanced by delaying and/or slowly ramping up the introduction of silane to deposit a silicon nitride capping layer after treating the exposed planarized surface of the Cu or Cu alloy with an ammonia-containing plasma. Other embodiments include purging the reaction chamber with nitrogen at elevated temperature to remove residual gases prior to introducing the wafer for plasma treatment.
摘要翻译：通过在处理暴露的平坦化表面之后延迟和/或缓慢地升高硅烷的引入以沉积氮化硅覆盖层来显着增强界面的完整性和阻挡层或覆盖层与Cu或Cu合金互连构件之间的粘合性具有含氨等离子体的Cu或Cu合金。其他实施方案包括在升高的温度下用氮气吹扫反应室以在引入用于等离子体处理的晶片之前去除残留气体。

8. 发明授权

US06329718B1 Method for reducing stress-induced voids for 0.25m&mgr; and smaller semiconductor chip technology by annealing interconnect lines and using low bias voltage and low interlayer dielectric deposition rate and semiconductor chip made thereby 失效
标题翻译：通过退火互连线和使用低偏压和低层间电介质沉积速率减少应力诱发的0.25μm及更小的半导体芯片技术的空穴的方法，由此制成半导体芯片
公开(公告)号：US06329718B1
公开(公告)日：2001-12-11
申请号：US09105775
申请日：1998-06-26
申请人： Minh Van Ngo , Paul R. Besser , Matthew Buynoski , John Caffall , Nick MacCrae , Richard J. Huang , Khanh Tran
发明人： Minh Van Ngo , Paul R. Besser , Matthew Buynoski , John Caffall , Nick MacCrae , Richard J. Huang , Khanh Tran
IPC分类号： H01L2348
CPC分类号： H01L21/7685 , H01L21/76837 , H01L21/76858 , H01L21/76885 , H01L23/53223 , H01L2221/1078 , H01L2924/0002 , H01L2924/00
摘要： A method for making 0.25 micron semiconductor chips includes annealing the metal interconnect lines prior to depositing an inter-layer dielectric (ILD) between the lines. During annealing, an alloy of aluminum and titanium forms, which subsequently volumetrically contracts, with the contraction being absorbed by the aluminum. Because the alloy is reacted prior to ILD deposition, however, the aluminum is not constrained by the ILD when it attempts to absorb the contraction of the alloy. Consequently, the likelihood of undesirable void formation in the interconnect lines is reduced. The likelihood of undesirable void formation is still further reduced during the subsequent ILD gapfill deposition process by using relatively low bias power to reduce vapor deposition temperature, and by using relatively low source gas deposition flow rates to reduce flow-induced compressive stress on the interconnect lines during ILD formation.
摘要翻译：用于制造0.25微米半导体芯片的方法包括在线之间沉积层间电介质（ILD）之前退火金属互连线。在退火期间，形成铝和钛的合金，其随后容积收缩，收缩被铝吸收。因为合金在ILD沉积之前反应，所以当铝试图吸收合金的收缩时，铝不受ILD的约束。因此，互连线中不希望的空隙形成的可能性降低。在随后的ILD间隙填充沉积过程中，通过使用相对低的偏置功率来降低气相沉积温度，并且通过使用相对较低的源气体沉积流速来减少互连线上的流动引起的压缩应力，仍然进一步降低了不希望的空隙形成的可能性在ILD形成期间。

9. 发明授权

US08202810B2 Low-H plasma treatment with N2 anneal for electronic memory devices 有权
标题翻译：用于电子存储器件的N 2退火的低-H等离子体处理
公开(公告)号：US08202810B2
公开(公告)日：2012-06-19
申请号：US11971331
申请日：2008-01-09
申请人： Alexander H. Nickel , Allen L. Evans , Minh Quoc Tran , Lu You , Minh Van Ngo , Pei-Yuan Gao , William S. Brennan , Erik Wilson , Sung Jin Kim , Hieu Trung Pham
发明人： Alexander H. Nickel , Allen L. Evans , Minh Quoc Tran , Lu You , Minh Van Ngo , Pei-Yuan Gao , William S. Brennan , Erik Wilson , Sung Jin Kim , Hieu Trung Pham
IPC分类号： H01L21/31
CPC分类号： H01L21/76877 , H01L21/76814 , H01L21/76828 , H01L21/76834 , H01L21/76883 , Y10S438/902
摘要： A method for forming a single damascene and/or dual damascene, contact and interconnect structure, comprising: performing front end processing, depositing copper including a copper barrier, annealing the copper in at least 90% N2 with less than 10% H2, performing planarization, performing in-situ low-H NH3 plasma treatment and low Si—H SiN etch stop layer deposition, and performing remaining back end processing.
摘要翻译：一种用于形成单个镶嵌和/或双镶嵌，接触和互连结构的方法，包括：执行前端处理，沉积包含铜屏障的铜，在至少90％的N 2中以小于10％的H 2退火铜，进行平面化，进行原位低H NH 3等离子体处理和低Si-H SiN蚀刻停止层沉积，并执行剩余的后端处理。

10. 发明申请

US20120038051A1 BURIED SILICIDE LOCAL INTERCONNECT WITH SIDEWALL SPACERS AND METHOD FOR MAKING THE SAME 有权
标题翻译：带硅胶的局部连接器和其制造方法
公开(公告)号：US20120038051A1
公开(公告)日：2012-02-16
申请号：US13281491
申请日：2011-10-26
申请人： Arvind Halliyal , Zoran Krivokapic , Matthew S. Buynoski , Nicholas H. Tripsas , Minh Van Ngo , Mark T. Ramsbey , Jeffery A. Shields , Jusuke Ogura
发明人： Arvind Halliyal , Zoran Krivokapic , Matthew S. Buynoski , Nicholas H. Tripsas , Minh Van Ngo , Mark T. Ramsbey , Jeffery A. Shields , Jusuke Ogura
IPC分类号： H01L23/48 , H01L21/768
CPC分类号： H01L21/28518 , H01L21/743 , H01L21/76895
摘要： A buried local interconnect and method of forming the same counterdopes a region of a doped substrate to form a counterdoped isolation region. A hardmask is formed and patterned on the doped substrate, with a recess being etched through the patterned hardmask into the counterdoped region. Dielectric spacers are formed on the sidewalls of the recess, with a portion of the bottom of the recess being exposed. A metal is then deposited in the recess and reacted to form silicide at the bottom of the recess. The recess is filled with fill material, which is polished. The hardmask is then removed to form a silicide buried local interconnect.
摘要翻译：掩埋的局部互连和形成相同对策的掺杂衬底的区域以形成反向隔离区的方法。硬掩模在掺杂的衬底上形成和图案化，其中凹陷通过图案化的硬掩模被蚀刻到反向掺杂的区域中。在凹槽的侧壁上形成有电介质隔离件，凹部底部的一部分露出。然后将金属沉积在凹部中并在凹部的底部反应形成硅化物。凹槽里填充有抛光的填充材料。然后去除硬掩模以形成硅化物掩埋的局部互连。

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