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1. 发明授权

US07812591B1 High-speed signal detect for serial interface 有权
标题翻译：串行接口高速信号检测
公开(公告)号：US07812591B1
公开(公告)日：2010-10-12
申请号：US12029659
申请日：2008-02-12
申请人： Mingde Pan , Juei-Chu Tu , Weiqi Ding
发明人： Mingde Pan , Juei-Chu Tu , Weiqi Ding
IPC分类号： G01R19/00
CPC分类号： G01R19/16566
摘要： More accurate signal detection circuitry in serial interfaces, particularly on a programmable integrated circuit device, such as a PLD, includes a high-speed, high-resolution, high-bandwidth comparator, along with digital filtering, to reduce the effect of process, temperature or supply variations. The comparator is used to compare a direct input signal with a programmable reference voltage, and, in a preferred embodiment, can detect the signal level within 8 mV accuracy. The output of the comparator may then be digitally filtered. Preferably, both a high-pass digital filter and a low-pass analog filter may be used to eliminate glitches and low-frequency noise. Preferably, the digital filters are programmable to adjust the sensitivity to noise. The filtered output is then latched and output to indicate receipt or loss of signal. This signal detect circuitry can operate reliably at data rates as high as 7 Gbps.
摘要翻译：串行接口中更准确的信号检测电路，特别是可编程集成电路器件（如PLD），包括高速，高分辨率，高带宽比较器以及数字滤波，以减少工艺，温度的影响或供应变化。比较器用于将直接输入信号与可编程参考电压进行比较，并且在优选实施例中，可以在8mV精度内检测信号电平。然后可以对比较器的输出进行数字滤波。优选地，可以使用高通数字滤波器和低通模拟滤波器来消除毛刺和低频噪声。优选地，数字滤波器可编程以调节对噪声的灵敏度。然后滤波后的输出被锁存并输出以指示信号的接收或丢失。该信号检测电路可以以高达7Gbps的数据速率可靠地工作。

2. 发明授权

US08030964B1 Techniques for level shifting signals 有权
标题翻译：电平转换信号的技术
公开(公告)号：US08030964B1
公开(公告)日：2011-10-04
申请号：US12121028
申请日：2008-05-15
申请人： Shou-Po Shih , Weiqi Ding , Juei-Chu Tu
发明人： Shou-Po Shih , Weiqi Ding , Juei-Chu Tu
IPC分类号： H03K19/0175
CPC分类号： H03K19/018521
摘要： A level shifter circuit includes an input circuit, an inverter, a pull-up circuit, and a pull-down circuit. The input circuit generates a pull-up signal in response to an input signal using charge from a supply voltage. The inverter inverts the input signal to generate a pull-down signal. The inverter comprises complementary transistors that receive charge from the supply voltage. The pull-up circuit pulls a level shifted output signal of the level shifter circuit to the supply voltage in response to the pull-up signal. The pull-down circuit pulls the level shifted output signal to a low voltage in response to the pull-down signal.
摘要翻译：电平移位电路包括输入电路，反相器，上拉电路和下拉电路。输入电路响应于使用来自电源电压的电荷的输入信号产生上拉信号。反相器反相输入信号产生下拉信号。反相器包括从电源电压接收电荷的互补晶体管。上拉电路响应于上拉信号将电平移位器电路的电平移位输出信号拉到电源电压。下拉电路响应于下拉信号将电平移位的输出信号拉低至低电压。

3. 发明授权

US08705602B1 Equalizer circuitry with selectable tap positions and coefficients 有权
标题翻译：均衡器电路，具有可选择的抽头位置和系数
公开(公告)号：US08705602B1
公开(公告)日：2014-04-22
申请号：US12580587
申请日：2009-10-16
申请人： Weiqi Ding , Mengchi Liu , Mingde Pan , Thungoc M. Tran , Sergey Shumarayev
发明人： Weiqi Ding , Mengchi Liu , Mingde Pan , Thungoc M. Tran , Sergey Shumarayev
IPC分类号： H03H7/30 , H03H7/40
CPC分类号： H04L25/03038 , H04L25/03343
摘要： Transmitter equalizer circuitry, e.g., for a serial, digital, data signal, includes tapped delay line circuitry for outputting a plurality of differently delayed versions of the signal propagating through the delay line circuitry. The equalizer circuitry also includes a plurality of electrical current digital-to-analog converters (“DACs”). The equalizer circuitry still further includes controllable (e.g., programmable) routing circuitry for selectably routing the delayed versions of the signal to the various DACs. The current strengths employed by the various DACs are also preferably controllable (e.g., programmable).
摘要翻译：例如，用于串行数字数据信号的发射机均衡器电路包括用于输出通过延迟线电路传播的信号的多个不同延迟版本的抽头延迟线电路。均衡器电路还包括多个电流数模转换器（“DAC”）。均衡器电路还包括可控（例如，可编程）路由电路，用于可选地将信号的延迟版本路由到各种DAC。各种DAC所使用的电流强度也优选是可控的（例如，可编程的）。

4. 发明申请

US20120274359A1 HIGH-SPEED DIFFERENTIAL COMPARATOR CIRCUITRY WITH ACCURATELY ADJUSTABLE THRESHOLD 有权
标题翻译：具有精确可调节阈值的高速差分比较器电路
公开(公告)号：US20120274359A1
公开(公告)日：2012-11-01
申请号：US13540410
申请日：2012-07-02
申请人： Weiqi Ding , Mingde Pan
发明人： Weiqi Ding , Mingde Pan
IPC分类号： H03K5/22
CPC分类号： H03K3/356139 , H03K5/08
摘要： A high-speed differential comparator circuit is provided with an accurately adjustable threshold voltage. Differential reference voltage signals are provided to control the threshold voltage of the comparator. The common mode voltage of the reference signals preferably tracks the common mode voltage of the differential high-speed serial data signal being processed by the comparator circuit.
摘要翻译：高速差分比较器电路具有精确可调的阈值电压。提供差分参考电压信号来控制比较器的阈值电压。参考信号的共模电压优选地跟踪由比较器电路正在处理的差分高速串行数据信号的共模电压。

5. 发明授权

US08750406B2 Multi-level amplitude signaling receiver 有权
标题翻译：多电平振幅信号接收机
公开(公告)号：US08750406B2
公开(公告)日：2014-06-10
申请号：US13363098
申请日：2012-01-31
申请人： Mingde Pan , Weiqi Ding , Sergey Shumarayev , Peng Li , Masashi Shimanouchi
发明人： Mingde Pan , Weiqi Ding , Sergey Shumarayev , Peng Li , Masashi Shimanouchi
IPC分类号： H04L25/34 , H04L25/49
CPC分类号： H04L25/4917 , H03D1/00 , H04L25/066 , H04L27/06
摘要： One embodiment relates to a receiver circuit for multi-level amplitude signaling which includes at least three amplitude levels for each symbol period. The receiver circuit includes a peak detector, a reference voltage generator, and a comparator circuit. The peak detector is arranged to detect a peak voltage of the multi-level amplitude signal, and the reference voltage generator uses the peak voltage to generate multiple reference voltages. The comparator circuit uses the multiple reference voltages to detect an amplitude level of the multi-level amplitude signal. Other embodiments and features are also disclosed.
摘要翻译：一个实施例涉及用于多电平振幅信令的接收机电路，其包括用于每个符号周期的至少三个幅度电平。接收器电路包括峰值检测器，参考电压发生器和比较器电路。峰值检测器被设置为检测多电平幅度信号的峰值电压，并且参考电压发生器使用峰值电压来产生多个参考电压。比较器电路使用多个参考电压来检测多电平幅度信号的幅度电平。还公开了其它实施例和特征。

6. 发明授权

US08610466B2 High-speed differential comparator circuitry with accurately adjustable threshold 有权
标题翻译：具有精确可调阈值的高速差分比较电路
公开(公告)号：US08610466B2
公开(公告)日：2013-12-17
申请号：US13540410
申请日：2012-07-02
申请人： Weiqi Ding , Mingde Pan
发明人： Weiqi Ding , Mingde Pan
IPC分类号： H03K5/22
CPC分类号： H03K3/356139 , H03K5/08
摘要： A high-speed differential comparator circuit is provided with an accurately adjustable threshold voltage. Differential reference voltage signals are provided to control the threshold voltage of the comparator. The common mode voltage of the reference signals preferably tracks the common mode voltage of the differential high-speed serial data signal being processed by the comparator circuit.
摘要翻译：高速差分比较器电路具有精确可调的阈值电压。提供差分参考电压信号来控制比较器的阈值电压。参考信号的共模电压优选地跟踪由比较器电路正在处理的差分高速串行数据信号的共模电压。

7. 发明授权

US08451883B1 On-chip full eye viewer architecture 有权
标题翻译：片上全景查看器架构
公开(公告)号：US08451883B1
公开(公告)日：2013-05-28
申请号：US12630674
申请日：2009-12-03
申请人： Weiqi Ding , Mingde Pan , Sergey Shumarayev , Peng Li
发明人： Weiqi Ding , Mingde Pan , Sergey Shumarayev , Peng Li
IPC分类号： H04B3/46
CPC分类号： G01R31/3171 , H04L1/0061 , H04L1/203 , H04L1/205 , H04L1/248 , H04L7/033 , H04L7/0334 , H04L7/048
摘要： Systems, methods, and devices for determining an eye diagram of a serial input signal to an integrated circuit without an oscilloscope are provided. For example, one embodiment of an integrated circuit device may be capable of determining an eye diagram associated with an equalized serial input signal. The device may include an equalizer and eye viewer circuitry. The equalizer may receive and perform equalization on a serial input signal to produce the equalized serial input signal, and the eye viewer circuitry may determine horizontal and vertical boundaries of the eye diagram associated with the equalized serial input signal.
摘要翻译：提供了用于确定没有示波器的集成电路的串行输入信号的眼图的系统，方法和装置。例如，集成电路设备的一个实施例可能能够确定与均衡的串行输入信号相关联的眼图。该装置可以包括均衡器和眼睛观察器电路。均衡器可以在串行输入信号上接收和执行均衡以产生均衡的串行输入信号，并且眼睛观察器电路可以确定与均衡的串行输入信号相关联的眼图的水平和垂直边界。

8. 发明授权

US08433958B2 Bit error rate checker receiving serial data signal from an eye viewer 有权
标题翻译：位错误率检测器从眼睛观察器接收串行数据信号
公开(公告)号：US08433958B2
公开(公告)日：2013-04-30
申请号：US12884923
申请日：2010-09-17
申请人： Weiqi Ding , Mingde Pan , Peng Li , Sergey Shumarayev , Masashi Shimanouchi
发明人： Weiqi Ding , Mingde Pan , Peng Li , Sergey Shumarayev , Masashi Shimanouchi
IPC分类号： G06F11/00
CPC分类号： H04L1/203 , G01R31/3171
摘要： An IC that includes an eye viewer and a BER checker coupled to the eye viewer, where the BER checker receives a serial data signal from the eye viewer, is provided. In one implementation, the BER checker receives the serial data signal from the eye viewer without the serial data signal passing through a deserializer. In one implementation, the BER checker compares the serial data signal against a reference data signal to determine the BER for the serial data signal. In one implementation, the IC includes an IC core coupled to the eye viewer and the BER checker, where the BER checker is outside the IC core. In one implementation, the BER checker is a dedicated BER checker. In one implementation, the BER checker includes an exclusive OR gate, a programmable delay circuit coupled to the exclusive OR gate, and an error counter coupled to the exclusive OR gate.
摘要翻译：提供了一种IC，其包括耦合到眼睛观察者的眼睛观察器和BER检查器，其中BER检查器从眼睛观察器接收串行数据信号。在一个实现中，BER检查器从眼睛观察器接收串行数据信号，而不经过串行数据信号通过解串器。在一个实现中，BER检验器将串行数据信号与参考数据信号进行比较，以确定串行数据信号的BER。在一个实现中，IC包括耦合到眼睛观察器和BER检查器的IC核心，其中BER检验器在IC核心之外。在一个实现中，BER检查器是专用的BER检查器。在一个实现中，BER检查器包括异或门，耦合到异或门的可编程延迟电路和耦合到异或门的错误计数器。

9. 发明授权

US08111784B1 On-chip data signal eye monitoring circuitry and methods 有权
标题翻译：片上数据信号眼监测电路及方法
公开(公告)号：US08111784B1
公开(公告)日：2012-02-07
申请号：US12082483
申请日：2008-04-11
申请人： Weiqi Ding , Mingde Pan , Wilson Wong , Sergey Shumarayev , Peng Li
发明人： Weiqi Ding , Mingde Pan , Wilson Wong , Sergey Shumarayev , Peng Li
IPC分类号： H04L25/06
CPC分类号： H04L25/063
摘要： Methods and apparatus for gathering information about the eye of a high-speed serial data signal include sampling each bit of a repeating, multi-bit data pattern at several eye slice locations. For any given eye slice location, each bit in the data pattern is compared in voltage to a base line reference signal voltage to establish a reference value for that bit. Then the reference signal voltage is gradually increased while the voltage comparisons are repeated until for some bit a result of the comparing is different than the reference value for that bit. This establishes an upper value for the eye at the eye slice location. The reference signal voltage is then gradually decreased to similarly find a lower value for that eye slice.
摘要翻译：用于收集关于高速串行数据信号的眼睛的信息的方法和装置包括在几个眼睛切片位置采样重复的多位数据模式的每一位。对于任何给定的眼片位置，将数据模式中的每个位在电压中与基线参考信号电压进行比较，以建立该位的参考值。然后在重复电压比较时，参考信号电压逐渐增加，直到比较结果的一些位与该位的参考值不同。这在眼部切片位置建立了眼睛的上限值。然后，参考信号电压逐渐减小，以类似地找到该眼片的较低值。

10. 发明授权

US08248107B2 High-speed differential comparator circuitry with accurately adjustable threshold 有权
标题翻译：具有精确可调阈值的高速差分比较电路
公开(公告)号：US08248107B2
公开(公告)日：2012-08-21
申请号：US12722319
申请日：2010-03-11
申请人： Weiqi Ding , Mingde Pan
发明人： Weiqi Ding , Mingde Pan
IPC分类号： H03F3/45
CPC分类号： H03K3/356139 , H03K5/08
摘要： A high-speed differential comparator circuit is provided with an accurately adjustable threshold voltage. Differential reference voltage signals are provided to control the threshold voltage of the comparator. The common mode voltage of the reference signals preferably tracks the common mode voltage of the differential high-speed serial data signal being processed by the comparator circuit.
摘要翻译：高速差分比较器电路具有精确可调的阈值电压。提供差分参考电压信号来控制比较器的阈值电压。参考信号的共模电压优选地跟踪由比较器电路正在处理的差分高速串行数据信号的共模电压。

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