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1. 发明授权

US08030964B1 Techniques for level shifting signals 有权
标题翻译：电平转换信号的技术
公开(公告)号：US08030964B1
公开(公告)日：2011-10-04
申请号：US12121028
申请日：2008-05-15
申请人： Shou-Po Shih , Weiqi Ding , Juei-Chu Tu
发明人： Shou-Po Shih , Weiqi Ding , Juei-Chu Tu
IPC分类号： H03K19/0175
CPC分类号： H03K19/018521
摘要： A level shifter circuit includes an input circuit, an inverter, a pull-up circuit, and a pull-down circuit. The input circuit generates a pull-up signal in response to an input signal using charge from a supply voltage. The inverter inverts the input signal to generate a pull-down signal. The inverter comprises complementary transistors that receive charge from the supply voltage. The pull-up circuit pulls a level shifted output signal of the level shifter circuit to the supply voltage in response to the pull-up signal. The pull-down circuit pulls the level shifted output signal to a low voltage in response to the pull-down signal.
摘要翻译：电平移位电路包括输入电路，反相器，上拉电路和下拉电路。输入电路响应于使用来自电源电压的电荷的输入信号产生上拉信号。反相器反相输入信号产生下拉信号。反相器包括从电源电压接收电荷的互补晶体管。上拉电路响应于上拉信号将电平移位器电路的电平移位输出信号拉到电源电压。下拉电路响应于下拉信号将电平移位的输出信号拉低至低电压。

2. 发明授权

US07999588B1 Duty cycle correction circuitry 有权
标题翻译：占空比校正电路
公开(公告)号：US07999588B1
公开(公告)日：2011-08-16
申请号：US12551434
申请日：2009-08-31
申请人： Mingde Pan , Shou-Po Shih , Mei Luo , Weiqi Ding
发明人： Mingde Pan , Shou-Po Shih , Mei Luo , Weiqi Ding
IPC分类号： H03K3/017
CPC分类号： H03K5/1565
摘要： Circuits and a method for tuning an integrated circuit (IC) are disclosed. The IC includes a storage circuit coupled to receive a data signal, a clock input signal and a reset signal. The storage circuit may be used to generate a clock signal. The reset signal is supplied by a reset circuit. The reset circuit may include one or more logic gates to generate the reset signal. The reset circuit receives a phase shifted version of the clock input signal and the reset signal is generated based on the phase shifted version of the clock input signal. In one embodiment, the reset signal is a series of pulses generated at specific intervals to shift the output of the storage circuit from logic high level to logic low level.
摘要翻译：公开了用于调谐集成电路（IC）的电路和方法。 IC包括耦合以接收数据信号，时钟输入信号和复位信号的存储电路。存储电路可用于产生时钟信号。复位信号由复位电路提供。复位电路可以包括一个或多个逻辑门以产生复位信号。复位电路接收时钟输入信号的相移版本，并且基于时钟输入信号的相移版本产生复位信号。在一个实施例中，复位信号是以特定间隔产生的一系列脉冲，以将存储电路的输出从逻辑高电平转换到逻辑低电平。

3. 发明授权

US08811555B2 Clock and data recovery circuitry with auto-speed negotiation and other possible features 有权
标题翻译：时钟和数据恢复电路，具有自动速度协商和其他可能的功能
公开(公告)号：US08811555B2
公开(公告)日：2014-08-19
申请号：US12700433
申请日：2010-02-04
申请人： Kazi Asaduzzaman , Tim Tri Hoang , Tin H. Lai , Shou-Po Shih , Sergey Shumarayev
发明人： Kazi Asaduzzaman , Tim Tri Hoang , Tin H. Lai , Shou-Po Shih , Sergey Shumarayev
IPC分类号： H04L7/00 , H03L7/081 , H04L7/033 , H03L7/08
CPC分类号： H03L7/08 , H03L7/0807 , H03L7/0814 , H03L7/087 , H03L7/0898 , H03L7/099 , H03L7/183 , H04L7/0337
摘要： An integrated circuit (“IC”) may include clock and data recovery (“CDR”) circuitry for recovering data information from an input serial data signal. The CDR circuitry may include a reference clock loop and a data loop. A retimed (recovered) data signal output by the CDR circuitry is monitored by other control circuitry on the IC for a communication change request contained in that signal. Responsive to such a request, the control circuitry can change an operating parameter of the CDR circuitry (e.g., a frequency division factor used in either of the above-mentioned loops).
摘要翻译：集成电路（“IC”）可以包括用于从输入串行数据信号恢复数据信息的时钟和数据恢复（“CDR”）电路。 CDR电路可以包括参考时钟环路和数据环路。由CDR电路输出的重新定时（恢复）数据信号由IC上的其它控制电路监视用于包含在该信号中的通信改变请求。响应于这种请求，控制电路可以改变CDR电路的操作参数（例如，在上述任何一个循环中使用的分频因子）。

4. 发明授权

US08671305B1 Techniques for adjusting periodic signals based on data detection 有权
标题翻译：基于数据检测调整周期信号的技术
公开(公告)号：US08671305B1
公开(公告)日：2014-03-11
申请号：US13175604
申请日：2011-07-01
申请人： Shou-Po Shih , Tim Tri Hoang , Kazi Asaduzzaman
发明人： Shou-Po Shih , Tim Tri Hoang , Kazi Asaduzzaman
IPC分类号： G06F1/04 , G06F1/12
CPC分类号： H04B10/6165 , H03L7/0807 , H03L7/087 , H03L7/099 , H03L7/14 , H04L7/0004 , H04L7/0083 , H04L7/033
摘要： A circuit includes a phase detector circuit, a phase frequency detector circuit, a data detection circuit, a multiplexer circuit, and a clock signal generation circuit. The phase detector circuit is operable to generate a first phase detection signal based on a data signal and a first periodic signal. The phase frequency detector circuit is operable to generate a second phase detection signal based on second and third periodic signals. The data detection circuit is operable to generate a data detection signal based on the first phase detection signal. A multiplexer circuit is operable to provide one of the first and the second phase detection signals as a selected signal based on the data detection signal. The periodic signal generation circuit is operable to cause adjustments to phases of the first and the second periodic signals based on the selected signal.
摘要翻译：电路包括相位检测器电路，相位频率检测器电路，数据检测电路，多路复用器电路和时钟信号发生电路。相位检测器电路可操作以基于数据信号和第一周期信号产生第一相位检测信号。相位频率检测器电路可操作以基于第二和第三周期信号产生第二相位检测信号。数据检测电路可操作以基于第一相位检测信号产生数据检测信号。多路复用器电路可操作以基于数据检测信号提供第一和第二相位检测信号中的一个作为选择的信号。周期信号产生电路可操作以基于所选择的信号来调整第一和第二周期信号的相位。

5. 发明申请

US20110188621A1 CLOCK AND DATA RECOVERY CIRCUITRY WITH AUTO-SPEED NEGOTIATION AND OTHER POSSIBLE FEATURES 有权
标题翻译：时钟和数据恢复电路与自动调速和其他可能的特性
公开(公告)号：US20110188621A1
公开(公告)日：2011-08-04
申请号：US12700433
申请日：2010-02-04
申请人： Kazi Asaduzzaman , Tim Tri Hoang , Tin H. Lai , Shou-Po Shih , Sergey Shumarayev
发明人： Kazi Asaduzzaman , Tim Tri Hoang , Tin H. Lai , Shou-Po Shih , Sergey Shumarayev
IPC分类号： H04L7/00
CPC分类号： H03L7/08 , H03L7/0807 , H03L7/0814 , H03L7/087 , H03L7/0898 , H03L7/099 , H03L7/183 , H04L7/0337
摘要： An integrated circuit (“IC”) may include clock and data recovery (“CDR”) circuitry for recovering data information from an input serial data signal. The CDR circuitry may include a reference clock loop and a data loop. A retimed (recovered) data signal output by the CDR circuitry is monitored by other control circuitry on the IC for a communication change request contained in that signal. Responsive to such a request, the control circuitry can change an operating parameter of the CDR circuitry (e.g., a frequency division factor used in either of the above-mentioned loops). This can help the IC support communication protocols that employ auto-speed negotiation.
摘要翻译：集成电路（“IC”）可以包括用于从输入串行数据信号恢复数据信息的时钟和数据恢复（“CDR”）电路。 CDR电路可以包括参考时钟环路和数据环路。由CDR电路输出的重新定时（恢复）数据信号由IC上的其它控制电路监视用于包含在该信号中的通信改变请求。响应于这种请求，控制电路可以改变CDR电路的操作参数（例如，在上述任何一个循环中使用的分频因子）。这可以帮助IC支持采用自动速度协商的通信协议。

6. 发明授权

US06535029B2 Fully differential continuous-time current-mode high speed CMOS comparator 有权
公开(公告)号：US06535029B2
公开(公告)日：2003-03-18
申请号：US09847837
申请日：2001-05-01
申请人： Shou-Po Shih , Chieh-Yuan Chao , Yuming Cao , Yu-Jen Wu
发明人： Shou-Po Shih , Chieh-Yuan Chao , Yuming Cao , Yu-Jen Wu
IPC分类号： H03K522
CPC分类号： H03K3/356139 , H03K5/2481 , H03K5/249
摘要： A fully differential continuous-time current-mode high-speed complimentary metal oxide semiconductor comparator is disclosed. The comparator includes an input and an output; a pre-amplifier clement coupled to each respective one of the plurality of inverters; an application switch operative to couple the pre-amplifier element to the input of a corresponding one of the plurality of inverters, the application switch having a first duty cycle; a current source operative to provide a bias current; and a bias switch operative to couple the bias current to each of the plurality of inverters, the bias switch having a duty cycle that is complementary to the duty cycle of the application switch, wherein the output of each of the plurality of inverters is pulled to about one-half the maximum output voltage level before a comparison between input signals is performed. By maintaining the comparator output at a substantially predetermined voltage level during non-operating periods, the switching characteristics of the comparator are enhanced.

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