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1. 发明授权

US07672803B1 Input of test conditions and output generation for built-in self test 有权
标题翻译：输入测试条件和输出产生内置自检
公开(公告)号：US07672803B1
公开(公告)日：2010-03-02
申请号：US11006034
申请日：2004-12-07
申请人： Mimi Lee , Darlene Hamilton , Ken Cheong Cheah
发明人： Mimi Lee , Darlene Hamilton , Ken Cheong Cheah
IPC分类号： G01R27/28
CPC分类号： G11C29/16 , G01R31/318511 , G11C16/04 , G11C29/12005 , G11C29/44
摘要： A system and method is discussed for providing programmable test conditions for a built-in self test circuit of a flash memory device. The present invention employs a flash memory having BIST circuit for testing the memory and a BIST interface circuit adapted to adjust the test conditions of the memory tests. The BIST interface circuit is operable to receive one or more global variables associated with the test conditions of a plurality of tests used on the flash memory and to output results of the memory tests based on the value of the variables. The global variables are used to adjust the test conditions and to trim one or more references used in various flash memory tests and operations. The system may further include a serial communications medium for communicating the global variables to the BIST interface and test results from the interface.
摘要翻译：讨论了一种用于为闪存器件的内置自测电路提供可编程测试条件的系统和方法。本发明采用具有用于测试存储器的BIST电路的闪速存储器和适于调整存储器测试的测试条件的BIST接口电路。 BIST接口电路可操作以接收与闪存上使用的多个测试的测试条件相关联的一个或多个全局变量，并且基于变量的值输出存储器测试的结果。全局变量用于调整测试条件并修剪用于各种闪存测试和操作的一个或多个引用。该系统还可以包括用于将全局变量传送到BIST接口的串行通信介质以及来自接口的测试结果。

2. 发明授权

US07284167B2 Automated tests for built-in self test 有权
标题翻译：自动测试内置自检
公开(公告)号：US07284167B2
公开(公告)日：2007-10-16
申请号：US11041608
申请日：2005-01-24
申请人： Mimi Lee , Darlene Hamilton , Ken Cheong Cheah , Kendra Nguyen , Xin Guo
发明人： Mimi Lee , Darlene Hamilton , Ken Cheong Cheah , Kendra Nguyen , Xin Guo
IPC分类号： G11C29/00 , G11C7/00
CPC分类号： G11C29/021 , G11C16/04 , G11C29/02 , G11C29/028 , G11C29/1201 , G11C29/16
摘要： A method is discussed for providing programmable test conditions for a built-in self test circuit of a flash memory device. The method comprises providing a BIST interface adapted to adjust a test condition used in a BIST circuit, providing the memory cells of the Flash memory device, and providing the BIST circuit adapted to test the flash memory. The method further comprises communicating with the BIST interface one or more global variables associated with the test condition, adjusting the test condition used by the BIST circuit based on the values represented by the global variables, performing one or more test operations on the flash memory in accordance with the adjusted test condition, and reporting the results of the memory test operations. The method of the present invention may further include a serial communications medium and the use of a serial test protocol for communicating the global variables to the BIST interface and test results from the interface. The global variables may also be provided by a memory device user.
摘要翻译：讨论了一种用于为闪存设备的内置自测电路提供可编程测试条件的方法。该方法包括提供BIST接口，其适于调整在BIST电路中使用的测试条件，提供闪存设备的存储单元，以及提供适于测试闪速存储器的BIST电路。该方法还包括与BIST接口通信与测试条件相关联的一个或多个全局变量，基于由全局变量表示的值来调整由BIST电路使用的测试条件，对闪速存储器执行一个或多个测试操作根据调整的测试条件，并记录测试操作的结果。本发明的方法还可以包括串行通信介质和使用串行测试协议来将全局变量传送到BIST接口并从接口测试结果。全局变量也可由存储器设备用户提供。

3. 发明授权

US07415646B1 Page—EXE erase algorithm for flash memory 有权
标题翻译：闪存的Page-EXE擦除算法
公开(公告)号：US07415646B1
公开(公告)日：2008-08-19
申请号：US10946812
申请日：2004-09-22
申请人： Mimi Lee , Darlene Hamilton , Ken Cheong Cheah
发明人： Mimi Lee , Darlene Hamilton , Ken Cheong Cheah
IPC分类号： G01R31/28
CPC分类号： G11C16/344 , G11C16/04 , G11C16/16 , G11C16/3445 , G11C29/50004 , G11C29/52 , G11C2216/18
摘要： Methods of performing a sector erase of flash memory devices incorporating built-in self test circuitry are provided. The present invention employs an interactive verification and sector erase algorithm to verify and repeatedly erase the sector until a portion of the groups of each page of the sector are erased or a first maximum number of erase pulses is achieved. The algorithm further includes a word verification and erase operation that sequentially verifies and erases each word of the sector until each word is erased or a second maximum number of erase pulses is achieved. The second maximum number of erase pulses may be based on a function of the first maximum number of erase pulses. The second maximum number of erase pulses may be input to the sector erase algorithm as a multi-bit code. The second maximum number of erase pulses and conversion of the multi-bit code may be based on a binary multiple of the first maximum number of erase pulses.
摘要翻译：提供了包含内置自测电路的闪存器件的扇区擦除方法。本发明使用交互验证和扇区擦除算法来验证并重复地擦除扇区，直到扇区的每一页的一部分组被擦除或实现了第一最大数目的擦除脉冲。该算法还包括一个字验证和擦除操作，其顺序地验证和擦除扇区的每个字，直到每个字被擦除或者实现第二个最大数量的擦除脉冲。第二最大擦除脉冲数可以基于第一最大数量的擦除脉冲的函数。擦除脉冲的第二个最大数量可以作为多位代码输入到扇区擦除算法。擦除脉冲的第二个最大数量和多位代码的转换可以基于第一最大数量的擦除脉冲的二进制数。

4. 发明授权

US06973003B1 Memory device and method 有权
标题翻译：内存设备和方法
公开(公告)号：US06973003B1
公开(公告)日：2005-12-06
申请号：US10677073
申请日：2003-10-01
申请人： Syahrizal Salleh , Edward V. Bautista, Jr. , Ken Cheong Cheah
发明人： Syahrizal Salleh , Edward V. Bautista, Jr. , Ken Cheong Cheah
IPC分类号： G11C7/00 , G11C11/406
CPC分类号： G11C11/40622 , G11C11/406
摘要： A memory device and a method for refreshing the memory device. The memory device includes a memory cell capable of storing two bits of data. One bit is referred to as the normal data bit and the other bit is referred to as the complementary data bit. Each memory cell has an associated dynamic reference cell. The normal data is refreshed by latching refresh data into a data latch and ORing the latched data with input data. The refresh data is written to the corresponding memory location. The data for the complementary data bit is refreshed by latching complementary data bit refresh data into the complementary data latches and writing to the memory cell. The normal and complementary data bits are refreshed before each read operation.
摘要翻译：一种用于刷新存储器件的存储器件和方法。存储器件包括能够存储两位数据的存储器单元。一位被称为正常数据位，另一位称为互补数据位。每个存储单元具有相关联的动态参考单元。正常数据通过将刷新数据锁存到数据锁存器中并将锁存数据与输入数据进行OR运算来刷新。刷新数据被写入相应的存储单元。通过将互补数据位刷新数据锁存到互补数据锁存器中并写入存储单元来刷新补充数据位的数据。正常和互补的数据位在每次读取操作之前刷新。

5. 发明授权

US07158442B1 Flexible latency in flash memory 有权
标题翻译：闪存中的灵活延迟
公开(公告)号：US07158442B1
公开(公告)日：2007-01-02
申请号：US11135231
申请日：2005-05-23
申请人： Jih Hong Beh , Ken Cheong Cheah
发明人： Jih Hong Beh , Ken Cheong Cheah
IPC分类号： G11C8/00
CPC分类号： G11C7/22 , G11C7/1051 , G11C7/1066 , G11C7/222 , G11C16/26
摘要： A method of reading data in and outputting data from a memory structure includes a buffer. In the present method, first read operation is undertaken to read a first set of data in the memory structure and provide data of the first set of data to the buffer, using an output clock. A first output operation is undertaken providing data read in the first read operation from the buffer, and a second read operation is undertaken to read a second set of data in the memory structure and provide data of the second set of data to the buffer, using the output clock. A second output operation is undertaken providing data read in the second read operation from the buffer. In the event that the completion of the first output operation would occur prior to the completion of the provision of the data of the second set of data to the buffer, a flexible time delay approach is undertaken so that, between the completion of the first output operation and the beginning of the second output operation, the minimum number of latencies are added as needed to insure that the provision of the data of the second set of data to the buffer is completed prior to the initiation of the second output operation.
摘要翻译：从存储器结构读取数据并从存储器结构输出数据的方法包括缓冲器。在本方法中，进行第一读取操作以读取存储器结构中的第一组数据，并使用输出时钟向缓冲器提供第一组数据的数据。进行第一输出操作，从缓冲器提供在第一读取操作中读取的数据，并进行第二读取操作以读取存储器结构中的第二组数据，并将第二组数据的数据提供给缓冲器，使用输出时钟。进行第二输出操作，从缓冲器提供在第二读取操作中读取的数据。在完成向缓冲器提供第二组数据的数据之前发生第一输出操作的完成的情况下，进行灵活的时间延迟方法，使得在完成第一输出之间操作和第二输出操作的开始，根据需要添加最小延迟数，以确保在第二输出操作开始之前向缓冲器提供第二组数据的数据。

6. 发明授权

US07010736B1 Address sequencer within BIST (Built-in-Self-Test) system 有权
标题翻译： BIST（内置自检）系统中的地址排序器
公开(公告)号：US07010736B1
公开(公告)日：2006-03-07
申请号：US10200518
申请日：2002-07-22
申请人： Boon Tang Teh , Edward V. Bautista, Jr. , Ken Cheong Cheah , Colin Bill , Joseph Kucera , Weng Fook Lee , Darlene G. Hamilton
发明人： Boon Tang Teh , Edward V. Bautista, Jr. , Ken Cheong Cheah , Colin Bill , Joseph Kucera , Weng Fook Lee , Darlene G. Hamilton
IPC分类号： G01R31/28
CPC分类号： G11C29/36 , G11C15/00 , G11C16/04 , G11C29/12005 , G11C29/16 , G11C29/18 , G11C29/44 , G11C29/4401 , G11C29/50 , G11C29/52 , G11C29/76 , G11C2029/1208 , G11C2029/3602
摘要： An address sequencer is fabricated on a semiconductor substrate having flash memory cells fabricated thereon for sequencing through the flash memory cells during BIST (built-in-self-test) of the flash memory cells. The address sequencer includes an address sequencer control logic and address sequencer buffers fabricated on the semiconductor substrate. The address sequencer buffers generate a plurality of bits indicating an address of the flash memory cells. The address sequencer control logic controls the buffers to sequence through a respective sequence of bit patterns for each of a plurality of BIST modes.
摘要翻译：在其上制造闪存单元的半导体衬底上制造地址序列器，用于在快闪存储器单元的BIST（内置自测试）期间对闪存单元进行排序。地址排序器包括在半导体衬底上制造的地址定序器控制逻辑和地址序列器缓冲器。地址顺序器缓冲器产生指示闪存单元的地址的多个位。地址定序器控制逻辑控制缓冲器以通过针对多个BIST模式中的每一个的相应的位模式序列进行排序。

7. 发明授权

US06980473B1 Memory device and method 有权
标题翻译：内存设备和方法
公开(公告)号：US06980473B1
公开(公告)日：2005-12-27
申请号：US10677031
申请日：2003-10-01
申请人： Edward V. Bautista, Jr. , Ken Cheong Cheah , Chi-Mun Ho
发明人： Edward V. Bautista, Jr. , Ken Cheong Cheah , Chi-Mun Ho
IPC分类号： G11C16/04 , G11C16/12 , G11C16/30 , G11C16/34
CPC分类号： G11C16/3459 , G11C16/12 , G11C16/30 , G11C16/3454 , G11C29/021 , G11C29/028
摘要： A memory device and a method for compensating for a load current in the memory device. The memory device includes a plurality of I/O buffers where each I/O buffer includes an I/O write-buffer driver circuit. The I/O write-buffer driver circuit is coupled to a load current compensation circuit. Although each I/O buffer includes an I/O write-buffer circuit, a single load current compensation circuit may be coupled to several I/O write-buffer driver circuits. The load current compensation circuit generates a load compensation current for each I/O buffer circuit that is not being programmed. The load compensation current increases the load current so that a drain-side programming voltage (VPROG) drives a substantially constant load current, wherein the drain-side programming voltage is substantially independent of the number of bits being programmed.
摘要翻译：一种用于补偿存储器件中的负载电流的存储器件和方法。存储器件包括多个I / O缓冲器，其中每个I / O缓冲器包括I / O写缓冲器驱动电路。 I / O写缓冲器驱动电路耦合到负载电流补偿电路。尽管每个I / O缓冲器都包含一个I / O写缓冲电路，但单个负载电流补偿电路可以耦合到多个I / O写缓冲器驱动电路。负载电流补偿电路为未编程的每个I / O缓冲电路产生负载补偿电流。负载补偿电流增加负载电流，使得漏极侧编程电压（VPROG）驱动基本恒定的负载电流，其中漏极侧编程电压基本上与被编程的位数无关。

8. 发明授权

US07028240B1 Diagnostic mode for testing functionality of BIST (built-in-self-test) back-end state machine 有权
标题翻译：用于测试BIST（内置自检）后端状态机的功能的诊断模式
公开(公告)号：US07028240B1
公开(公告)日：2006-04-11
申请号：US10200526
申请日：2002-07-22
申请人： Edward V. Bautista, Jr. , Ken Cheong Cheah , Colin Bill
发明人： Edward V. Bautista, Jr. , Ken Cheong Cheah , Colin Bill
IPC分类号： G01R3/28
CPC分类号： G11C29/02 , G11C16/04 , G11C29/16
摘要： In a method and system for diagnosing a back-end state machine used for testing flash memory cells fabricated on a semiconductor substrate, a signal selector and a diagnostic matching logic are fabricated on the semiconductor substrate. The diagnostic matching logic sets a generated match output to a pass or fail state depending on control variables from the back-end state machine. The signal selector selects the generated match output to be used in a verify step of a BIST (built-in-self-test) mode, if a diagnostic mode is invoked. The back-end state machine performs a plurality of BIST modes with the generated match output, for testing the functionality of the back-end state machine.
摘要翻译：在用于诊断用于测试在半导体衬底上制造的闪存单元的后端状态机的方法和系统中，在半导体衬底上制造信号选择器和诊断匹配逻辑。诊断匹配逻辑根据后端状态机的控制变量将生成的匹配输出设置为通过或失败状态。如果调用诊断模式，则信号选择器选择要在BIST（内置自检）模式的验证步骤中使用的生成的匹配输出。后端状态机利用生成的匹配输出执行多个BIST模式，用于测试后端状态机的功能。

9. 发明授权

US06970368B1 CAM (content addressable memory) cells as part of core array in flash memory device 有权
标题翻译： CAM（内容可寻址存储器）单元作为闪存设备中的核心阵列的一部分
公开(公告)号：US06970368B1
公开(公告)日：2005-11-29
申请号：US10650049
申请日：2003-08-26
申请人： Edward V. Bautista, Jr. , Ken Cheong Cheah
发明人： Edward V. Bautista, Jr. , Ken Cheong Cheah
IPC分类号： G11C15/00 , G11C15/04
CPC分类号： G11C15/046
摘要： In a method and system for providing a CAM (content addressable memory) cell of a flash memory device, a respective core flash memory cell to be used as the CAM cell is fabricated as part of a core array of the flash memory device. In addition, the respective core flash memory cell is accessed from the core array as the CAM cell for a CAM function within the flash memory device. Components used for supporting operation of the core array are also used for accessing the core flash memory cells of the additional sector for such CAM functionality. Thus, CAM functionality is provided with a minimized number of components and with minimized area of the die of the flash memory device. In addition, because the CAM cells are implemented as core flash memory cells of the core array, the CAM cells may reliably undergo more numerous programming and erasing cycles.
摘要翻译：在用于提供闪速存储器件的CAM（内容可寻址存储器）单元的方法和系统中，将要用作CAM单元的相应核心闪速存储器单元制造为闪速存储器件的核心阵列的一部分。此外，各个核心闪存单元从核心阵列作为用于CAM存储器件内的CAM功能的CAM单元访问。用于支持核心阵列操作的组件也用于访问用于这种CAM功能的附加扇区的核心闪存单元。因此，CAM功能被提供有最少数量的部件并且具有闪存器件的管芯的最小面积。另外，由于CAM单元被实现为核心阵列的核心闪存单元，因此CAM单元可以可靠地进行更多的编程和擦除周期。

10. 发明授权

US06665214B1 On-chip erase pulse counter for efficient erase verify BIST (built-in-self-test) mode 有权
标题翻译：片内擦除脉冲计数器，用于高效擦除验证BIST（内置自检）模式
公开(公告)号：US06665214B1
公开(公告)日：2003-12-16
申请号：US10200330
申请日：2002-07-22
申请人： Ken Cheong Cheah , Edward V. Bautista, Jr. , Weng Fook Lee , Boon Tang Teh
发明人： Ken Cheong Cheah , Edward V. Bautista, Jr. , Weng Fook Lee , Boon Tang Teh
IPC分类号： G11C1606
CPC分类号： G11C29/50004 , G11C16/04 , G11C29/02 , G11C29/44 , G11C29/48 , G11C29/50 , G11C2029/5002
摘要： In a method and system for monitoring erase pulses applied on a sector of flash memory cells fabricated on a semiconductor substrate, a pulse counter and a pulse counter controller are fabricated on the semiconductor substrate. The pulse counter controller inputs a maximum number and outputs an indication of a sector fail if the flash memory cells of the sector do not pass erase verification with less than the maximum number of erase pulses applied on the sector during an erase verify BIST (Built-in-Self-Test) mode. In one example, the maximum number is a percentage of a diagonal total number of erase pulses needed to be applied on the sector until each flash memory cell at a diagonal location of the sector passes erase verification.
摘要翻译：在用于监视施加在制造在半导体衬底上的快闪存储器单元的扇区上的擦除脉冲的方法和系统中，在半导体衬底上制造脉冲计数器和脉冲计数器控制器。脉冲计数器控制器输入最大数量，并且如果在擦除验证期间扇区的闪速存储单元不通过小于刷新扇区上最大擦除脉冲数的擦除验证，则输出扇区失败的指示BIST（Built- 自检）模式。在一个示例中，最大数量是需要施加在扇区上的擦除脉冲的对角线总数的百分比，直到扇区的对角线位置处的每个闪存单元通过擦除验证。

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