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1. 发明授权

US07010736B1 Address sequencer within BIST (Built-in-Self-Test) system 有权
标题翻译： BIST（内置自检）系统中的地址排序器
公开(公告)号：US07010736B1
公开(公告)日：2006-03-07
申请号：US10200518
申请日：2002-07-22
申请人： Boon Tang Teh , Edward V. Bautista, Jr. , Ken Cheong Cheah , Colin Bill , Joseph Kucera , Weng Fook Lee , Darlene G. Hamilton
发明人： Boon Tang Teh , Edward V. Bautista, Jr. , Ken Cheong Cheah , Colin Bill , Joseph Kucera , Weng Fook Lee , Darlene G. Hamilton
IPC分类号： G01R31/28
CPC分类号： G11C29/36 , G11C15/00 , G11C16/04 , G11C29/12005 , G11C29/16 , G11C29/18 , G11C29/44 , G11C29/4401 , G11C29/50 , G11C29/52 , G11C29/76 , G11C2029/1208 , G11C2029/3602
摘要： An address sequencer is fabricated on a semiconductor substrate having flash memory cells fabricated thereon for sequencing through the flash memory cells during BIST (built-in-self-test) of the flash memory cells. The address sequencer includes an address sequencer control logic and address sequencer buffers fabricated on the semiconductor substrate. The address sequencer buffers generate a plurality of bits indicating an address of the flash memory cells. The address sequencer control logic controls the buffers to sequence through a respective sequence of bit patterns for each of a plurality of BIST modes.
摘要翻译：在其上制造闪存单元的半导体衬底上制造地址序列器，用于在快闪存储器单元的BIST（内置自测试）期间对闪存单元进行排序。地址排序器包括在半导体衬底上制造的地址定序器控制逻辑和地址序列器缓冲器。地址顺序器缓冲器产生指示闪存单元的地址的多个位。地址定序器控制逻辑控制缓冲器以通过针对多个BIST模式中的每一个的相应的位模式序列进行排序。

2. 发明授权

US06665214B1 On-chip erase pulse counter for efficient erase verify BIST (built-in-self-test) mode 有权
标题翻译：片内擦除脉冲计数器，用于高效擦除验证BIST（内置自检）模式
公开(公告)号：US06665214B1
公开(公告)日：2003-12-16
申请号：US10200330
申请日：2002-07-22
申请人： Ken Cheong Cheah , Edward V. Bautista, Jr. , Weng Fook Lee , Boon Tang Teh
发明人： Ken Cheong Cheah , Edward V. Bautista, Jr. , Weng Fook Lee , Boon Tang Teh
IPC分类号： G11C1606
CPC分类号： G11C29/50004 , G11C16/04 , G11C29/02 , G11C29/44 , G11C29/48 , G11C29/50 , G11C2029/5002
摘要： In a method and system for monitoring erase pulses applied on a sector of flash memory cells fabricated on a semiconductor substrate, a pulse counter and a pulse counter controller are fabricated on the semiconductor substrate. The pulse counter controller inputs a maximum number and outputs an indication of a sector fail if the flash memory cells of the sector do not pass erase verification with less than the maximum number of erase pulses applied on the sector during an erase verify BIST (Built-in-Self-Test) mode. In one example, the maximum number is a percentage of a diagonal total number of erase pulses needed to be applied on the sector until each flash memory cell at a diagonal location of the sector passes erase verification.
摘要翻译：在用于监视施加在制造在半导体衬底上的快闪存储器单元的扇区上的擦除脉冲的方法和系统中，在半导体衬底上制造脉冲计数器和脉冲计数器控制器。脉冲计数器控制器输入最大数量，并且如果在擦除验证期间扇区的闪速存储单元不通过小于刷新扇区上最大擦除脉冲数的擦除验证，则输出扇区失败的指示BIST（Built- 自检）模式。在一个示例中，最大数量是需要施加在扇区上的擦除脉冲的对角线总数的百分比，直到扇区的对角线位置处的每个闪存单元通过擦除验证。

3. 发明授权

US06507527B1 Memory line discharge before sensing 有权
标题翻译：感应前存储线放电
公开(公告)号：US06507527B1
公开(公告)日：2003-01-14
申请号：US09698614
申请日：2000-10-27
申请人： Lee Cleveland , Jin-Lien Lin , Takao Akaogi , Ali Al-Shamma , Boon Tang Teh , Kendra Nguyen , Yong Kim
发明人： Lee Cleveland , Jin-Lien Lin , Takao Akaogi , Ali Al-Shamma , Boon Tang Teh , Kendra Nguyen , Yong Kim
IPC分类号： G11C700
CPC分类号： G11C7/06 , G11C7/12
摘要： A method of charging a data line to a desired voltage level prior to the data line being sensed in a low power memory device by discharging the data line from a voltage level above the desired voltage level to approximately the desired voltage level. By using N-type transistors to discharge the data line to the desired voltage level, the voltage level can be reached faster with cheaper components.
摘要翻译：一种通过将数据线从高于期望电压电平的电压电平放电到大约期望的电压电平，在数据线在低功率存储器件中被感测之前将数据线充电到期望的电压电平的方法。通过使用N型晶体管将数据线放电至期望的电压电平，可以用更便宜的组件更快地达到电压电平。

4. 发明授权

US06347052B1 Word line decoding architecture in a flash memory 有权
标题翻译：字线解码架构在闪存中
公开(公告)号：US06347052B1
公开(公告)日：2002-02-12
申请号：US09690554
申请日：2000-10-17
申请人： Takao Akaogi , Ali K. Al-Shamma , Lee Cleveland , Yong Kim , Jin-Lien Lin , Kendra Nguyen , Boon Tang Teh
发明人： Takao Akaogi , Ali K. Al-Shamma , Lee Cleveland , Yong Kim , Jin-Lien Lin , Kendra Nguyen , Boon Tang Teh
IPC分类号： G11C1606
CPC分类号： G11C16/08 , G11C8/10
摘要： A flash memory having word line decoding and selection architecture is described. The flash memory include first and second sectors of memory cells, first and second local driver circuits, first, second and third decoding circuits, and a driving circuit. The first sectors of first memory cells include a first plurality of word lines coupled to the first memory cells, each being capable of being a first selected word line. The second sectors of second memory cells include a similar Local driver circuits are independently coupled to each word line of the first and second pluralities of word lines of the first sectors. Each decoding circuits comprise a first and a second side of decoding circuitry. The first side of decoding circuitry activates a first selected plurality of local driver circuits and the second side of decoding circuitry activates a second selected plurality of local driver circuits. The second decoding circuits are coupled to the first local driver circuits and supply a first boosted voltage to the first selected word line coupled to a first local driver circuit. The third decoding circuits are coupled to the second local driver circuits and supply a second boosted voltage to the second selected word line. The driving circuit supplies a series of boosted voltages to the first decoding circuits, the second decoding circuits, the third decoding circuits, the first local driver circuits, and the second local driver circuits.
摘要翻译：描述了具有字线解码和选择架构的闪速存储器。闪速存储器包括存储单元的第一和第二扇区，第一和第二本地驱动电路，第一，第二和第三解码电路以及驱动电路。第一存储器单元的第一扇区包括耦合到第一存储器单元的第一多个字线，每个字线能够是第一选定的字线。第二存储器单元的第二扇区包括类似的局部驱动器电路独立地耦合到第一扇区的第一和第二多个字线的每个字线。每个解码电路包括解码电路的第一和第二侧。解码电路的第一侧激活第一选定的多个本地驱动器电路，并且解码电路的第二侧激活第二选定的多个局部驱动器电路。第二解码电路耦合到第一本地驱动电路，并将第一升压电压提供给耦合到第一本地驱动电路的第一选定字线。第三解码电路耦合到第二本地驱动电路，并将第二升压电压提供给第二选定字线。驱动电路向第一解码电路，第二解码电路，第三解码电路，第一本地驱动电路和第二本地驱动电路提供一系列升压电压。

5. 发明授权

US06243316B1 Voltage boost reset circuit for a flash memory 有权
标题翻译：闪存的升压复位电路
公开(公告)号：US06243316B1
公开(公告)日：2001-06-05
申请号：US09501159
申请日：2000-02-09
申请人： Takao Akaogi , Ali K. Al-Shamma , Lee Edward Cleveland , Yong Kim , Jin-Lien Lin , Boon Tang Teh , Kendra Nguyen
发明人： Takao Akaogi , Ali K. Al-Shamma , Lee Edward Cleveland , Yong Kim , Jin-Lien Lin , Boon Tang Teh , Kendra Nguyen
IPC分类号： G11C700
CPC分类号： G11C8/08 , G11C5/145 , G11C16/08
摘要： A voltage boost circuit (111) for a memory (100) includes a boosting circuit (110) which is coupled to a boosted node (120) to boost a word line voltage for accessing a core cell of the memory. The voltage boost circuit further includes a reset circuit (112) coupled to the boosted node and including a switchable zero-threshold transistor (202) for resetting the boosted node to a reset voltage (VCC).
摘要翻译：用于存储器（100）的升压电路（111）包括升压电路（110），其被耦合到升压节点（120）以升高用于访问存储器的核心单元的字线电压。升压电路还包括耦合到升压节点的复位电路（112），并且包括用于将升压节点复位到复位电压（VCC）的可切换零阈值晶体管（202）。

6. 发明授权

US06351420B1 Voltage boost level clamping circuit for a flash memory 有权
标题翻译：用于闪存的电压升压电平钳位电路
公开(公告)号：US06351420B1
公开(公告)日：2002-02-26
申请号：US09595519
申请日：2000-06-16
申请人： Takao Akaogi , Ali K. Al-Shamma , Lee Edward Cleveland , Yong Kim , Jin-Lien Lin , Boon Tang Teh , Kendra Nguyen
发明人： Takao Akaogi , Ali K. Al-Shamma , Lee Edward Cleveland , Yong Kim , Jin-Lien Lin , Boon Tang Teh , Kendra Nguyen
IPC分类号： G11C700
CPC分类号： G11C8/08 , G11C5/145 , G11C16/12 , G11C16/30
摘要： A voltage boost circuit (111) for a flash memory (100) includes a boosting circuit (110), which is capable of boosting a portion of a power supply voltage (VCC) of the flash memory to a word line voltage level adequate for accessing a core cell in a core cell array (102) of the memory. The voltage boost circuit further includes a balancing or clamping circuit (112) for providing a nonzero adjustment voltage (VCL) to the boosting circuit to reduce the portion of the supply voltage that is available for boosting by the boosting circuit when the power supply voltage exceeds a certain value.
摘要翻译：用于闪存（100）的升压电路（111）包括升压电路（110），其能够将闪存的电源电压（VCC）的一部分升压到足以访问的字线电压电平存储器的核心单元阵列（102）中的核心单元。升压电路还包括用于向升压电路提供非零调节电压（VCL）的平衡或钳位电路（112），以在电源电压超过时减小升压电路可用于升压的电源电压部分一定的价值。

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