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1. 发明授权

US07672803B1 Input of test conditions and output generation for built-in self test 有权
标题翻译：输入测试条件和输出产生内置自检
公开(公告)号：US07672803B1
公开(公告)日：2010-03-02
申请号：US11006034
申请日：2004-12-07
申请人： Mimi Lee , Darlene Hamilton , Ken Cheong Cheah
发明人： Mimi Lee , Darlene Hamilton , Ken Cheong Cheah
IPC分类号： G01R27/28
CPC分类号： G11C29/16 , G01R31/318511 , G11C16/04 , G11C29/12005 , G11C29/44
摘要： A system and method is discussed for providing programmable test conditions for a built-in self test circuit of a flash memory device. The present invention employs a flash memory having BIST circuit for testing the memory and a BIST interface circuit adapted to adjust the test conditions of the memory tests. The BIST interface circuit is operable to receive one or more global variables associated with the test conditions of a plurality of tests used on the flash memory and to output results of the memory tests based on the value of the variables. The global variables are used to adjust the test conditions and to trim one or more references used in various flash memory tests and operations. The system may further include a serial communications medium for communicating the global variables to the BIST interface and test results from the interface.
摘要翻译：讨论了一种用于为闪存器件的内置自测电路提供可编程测试条件的系统和方法。本发明采用具有用于测试存储器的BIST电路的闪速存储器和适于调整存储器测试的测试条件的BIST接口电路。 BIST接口电路可操作以接收与闪存上使用的多个测试的测试条件相关联的一个或多个全局变量，并且基于变量的值输出存储器测试的结果。全局变量用于调整测试条件并修剪用于各种闪存测试和操作的一个或多个引用。该系统还可以包括用于将全局变量传送到BIST接口的串行通信介质以及来自接口的测试结果。

2. 发明授权

US07284167B2 Automated tests for built-in self test 有权
标题翻译：自动测试内置自检
公开(公告)号：US07284167B2
公开(公告)日：2007-10-16
申请号：US11041608
申请日：2005-01-24
申请人： Mimi Lee , Darlene Hamilton , Ken Cheong Cheah , Kendra Nguyen , Xin Guo
发明人： Mimi Lee , Darlene Hamilton , Ken Cheong Cheah , Kendra Nguyen , Xin Guo
IPC分类号： G11C29/00 , G11C7/00
CPC分类号： G11C29/021 , G11C16/04 , G11C29/02 , G11C29/028 , G11C29/1201 , G11C29/16
摘要： A method is discussed for providing programmable test conditions for a built-in self test circuit of a flash memory device. The method comprises providing a BIST interface adapted to adjust a test condition used in a BIST circuit, providing the memory cells of the Flash memory device, and providing the BIST circuit adapted to test the flash memory. The method further comprises communicating with the BIST interface one or more global variables associated with the test condition, adjusting the test condition used by the BIST circuit based on the values represented by the global variables, performing one or more test operations on the flash memory in accordance with the adjusted test condition, and reporting the results of the memory test operations. The method of the present invention may further include a serial communications medium and the use of a serial test protocol for communicating the global variables to the BIST interface and test results from the interface. The global variables may also be provided by a memory device user.
摘要翻译：讨论了一种用于为闪存设备的内置自测电路提供可编程测试条件的方法。该方法包括提供BIST接口，其适于调整在BIST电路中使用的测试条件，提供闪存设备的存储单元，以及提供适于测试闪速存储器的BIST电路。该方法还包括与BIST接口通信与测试条件相关联的一个或多个全局变量，基于由全局变量表示的值来调整由BIST电路使用的测试条件，对闪速存储器执行一个或多个测试操作根据调整的测试条件，并记录测试操作的结果。本发明的方法还可以包括串行通信介质和使用串行测试协议来将全局变量传送到BIST接口并从接口测试结果。全局变量也可由存储器设备用户提供。

3. 发明授权

US07415646B1 Page—EXE erase algorithm for flash memory 有权
标题翻译：闪存的Page-EXE擦除算法
公开(公告)号：US07415646B1
公开(公告)日：2008-08-19
申请号：US10946812
申请日：2004-09-22
申请人： Mimi Lee , Darlene Hamilton , Ken Cheong Cheah
发明人： Mimi Lee , Darlene Hamilton , Ken Cheong Cheah
IPC分类号： G01R31/28
CPC分类号： G11C16/344 , G11C16/04 , G11C16/16 , G11C16/3445 , G11C29/50004 , G11C29/52 , G11C2216/18
摘要： Methods of performing a sector erase of flash memory devices incorporating built-in self test circuitry are provided. The present invention employs an interactive verification and sector erase algorithm to verify and repeatedly erase the sector until a portion of the groups of each page of the sector are erased or a first maximum number of erase pulses is achieved. The algorithm further includes a word verification and erase operation that sequentially verifies and erases each word of the sector until each word is erased or a second maximum number of erase pulses is achieved. The second maximum number of erase pulses may be based on a function of the first maximum number of erase pulses. The second maximum number of erase pulses may be input to the sector erase algorithm as a multi-bit code. The second maximum number of erase pulses and conversion of the multi-bit code may be based on a binary multiple of the first maximum number of erase pulses.
摘要翻译：提供了包含内置自测电路的闪存器件的扇区擦除方法。本发明使用交互验证和扇区擦除算法来验证并重复地擦除扇区，直到扇区的每一页的一部分组被擦除或实现了第一最大数目的擦除脉冲。该算法还包括一个字验证和擦除操作，其顺序地验证和擦除扇区的每个字，直到每个字被擦除或者实现第二个最大数量的擦除脉冲。第二最大擦除脉冲数可以基于第一最大数量的擦除脉冲的函数。擦除脉冲的第二个最大数量可以作为多位代码输入到扇区擦除算法。擦除脉冲的第二个最大数量和多位代码的转换可以基于第一最大数量的擦除脉冲的二进制数。

4. 发明申请

US20060168491A1 Automated tests for built-in self test 有权
标题翻译：自动测试内置自检
公开(公告)号：US20060168491A1
公开(公告)日：2006-07-27
申请号：US11041608
申请日：2005-01-24
申请人： Mimi Lee , Darlene Hamilton , Ken Cheah , Kendra Nguyen , Xin Guo
发明人： Mimi Lee , Darlene Hamilton , Ken Cheah , Kendra Nguyen , Xin Guo
IPC分类号： G01R31/28
CPC分类号： G11C29/021 , G11C16/04 , G11C29/02 , G11C29/028 , G11C29/1201 , G11C29/16
摘要： A method is discussed for providing programmable test conditions for a built-in self test circuit of a flash memory device. The method comprises providing a BIST interface adapted to adjust a test condition used in a BIST circuit, providing the memory cells of the Flash memory device, and providing the BIST circuit adapted to test the flash memory. The method further comprises communicating with the BIST interface one or more global variables associated with the test condition, adjusting the test condition used by the BIST circuit based on the values represented by the global variables, performing one or more test operations on the flash memory in accordance with the adjusted test condition, and reporting the results of the memory test operations. The method of the present invention may further include a serial communications medium and the use of a serial test protocol for communicating the global variables to the BIST interface and test results from the interface. The global variables may also be provided by a memory device user.
摘要翻译：讨论了一种用于为闪存设备的内置自测电路提供可编程测试条件的方法。该方法包括提供BIST接口，其适于调整在BIST电路中使用的测试条件，提供闪存设备的存储单元，以及提供适于测试闪速存储器的BIST电路。该方法还包括与BIST接口通信与测试条件相关联的一个或多个全局变量，基于由全局变量表示的值来调整由BIST电路使用的测试条件，对闪速存储器执行一个或多个测试操作根据调整的测试条件，并记录测试操作的结果。本发明的方法还可以包括串行通信介质和使用串行测试协议来将全局变量传送到BIST接口并从接口测试结果。全局变量也可由存储器设备用户提供。

5. 发明申请

US20050073886A1 Memory device and method using positive gate stress to recover overerased cell 有权
标题翻译：使用正栅极应力的存储器件和方法来恢复过度电池
公开(公告)号：US20050073886A1
公开(公告)日：2005-04-07
申请号：US10677790
申请日：2003-10-02
申请人： Darlene Hamilton , Zhizheng Liu , Mark Randolph , Yi He , Edward Hsia , Kulachet Tanpairoj , Mimi Lee , Alykhan Madhani
发明人： Darlene Hamilton , Zhizheng Liu , Mark Randolph , Yi He , Edward Hsia , Kulachet Tanpairoj , Mimi Lee , Alykhan Madhani
IPC分类号： G11C16/04 , G11C16/34 , G11C11/34
CPC分类号： G11C16/3404 , G11C16/0475 , G11C16/107 , G11C16/3409 , G11C16/344 , G11C16/3445 , G11C16/345
摘要： A method of erasing a flash electrically erasable read only memory (EEPROM) device composed of a plurality of memory cells includes pre-programming the plurality of memory cells, applying an erase pulse to the plurality of memory cells followed by an erase verification. The erase verification is followed by soft programming any memory cells having a threshold voltage below a predetermined minimum level and applying a positive gate stress to the plurality of memory cells. The erase method prevents overerasing and provides a tightened threshold voltage distribution.
摘要翻译：擦除由多个存储器单元组成的闪存电可擦除只读存储器（EEPROM）器件的方法包括对多个存储器单元进行预编程，向多个存储器单元施加擦除脉冲，随后进行擦除验证。擦除验证之后是对具有低于预定最小电平的阈值电压的任何存储器单元进行软编程，并向多个存储单元施加正栅极应力。擦除方法可以防止过压，并提供紧固的阈值电压分布。

6. 发明授权

US06768673B1 Method of programming and reading a dual cell memory device 失效
标题翻译：编程和读取双单元存储器件的方法
公开(公告)号：US06768673B1
公开(公告)日：2004-07-27
申请号：US10422276
申请日：2003-04-24
申请人： Edward Hsia , Darlene Hamilton , Kulachet Tanpairoj , Mimi Lee , Alykhan F. Madhani , Yi He
发明人： Edward Hsia , Darlene Hamilton , Kulachet Tanpairoj , Mimi Lee , Alykhan F. Madhani , Yi He
IPC分类号： G11C1604
CPC分类号： G11C16/0475 , G11C11/5628 , G11C11/5671 , G11C16/10 , G11C2211/5634
摘要： A method of programming and reading a dual cell memory device. The method includes storing a selected program level in each cell and reading one of the cells to determine a single data value stored by the memory device.
摘要翻译：一种编程和读取双单元存储器件的方法。该方法包括将所选程序级存储在每个单元中并读取单元中的一个以确定存储器件存储的单个数据值。

7. 发明授权

US08941094B2 Methods for adjusting the conductivity range of a nanotube fabric layer 有权
标题翻译：调整纳米管织物层电导率范围的方法
公开(公告)号：US08941094B2
公开(公告)日：2015-01-27
申请号：US12874501
申请日：2010-09-02
申请人： C. Rinn Cleavelin , Thomas Rueckes , H. Montgomery Manning , Darlene Hamilton , Feng Gu
发明人： C. Rinn Cleavelin , Thomas Rueckes , H. Montgomery Manning , Darlene Hamilton , Feng Gu
IPC分类号： H01L45/00 , B82Y30/00 , B82Y40/00 , H01B1/24 , H01L29/78 , H01L51/00 , H01L51/44
CPC分类号： H01L45/149 , B82Y10/00 , B82Y30/00 , B82Y40/00 , H01B1/24 , H01L29/78 , H01L51/0015 , H01L51/0048 , H01L51/444 , Y02E10/549
摘要： Methods for adjusting and/or limiting the conductivity range of a nanotube fabric layer are disclosed. In some aspects, the conductivity of a nanotube fabric layer is adjusted by functionalizing the nanotube elements within the fabric layer via wet chemistry techniques. In some aspects, the conductivity of a nanotube fabric layer is adjusted by functionalizing the nanotube elements within the fabric layer via plasma treatment. In some aspects, the conductivity of a nanotube fabric layer is adjusted by functionalizing the nanotube elements within the fabric layer via CVD treatment. In some aspects, the conductivity of a nanotube fabric layer is adjusted by functionalizing the nanotube elements within the fabric layer via an inert ion gas implant.
摘要翻译：公开了调整和/或限制纳米管织物层的电导率范围的方法。在一些方面，通过湿法化学技术使织物层内的纳米管元件功能化来调节纳米管织物层的导电性。在一些方面，通过等离子体处理使织物层内的纳米管元件功能化来调节纳米管织物层的导电性。在一些方面，通过CVD处理使织物层内的纳米管元件功能化来调节纳米管织物层的导电性。在一些方面，纳米管织物层的导电性通过惰性离子注入物官能化织物层内的纳米管元件来调节。

8. 发明授权

US08264898B2 Controlling AC disturbance while programming 有权
标题翻译：在编程时控制交流干扰
公开(公告)号：US08264898B2
公开(公告)日：2012-09-11
申请号：US13156763
申请日：2011-06-09
申请人： Sung-Yong Chung , Zhizheng Liu , Yugi Mizuguchi , Xuguang Alan Wang , Yi He , Ming Kwan , Darlene Hamilton , Sung-Chul Lee , Guowei Wang , Nancy Leong
发明人： Sung-Yong Chung , Zhizheng Liu , Yugi Mizuguchi , Xuguang Alan Wang , Yi He , Ming Kwan , Darlene Hamilton , Sung-Chul Lee , Guowei Wang , Nancy Leong
IPC分类号： G11C7/00
CPC分类号： G11C16/3418 , G11C16/0416 , G11C16/24 , G11C16/3427
摘要： A system and methodology that can minimize disturbance during an AC operation associated with a memory, such as, program, read and/or erase, is provided. The system pre-charges all or a desired subset of the bit lines in a memory array to a specified voltage, during an AC operation to facilitate reducing AC disturbances between neighboring cells. A pre-charge voltage can be applied to all bit lines in a block in the memory array, or to bit lines associated with a selected memory cell and neighbor memory cells adjacent to the selected memory cell in the block. The system ensures that source and drain voltage levels can be set to desired levels at the same or substantially the same time, while selecting a memory cell. This can facilitate minimizing AC disturbances in the selected memory cell during the AC operation.
摘要翻译：提供了一种能够在与诸如程序，读取和/或擦除之类的存储器相关联的AC操作期间最小化干扰的系统和方法。在AC操作期间，系统将存储器阵列中的所有或所需的位线子集预充电到指定的电压，以便于减少相邻单元之间的AC干扰。可以将预充电电压施加到存储器阵列中的块中的所有位线，或者对与所选择的存储器单元相关联的位线以及与块中所选择的存储单元相邻的相邻存储单元。该系统确保在选择存储器单元时，源极和漏极电压电平可以在相同或基本相同的时间被设置为期望的电平。这可以有助于在AC操作期间最小化所选择的存储器单元中的AC干扰。

9. 发明申请

US20110235412A1 CONTROLLING AC DISTURBANCE WHILE PROGRAMMING 有权
标题翻译：控制交流干扰编程
公开(公告)号：US20110235412A1
公开(公告)日：2011-09-29
申请号：US13156763
申请日：2011-06-09
申请人： Sung-Yong Chung , Zhizheng Liu , Yugi Mizuguchi , Xuguang Alan Wang , Yi He , Ming Kwan , Darlene Hamilton , Sung-Chul Lee , Guowei Wang , Nancy Leong
发明人： Sung-Yong Chung , Zhizheng Liu , Yugi Mizuguchi , Xuguang Alan Wang , Yi He , Ming Kwan , Darlene Hamilton , Sung-Chul Lee , Guowei Wang , Nancy Leong
IPC分类号： G11C16/04
CPC分类号： G11C16/3418 , G11C16/0416 , G11C16/24 , G11C16/3427
摘要： A system and methodology that can minimize disturbance during an AC operation associated with a memory, such as, program, read and/or erase, is provided. The system pre-charges all or a desired subset of the bit lines in a memory array to a specified voltage, during an AC operation to facilitate reducing AC disturbances between neighboring cells. A pre-charge voltage can be applied to all bit lines in a block in the memory array, or to bit lines associated with a selected memory cell and neighbor memory cells adjacent to the selected memory cell in the block. The system ensures that source and drain voltage levels can be set to desired levels at the same or substantially the same time, while selecting a memory cell. This can facilitate minimizing AC disturbances in the selected memory cell during the AC operation.
摘要翻译：提供了一种能够在与诸如程序，读取和/或擦除之类的存储器相关联的AC操作期间最小化干扰的系统和方法。在AC操作期间，系统将存储器阵列中的所有或所需的位线子集预充电到指定的电压，以便于减少相邻单元之间的AC干扰。可以将预充电电压施加到存储器阵列中的块中的所有位线，或者对与所选择的存储器单元相关联的位线以及与块中所选择的存储单元相邻的相邻存储单元。该系统确保在选择存储器单元时，源极和漏极电压电平可以在相同或基本相同的时间被设置为期望的电平。这可以有助于在AC操作期间最小化所选择的存储器单元中的AC干扰。

10. 发明申请

US20100103732A1 CONTROLLING AC DISTURBANCE WHILE PROGRAMMING 有权
标题翻译：控制交流干扰编程
公开(公告)号：US20100103732A1
公开(公告)日：2010-04-29
申请号：US12650118
申请日：2009-12-30
申请人： Sung-Yong Chung , Zhizheng Liu , Yugi Mizuguchi , Xuguang Alan Wang , Yi He , Ming Kwan , Darlene Hamilton , Sung-Chul Lee , Guowei Wang , Nancy Leong
发明人： Sung-Yong Chung , Zhizheng Liu , Yugi Mizuguchi , Xuguang Alan Wang , Yi He , Ming Kwan , Darlene Hamilton , Sung-Chul Lee , Guowei Wang , Nancy Leong
IPC分类号： G11C16/04 , G11C16/06
CPC分类号： G11C16/3418 , G11C16/0416 , G11C16/24 , G11C16/3427
摘要： A system and methodology that can minimize disturbance during an AC operation associated with a memory, such as, program, read and/or erase, is provided. The system pre-charges all or a desired subset of the bit lines in a memory array to a specified voltage, during an AC operation to facilitate reducing AC disturbances between neighboring cells. A pre-charge voltage can be applied to all bit lines in a block in the memory array, or to bit lines associated with a selected memory cell and neighbor memory cells adjacent to the selected memory cell in the block. The system ensures that source and drain voltage levels can be set to desired levels at the same or substantially the same time, while selecting a memory cell. This can facilitate minimizing AC disturbances in the selected memory cell during the AC operation.
摘要翻译：提供了一种能够在与诸如程序，读取和/或擦除之类的存储器相关联的AC操作期间最小化干扰的系统和方法。在AC操作期间，系统将存储器阵列中的所有或所需的位线子集预充电到指定的电压，以便于减少相邻单元之间的AC干扰。可以将预充电电压施加到存储器阵列中的块中的所有位线，或者对与所选择的存储器单元相关联的位线以及与块中所选择的存储单元相邻的相邻存储单元。该系统确保在选择存储器单元时，源极和漏极电压电平可以在相同或基本相同的时间被设置为期望的电平。这可以有助于在AC操作期间最小化所选择的存储器单元中的AC干扰。

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