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1. 发明申请

US20050179107A1 Low doped layer for nitride-based semiconductor device 失效
标题翻译：用于氮化物基半导体器件的低掺杂层
公开(公告)号：US20050179107A1
公开(公告)日：2005-08-18
申请号：US10780526
申请日：2004-02-17
申请人： Milan Pophristic , Michael Murphy , Richard Stall , Bryan Shelton , Linlin Liu , Alex Ceruzzi
发明人： Milan Pophristic , Michael Murphy , Richard Stall , Bryan Shelton , Linlin Liu , Alex Ceruzzi
IPC分类号： H01L21/28 , H01L29/15 , H01L29/20 , H01L29/45 , H01L29/47 , H01L29/778 , H01L29/872 , H01L27/095
CPC分类号： H01L29/452 , H01L29/157 , H01L29/2003 , H01L29/475 , H01L29/7787 , H01L29/872
摘要： A repeatable and uniform low doped layer is formed using modulation doping by forming alternating sub-layers of doped and undoped nitride semiconductor material atop another layer. A Schottky diode is formed of such a low doped nitride semiconductor layer disposed atop a much more highly doped nitride semiconductor layer. The resulting device has both a low on-resistance when the device is forward biased and a high breakdown voltage when the device is reverse biased.
摘要翻译：通过在另一层上形成掺杂和未掺杂的氮化物半导体材料的交替子层，通过调制掺杂形成可重复且均匀的低掺杂层。肖特基二极管由设置在更高掺杂的氮化物半导体层顶上的这种低掺杂氮化物半导体层形成。当器件正向偏置时，所得器件具有低导通电阻，器件反向偏置时具有高击穿电压。

2. 发明申请

US20050179104A1 Lateral conduction schottky diode with plural mesas 有权
标题翻译：具有多个台面的横向导通肖特基二极管
公开(公告)号：US20050179104A1
公开(公告)日：2005-08-18
申请号：US10780363
申请日：2004-02-17
申请人： Bryan Shelton , Linlin Liu , Alex Ceruzzi , Michael Murphy , Milan Pophristic , Boris Peres , Richard Stall , Xiang Gao , Ivan Eliashevich
发明人： Bryan Shelton , Linlin Liu , Alex Ceruzzi , Michael Murphy , Milan Pophristic , Boris Peres , Richard Stall , Xiang Gao , Ivan Eliashevich
IPC分类号： H01L21/60 , H01L29/06 , H01L29/20 , H01L29/47 , H01L29/872 , H01L21/00 , H01L31/0328
CPC分类号： H01L24/81 , H01L29/0692 , H01L29/2003 , H01L29/872 , H01L2224/81801 , H01L2924/01005 , H01L2924/01006 , H01L2924/01012 , H01L2924/01013 , H01L2924/01023 , H01L2924/0103 , H01L2924/01032 , H01L2924/01033 , H01L2924/01049 , H01L2924/01078 , H01L2924/01079 , H01L2924/01087 , H01L2924/014 , H01L2924/12032 , H01L2924/00
摘要： A lateral conduction Schottky diode includes multiple mesa regions upon which Schottky contacts are formed and which are at least separated by ohmic contacts to reduce the current path length and reduce current crowding in the Schottky contact, thereby reducing the forward resistance of a device. The multiple mesas may be isolated from one another and have sizes and shapes optimized for reducing the forward resistance. Alternatively, some of the mesas may be finger-shaped and intersect with a central mesa or a bridge mesa, and some or all of the ohmic contacts are interdigitated with the finger-shaped mesas. The dimensions of the finger-shaped mesas and the perimeter of the intersecting structure may be optimized to reduce the forward resistance. The Schottky diodes may be mounted to a submount in a flip chip arrangement that further reduces the forward voltage as well as improves power dissertation and reduces heat generation.
摘要翻译：横向导通肖特基二极管包括形成肖特基接触的多个台面区域，其至少由欧姆接触分开，以减小电流路径长度并减少肖特基接触中的电流拥挤，从而降低器件的正向电阻。多个台面可以彼此隔离并且具有优化的尺寸和形状以减少前向阻力。或者，一些台面可以是手指形状并与中央台面或桥台面相交，并且部分或全部欧姆接触件与指状台面相互交错。指状台面的尺寸和相交结构的周长可以被优化以减小正向阻力。肖特基二极管可以以倒装芯片布置的方式安装到基座上，这进一步降低了正向电压，并且改善了功率论文并减少了发热。

3. 发明申请

US20050202661A1 Non-activated guard ring for semiconductor devices 失效
标题翻译：半导体器件非激活保护环
公开(公告)号：US20050202661A1
公开(公告)日：2005-09-15
申请号：US10935000
申请日：2004-09-07
申请人： Alex Ceruzzi , Milan Pophristic , Bryan Shelton , Linlin Liu , Michael Murphy , Ting Zhu
发明人： Alex Ceruzzi , Milan Pophristic , Bryan Shelton , Linlin Liu , Michael Murphy , Ting Zhu
IPC分类号： H01L21/44
CPC分类号： H01L29/32 , H01L29/0615 , H01L29/0619 , H01L29/0634 , H01L29/2003 , H01L29/207 , H01L29/452 , H01L29/475 , H01L29/66143 , H01L29/66212 , H01L29/872
摘要： A guard ring is formed in a semiconductor region that is part of a Schottky junction or Schottky diode. The guard ring is formed by ion implantation into the semiconductor contact layer without completely annealing the semiconductor contact layer to form a high resistance region. The guard ring may be located at the edge of the layer or, alternatively, at a distance away from the edge of the layer. A Schottky metal contact is formed atop the layer, and the edges of the Schottky contact are disposed atop the guard ring.
摘要翻译：在作为肖特基结或肖特基二极管的一部分的半导体区域中形成保护环。保护环通过离子注入形成于半导体接触层中，而不会使半导体接触层完全退火以形成高电阻区域。保护环可以位于层的边缘处，或者可选地，离开层的边缘一定距离。肖特基金属接触形成在层的顶部，肖特基接触的边缘设置在保护环的顶部。

4. 发明申请

US20060154455A1 Gallium nitride-based devices and manufacturing process 审中-公开
标题翻译：基于氮化镓的器件及制造工艺
公开(公告)号：US20060154455A1
公开(公告)日：2006-07-13
申请号：US11371738
申请日：2006-03-09
申请人： Shiping Guo , David Gotthold , Milan Pophristic , Boris Peres , Ivan Eliashevich , Bryan Shelton , Alex Ceruzzi , Michael Murphy , Richard Stall
发明人： Shiping Guo , David Gotthold , Milan Pophristic , Boris Peres , Ivan Eliashevich , Bryan Shelton , Alex Ceruzzi , Michael Murphy , Richard Stall
IPC分类号： H01L21/20 , H01L21/36 , H01L31/20
CPC分类号： H01L29/155 , C30B29/68 , H01L21/02381 , H01L21/02458 , H01L21/02491 , H01L21/02507 , H01L21/0254 , H01L29/2003 , H01L33/007
摘要： A nitride semiconductor is grown on a silicon substrate by depositing a few mono-layers of aluminum to protect the silicon substrate from ammonia used during the growth process, and then forming a nucleation layer from aluminum nitride and a buffer structure including multiple superlattices of AlRGa(1-R)N semiconductors having different compositions and an intermediate layer of GaN or other Ga-rich nitride semiconductor. The resulting structure has superior crystal quality. The silicon substrate used in epitaxial growth is removed before completion of the device so as to provide superior electrical properties in devices such as high-electron mobility transistors.
摘要翻译：在硅衬底上生长氮化物半导体，通过沉积几个单层铝，以保护硅衬底免受生长过程中使用的氨的影响，然后从氮化铝形成成核层，并形成包含多个超晶格Al 具有不同组成的半导体和GaN或其它富镓氮化物半导体的中间层的半导体。所得结构具有优异的晶体质量。在器件完成之前除去用于外延生长的硅衬底，以便在诸如高电子迁移率晶体管的器件中提供优异的电性能。

5. 发明申请

US20060151868A1 Package for gallium nitride semiconductor devices 审中-公开
标题翻译：氮化镓半导体器件封装
公开(公告)号：US20060151868A1
公开(公告)日：2006-07-13
申请号：US11032666
申请日：2005-01-10
申请人： TingGang Zhu , Bryan Shelton , Marek Pabisz , Mark Gottfried , Linlin Liu , Boris Peres , Alex Ceruzzi
发明人： TingGang Zhu , Bryan Shelton , Marek Pabisz , Mark Gottfried , Linlin Liu , Boris Peres , Alex Ceruzzi
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L23/3107 , H01L23/49562 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L2224/32245 , H01L2224/45015 , H01L2224/45124 , H01L2224/45144 , H01L2224/48091 , H01L2224/48247 , H01L2224/48257 , H01L2224/48472 , H01L2224/49171 , H01L2224/73265 , H01L2924/00011 , H01L2924/00014 , H01L2924/014 , H01L2924/10253 , H01L2924/10272 , H01L2924/12032 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/19043 , H01L2924/20755 , H01L2924/2076 , H01L2924/3011 , H01L2924/00 , H01L2924/00012 , H01L2224/43 , H01L2924/01006
摘要： A packaged semiconductor device, in particular a gallium nitride semiconductor structure including a lower semiconductor layer and an upper semiconductor layer disposed over a portion of the lower semiconductor layer. The semiconductor structure includes a plurality of mesas projecting upwardly from the lower layer, each of the mesas including a portion of the upper layer and defining an upper contact surface separated form adjacent mesas by a portion of the lower layer surface. The device further includes a die mounting support, wherein the bottom surface of the die is attached to the top surface of the die mounting support; and a plurality of spaced external conductors extending from the support, at least once of said spaced external conductors having a bond wire post at one end thereof; with a bonding wire extending between the bond wire post and a contact region to the top surface of the plurality of mesas.
摘要翻译：封装的半导体器件，特别是包括下半导体层和设置在下半导体层的一部分上的上半导体层的氮化镓半导体结构。半导体结构包括从下层向上突出的多个台面，每个台面包括上层的一部分，并且限定由下层表面的一部分与相邻台面分开的上接触表面。该装置还包括模具安装支撑件，其中模具的底表面附接到模具安装支撑件的顶表面; 以及从所述支撑件延伸的多个间隔开的外部导体，所述间隔开的外部导体中的至少一个在其一端具有接合线柱; 其中接合线在接合线柱和与多个台面的顶表面之间的接触区域之间延伸。

6. 发明申请

US20060076589A1 PIN photodiode structure and fabrication process for reducing dielectric delamination 有权
标题翻译： PIN光电二极管结构和减少介电分层的制造工艺
公开(公告)号：US20060076589A1
公开(公告)日：2006-04-13
申请号：US11079708
申请日：2005-03-14
申请人： Xiang Gao , Alex Ceruzzi , Steve Schwed , Linlin Liu , Mark Gottfried
发明人： Xiang Gao , Alex Ceruzzi , Steve Schwed , Linlin Liu , Mark Gottfried
IPC分类号： H01L31/113
CPC分类号： H01L31/02161 , H01L31/105
摘要： A PIN photodiode, and a method of manufacturing a PIN photodiode that reduces dielectric delamination and increases device reliability. The process proceeds by forming an first type electrode layer on the substrate; forming an intrinsic layer of the first type electrode layer; forming a second type electrode layer on the intrinsic layer; etching the second type electrode layer to define a mesa shaped structure; and depositing a passivation material over the mesa shaped structure.
摘要翻译： PIN光电二极管，以及制造PIN光电二极管的方法，该光电二极管降低了介质分层并提高了器件可靠性。该工艺通过在衬底上形成第一类型电极层而进行; 形成第一类型电极层的本征层; 在本征层上形成第二类型的电极层; 蚀刻第二类型电极层以限定台面形结构; 以及在所述台面形结构上沉积钝化材料。

7. 发明授权

US07538403B2 PIN diode structure with zinc diffusion region 失效
标题翻译： PIN二极管结构与锌扩散区
公开(公告)号：US07538403B2
公开(公告)日：2009-05-26
申请号：US11230959
申请日：2005-09-19
申请人： Xiang Gao , Alex Ceruzzi , Linlin Liu , Stephen Schwed
发明人： Xiang Gao , Alex Ceruzzi , Linlin Liu , Stephen Schwed
IPC分类号： H01L27/15
CPC分类号： H01L31/105
摘要： A PIN photodiode having a substrate, a first type electrode layer disposed on the substrate, a first layer of intrinsic material disposed over a portion of the first-type electrode layer, a first type window layer disposed over said intrinsic layer. An island shaped region of intrinsic material is disposed over the window layer and a dielectric layer disposed over the island region and at least the peripheral portion of said island shaped region whereby an opening is formed in the island shaped region. A dopant is diffused through the opening so as to form a PN junction that extends into the first layer of intrinsic material.
摘要翻译：具有衬底的PIN光电二极管，设置在衬底上的第一类型电极层，设置在第一类型电极层的一部分上的第一本征材料层，设置在所述本征层上的第一类型窗口层。本征材料的岛状区域设置在窗口层上方，并且设置在岛状区域和至少所述岛状区域的周边部分上的电介质层，从而在岛状区域中形成开口。掺杂剂通过开口扩散，以便形成延伸到本征材料的第一层中的PN结。

8. 发明授权

US08022495B2 PIN diode structure with zinc diffusion region 失效
标题翻译： PIN二极管结构与锌扩散区
公开(公告)号：US08022495B2
公开(公告)日：2011-09-20
申请号：US12420213
申请日：2009-04-08
申请人： Xiang Gao , Alex Ceruzzi , Linlin Liu , Stephen Schwed
发明人： Xiang Gao , Alex Ceruzzi , Linlin Liu , Stephen Schwed
IPC分类号： H01L31/06
CPC分类号： H01L31/105
摘要： A PIN photodiode having a substrate, a first type electrode layer disposed on the substrate, a first layer of intrinsic material disposed over a portion of the first-type electrode layer, and a first type window layer disposed over the intrinsic layer. An island shaped region of intrinsic material is disposed over the window layer and a dielectric layer is disposed over the island region and at least the peripheral portion of said island shaped region whereby an opening is formed in the island shaped region. A dopant is diffused through the opening so as to form a PN junction that extends into the first layer of intrinsic material.
摘要翻译： PIN光电二极管，其具有基板，设置在基板上的第一类型电极层，设置在第一类型电极层的一部分上的第一本征材料层，以及设置在本征层上的第一类型窗口层。本征材料的岛状区域设置在窗口层上方，并且电介质层设置在岛状区域和至少所述岛状区域的周边部分上，从而在岛状区域中形成开口。掺杂剂通过开口扩散，以便形成延伸到本征材料的第一层中的PN结。

9. 发明授权

US07439599B2 PIN photodiode structure and fabrication process for reducing dielectric delamination 有权
标题翻译： PIN光电二极管结构和减少介电分层的制造工艺
公开(公告)号：US07439599B2
公开(公告)日：2008-10-21
申请号：US11079708
申请日：2005-03-14
申请人： Xiang Gao , Alex Ceruzzi , Steve Schwed , Linlin Liu , Mark Gottfried
发明人： Xiang Gao , Alex Ceruzzi , Steve Schwed , Linlin Liu , Mark Gottfried
IPC分类号： H01L31/00
CPC分类号： H01L31/02161 , H01L31/105
摘要： A PIN photodiode, and a method of manufacturing a PIN photodiode that reduces dielectric delamination and increases device reliability. The process proceeds by forming an first type electrode layer on the substrate; forming an intrinsic layer of the first type electrode layer; forming a second type electrode layer on the intrinsic layer; etching the second type electrode layer to define a mesa shaped structure; and depositing a passivation material over the mesa shaped structure.
摘要翻译： PIN光电二极管，以及制造PIN光电二极管的方法，该光电二极管减少了介质分层并提高了器件的可靠性该工艺通过在衬底上形成第一类型电极层而进行; 形成第一类型电极层的本征层; 在本征层上形成第二类型的电极层; 蚀刻第二类型电极层以限定台面形结构; 以及在所述台面形结构上沉积钝化材料。

10. 发明申请

US20060060933A1 PIN diode structure with zinc diffusion region 失效
公开(公告)号：US20060060933A1
公开(公告)日：2006-03-23
申请号：US11230959
申请日：2005-09-19
申请人： Xiang Gao , Alex Ceruzzi , Linlin Liu , Stephen Schwed
发明人： Xiang Gao , Alex Ceruzzi , Linlin Liu , Stephen Schwed
IPC分类号： H01L31/105
CPC分类号： H01L31/105
摘要： A PIN photodiode having a substrate, a first type electrode layer disposed on the substrate, a first layer of intrinsic material disposed over a portion of the first-type electrode layer, a first type window layer disposed over said intrinsic layer. An island shaped region of intrinsic material is disposed over the window layer and a dielectric layer disposed over the island region and at least the peripheral portion of said island shaped region whereby an opening is formed in the island shaped region. A dopant is diffused through the opening so as to form a PN junction that extends into the first layer of intrinsic material.

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