专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06260105B1 Memory controller with a plurality of memory address buses 失效
标题翻译：具有多个存储器地址总线的存储器控制器
公开(公告)号：US06260105B1
公开(公告)日：2001-07-10
申请号：US08954620
申请日：1997-10-20
申请人： Mike W. Williams , Jasmin Ajanovic , Joseph H. Salmon
发明人： Mike W. Williams , Jasmin Ajanovic , Joseph H. Salmon
IPC分类号： G06F1206
CPC分类号： G06F13/1684 , Y02D10/14
摘要： A memory controller for a computer system includes a first memory address bus and a second memory, address bus. The memory controller further includes circuitry that toggles one of the first and second memory address buses at a time. Because only one memory address bus is toggled at once, the first and second memory address buses can share power and ground pins, thereby reducing the number of power and ground pins on the memory controller.
摘要翻译：用于计算机系统的存储器控制器包括第一存储器地址总线和第二存储器地址总线。存储器控制器还包括一次切换第一和第二存储器地址总线之一的电路。因为一次只切换一个存储器地址总线，所以第一和第二存储器地址总线可以共享电源和接地引脚，从而减少存储器控制器上的电源和接地引脚的数量。

2. 发明申请

US20110320867A1 METHOD AND APPARATUS FOR TRAINING A MEMORY SIGNAL VIA AN ERROR SIGNAL OF A MEMORY 有权
标题翻译：用于通过存储器的错误信号训练存储信号的方法和装置
公开(公告)号：US20110320867A1
公开(公告)日：2011-12-29
申请号：US12824675
申请日：2010-06-28
申请人： Santanu Chaudhuri , Joseph H. Salmon , Kuljit S. Bains
发明人： Santanu Chaudhuri , Joseph H. Salmon , Kuljit S. Bains
IPC分类号： G06F11/07
CPC分类号： G06F11/0793 , G06F11/073 , G06F13/1689 , G11C2207/2254
摘要： Described herein is a method and an apparatus for training a memory signal via an error signal of a memory. The method comprises transmitting from a memory controller a command-address (C/A) signal to a memory module; determining by the memory controller an error in the memory module via an error signal from an error pin of the memory module, the error associated with the C/A signal transmitted to the memory module; and modifying by the memory controller the C/A signal in response to determining an error in the memory module, wherein the error pin is a parity error pin of the memory module, and wherein the memory module comprises a Double Data Rate 4 (DDR4) interface.
摘要翻译：这里描述了一种通过存储器的误差信号来训练存储器信号的方法和装置。该方法包括从存储器控制器向存储器模块发送命令地址（C / A）信号; 由存储器控制器通过来自存储器模块的错误引脚的错误信号确定存储器模块中的错误，该错误与传送到存储器模块的C / A信号相关联; 以及响应于确定所述存储器模块中的错误，由所述存储器控制器修改所述C / A信号，其中所述错误引脚是所述存储器模块的奇偶校验错误引脚，并且其中所述存储器模块包括双倍数据速率4（DDR4）接口。

3. 发明授权

US5257221A Apparatus for selecting mumber of wait states in a burst EPROM architecture 失效
标题翻译：用于在突发EPROM架构中选择等待状态的数量的装置
公开(公告)号：US5257221A
公开(公告)日：1993-10-26
申请号：US981949
申请日：1992-11-25
申请人： David A. Leak , Joseph H. Salmon , Robert E. Larsen
发明人： David A. Leak , Joseph H. Salmon , Robert E. Larsen
IPC分类号： G11C16/18 , G11C5/00
CPC分类号： G11C16/18
摘要： A mechanism to change the functionality of a state machine used to control operation of an EPROM device. The mechanism is programmed to generate logic level signals which are input to combinatorial logic used to implement the state machine to cause the state machine to operate with a predetermined number of wait states (typically on, two or three wait states) depending on the programming applied to the mechanism. The mechanism utilizes EPROM cells which are covered by a shield so that once programmed, they cannot be erased. The programming is performed after the part has been manufactured, but before shipment to a customer who, upon receipt of the part programs the EPROM in the usual manner. The programmed EPROM can then be erased nd reprogrammed without affecting the programming defining the number of wait states generated during operation of the state machine.
摘要翻译：用于改变用于控制EPROM设备的操作的状态机的功能的机制。该机制被编程为产生逻辑电平信号，其被输入到用于实现状态机的组合逻辑，以使得状态机以预定数量的等待状态（通常为两个或三个等待状态）运行，这取决于所应用的编程的机制。该机制利用被屏蔽覆盖的EPROM单元，因此一旦编程，它们就不能被擦除。编程在零件制造完成之后，在装运到客户之前，以通常的方式接收到EPROM的零件程序。然后可以擦除编程的EPROM并重新编程，而不影响定义状态机操作期间产生的等待状态数量的编程。

4. 发明申请

US20080151591A1 Memory system with a configurable number of read data bits 审中-公开
标题翻译：具有可配置数量的读取数据位的存储器系统
公开(公告)号：US20080151591A1
公开(公告)日：2008-06-26
申请号：US11644607
申请日：2006-12-21
申请人： Kevin J. Doran , Joseph H. Salmon , Michael W. Williams
发明人： Kevin J. Doran , Joseph H. Salmon , Michael W. Williams
IPC分类号： G11C5/06 , H05K5/00
CPC分类号： G11C5/04
摘要： In some embodiments, a chip includes transmitter circuitry, receiver circuitry, and control circuitry to detect whether a memory module is coupled to the receiver circuitry. The control circuitry selectively provides memory chip configuration signals to the transmitter circuitry to be provided to memory chips to control how many interface lanes in the memory chips are to be used to carry read data in response to a read request and whether some of the interface lanes are used for carrying read data signals or command signals. Other embodiments are described.
摘要翻译：在一些实施例中，芯片包括发射器电路，接收器电路和控制电路，以检测存储器模块是否耦合到接收器电路。控制电路选择性地向发射机电路提供存储器芯片配置信号以提供给存储器芯片，以控制存储器芯片中的多少个接口通道将被用于响应于读取请求而携带读取数据，以及一些接口通道用于承载读数据信号或命令信号。描述其他实施例。

5. 发明授权

US06941484B2 Synthesis of a synchronization clock 有权
标题翻译：合成同步时钟
公开(公告)号：US06941484B2
公开(公告)日：2005-09-06
申请号：US10090080
申请日：2002-03-01
申请人： Hing Y. To , Joseph H. Salmon , Michael W. Williams
发明人： Hing Y. To , Joseph H. Salmon , Michael W. Williams
IPC分类号： G06F1/06 , G11C7/10 , G11C7/22 , G06F1/12
CPC分类号： G11C7/1084 , G06F1/06 , G11C7/1078 , G11C7/22 , G11C7/222 , G11C2207/2254
摘要： A method, system, and device capable of generating one or more clocks internally to detect, sample, and receive synchronous data streams and eliminate the need for corresponding external synchronization clocks for each data stream. One aspect of the clock generator provides a two-stage interpolation system. In a first stage, two clocks are selected which accurately detect a calibration data sample. In a second stage, a single, fine-tuned, clock is synthesized by interpolating the two selected clocks.
摘要翻译：一种能够在内部产生一个或多个时钟来检测，采样和接收同步数据流并消除对每个数据流的相应外部同步时钟的需要的方法，系统和装置。时钟发生器的一个方面提供了两级插值系统。在第一阶段，选择精确检测校准数据样本的两个时钟。在第二阶段，通过内插两个所选择的时钟来合成单个微调时钟。

6. 发明授权

US5533196A Method and apparatus for testing for a sufficient write voltage level during power up of a SRAM array 失效
标题翻译：用于在SRAM阵列加电期间测试足够的写入电压电平的方法和装置
公开(公告)号：US5533196A
公开(公告)日：1996-07-02
申请号：US189307
申请日：1994-01-31
申请人： Joseph H. Salmon
发明人： Joseph H. Salmon
IPC分类号： G11C29/02 , G06F11/34
CPC分类号： G11C29/02
摘要： A SRAM testing circuit utilized to assure that a voltage is at a sufficient level for accessing a memory cell including a pair of memory cells each including those elements necessary to duplicate the memory cells of an associated memory array, a circuit for providing alternating-valued input signals for writing to the pair of memory cells during each clock period at which a write operation may occur, apparatus for emulating the load provided to a bitline of an associated memory array, apparatus for applying the input signals to one of the pair of memory cells and applying the inverse of the input signals to the other of the pair of memory cells, apparatus for testing both the condition of each of the memory cells after the application of the input and inverse input signals against the condition of the signals provided to each of the cells to determine if each of the pair of memory cells has switched to the appropriate condition, and apparatus for generating a fail signal if either one of the pair of memory cells has not switched to the appropriate condition.
摘要翻译：一种SRAM测试电路，用于确保电压处于足够的水平，用于访问包括一对存储单元的存储单元，每个存储单元包括复制相关存储器阵列的存储单元所需的那些元件，用于提供交替输入的电路用于在可能发生写入操作的每个时钟周期期间写入到该对存储器单元的信号，用于模拟提供给相关联的存储器阵列的位线的装置的装置，用于将输入信号施加到该对存储单元之一以及将所述输入信号的反相应用于所述一对存储器单元中的另一个，用于在施加所述输入和所述输入信号之后测试每个所述存储器单元的状态的装置，确定所述一对存储单元中的每一个是否切换到适当的条件，以及用于产生失败信号的装置的一对存储单元没有切换到适当的条件。

7. 发明授权

US5490109A Method and apparatus for preventing over-erasure of flash EEPROM memory devices 失效
标题翻译：防止闪存EEPROM存储器件过度擦除的方法和装置
公开(公告)号：US5490109A
公开(公告)日：1996-02-06
申请号：US267472
申请日：1994-06-28
申请人： Joseph H. Salmon
发明人： Joseph H. Salmon
IPC分类号： G11C16/16 , G11C16/34 , G11C11/34
CPC分类号： G11C16/3477 , G11C16/16 , G11C16/3468
摘要： An arrangement for controlling the application of erase biasing voltages to the memory devices of a flash EEPROM memory array which arrangement precludes application of any erase biasing voltage until all of the devices are tested to determine which if any devices are programmed, and then allows application of erase bias voltages only to those blocks of the memory array which include devices which are programmed. In one embodiment, a power-on state machine which is used to read the state of the devices to initialize the array is used to test the condition of the array whenever an erase is desired and latching means are used with each block to preclude any erasing until it is determined that the block, in fact, includes programmed devices.
摘要翻译：一种用于控制对闪存EEPROM存储器阵列的存储器件施加擦除偏置电压的装置，该布置排除了施加任何擦除偏置电压，直到所有器件被测试，以确定哪个器件是否被编程，然后允许应用将偏置电压擦除到存储器阵列的那些包括被编程的器件的块。在一个实施例中，用于读取初始化阵列的设备的状态的开机状态机用于在需要擦除时测试阵列的状况，并且每个块使用锁存装置以排除任何擦除直到确定该块实际上包括已编程的设备。

8. 发明授权

US5057715A CMOS output circuit using a low threshold device 失效
标题翻译： CMOS输出电路采用低阈值器件
公开(公告)号：US5057715A
公开(公告)日：1991-10-15
申请号：US456081
申请日：1989-12-21
申请人： Robert E. Larsen , Khandker N. Quader , Joseph H. Salmon
发明人： Robert E. Larsen , Khandker N. Quader , Joseph H. Salmon
IPC分类号： H03K19/003
CPC分类号： H03K19/00315
摘要： A CMOS output driver includes an n-channel low threshold device in series between a p-channel transistor and an output terminal. Under normal driver operation, the low threshold transistor drops essentially zero volts and is imperceptible in the circuit. However, under special mode conditions when high voltage is applied to the output terminal, the low threshold transistor stops conducting when the output terminal approaches Vcc, so that any further increase in the voltage at the output terminal cannot be applied to the drain of the p-channel transistor which can cause its failure.
摘要翻译： CMOS输出驱动器包括串联在p沟道晶体管和输出端之间的n沟道低阈值器件。在正常的驱动器操作下，低阈值晶体管基本上下降了零伏，并且在电路中是不可察觉的。然而，当在输出端子施加高电压时的特殊模式条件下，当输出端子接近Vcc时，低阈值晶体管停止导通，使得输出端子处的电压的任何进一步增加不能施加到p的漏极可能导致其故障的通道晶体管。

9. 发明授权

US06421801B1 Testing IO timing in a delay locked system using separate transmit and receive loops 有权
标题翻译：使用单独的发送和接收循环来测试延迟锁定系统中的IO时序
公开(公告)号：US06421801B1
公开(公告)日：2002-07-16
申请号：US09327942
申请日：1999-06-08
申请人： John T. Maddux , Joseph H. Salmon
发明人： John T. Maddux , Joseph H. Salmon
IPC分类号： G06F1100
CPC分类号： G01R31/319
摘要： A method and apparatus for testing an input data path of an integrated circuit. Dual transmit and receive delay locked loops (DLLs) provide clocks for test mode data transmit and receive. Test mode logic drives a data pattern into an input receiver with the data pattern clocked by the transmit DLL and the input receiver clock by the receive DLL. The output of the input receiver is compared with the data pattern. The transmit DLL is adjusted relative to the receive DLL to measure setup and hold times of the data pattern driven through the input receiver.
摘要翻译：一种用于测试集成电路的输入数据路径的方法和装置。双发送和接收延迟锁定环（DLL）为测试模式数据发送和接收提供时钟。测试模式逻辑将数据模式驱动到具有由发送DLL定时的数据模式和由接收DLL输入的接收器时钟的输入接收器中。将输入接收机的输出与数据模式进行比较。发送DLL相对于接收DLL进行调整，以测量通过输入接收器驱动的数据模式的建立和保持时间。

10. 发明授权

US06381722B1 Method and apparatus for testing high speed input paths 失效
标题翻译：用于测试高速输入路径的方法和装置
公开(公告)号：US06381722B1
公开(公告)日：2002-04-30
申请号：US09327943
申请日：1999-06-08
申请人： Joseph H. Salmon , John T. Maddux
发明人： Joseph H. Salmon , John T. Maddux
IPC分类号： G01R3130
CPC分类号： G01R31/3016
摘要： A method and circuit to test for defects in the input path of an integrated circuit by providing a logic pattern data to a scan chain of the integrated circuit and testing setup and hold timing parameters. The method including determining a maximum value for a timing parameter and generating a data pattern with the timing parameter having the maximum value. The method also including monitoring an output of a logic function performed on the data pattern and adjusting the value of the timing parameter based on the output of the logic function.
摘要翻译：一种用于通过向集成电路的扫描链提供逻辑图案数据并测试建立和保持定时参数来测试集成电路的输入路径中的缺陷的方法和电路。该方法包括确定定时参数的最大值并且产生具有最大值的定时参数的数据模式。该方法还包括监视对数据模式执行的逻辑功能的输出，并且基于逻辑功能的输出来调整定时参数的值。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式