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1. 发明授权

US06941484B2 Synthesis of a synchronization clock 有权
标题翻译：合成同步时钟
公开(公告)号：US06941484B2
公开(公告)日：2005-09-06
申请号：US10090080
申请日：2002-03-01
申请人： Hing Y. To , Joseph H. Salmon , Michael W. Williams
发明人： Hing Y. To , Joseph H. Salmon , Michael W. Williams
IPC分类号： G06F1/06 , G11C7/10 , G11C7/22 , G06F1/12
CPC分类号： G11C7/1084 , G06F1/06 , G11C7/1078 , G11C7/22 , G11C7/222 , G11C2207/2254
摘要： A method, system, and device capable of generating one or more clocks internally to detect, sample, and receive synchronous data streams and eliminate the need for corresponding external synchronization clocks for each data stream. One aspect of the clock generator provides a two-stage interpolation system. In a first stage, two clocks are selected which accurately detect a calibration data sample. In a second stage, a single, fine-tuned, clock is synthesized by interpolating the two selected clocks.
摘要翻译：一种能够在内部产生一个或多个时钟来检测，采样和接收同步数据流并消除对每个数据流的相应外部同步时钟的需要的方法，系统和装置。时钟发生器的一个方面提供了两级插值系统。在第一阶段，选择精确检测校准数据样本的两个时钟。在第二阶段，通过内插两个所选择的时钟来合成单个微调时钟。

2. 发明授权

US07117401B2 Method and apparatus for optimizing timing for a multi-drop bus 有权
标题翻译：用于优化多点总线定时的方法和装置
公开(公告)号：US07117401B2
公开(公告)日：2006-10-03
申请号：US11121789
申请日：2005-05-04
申请人： Joseph H. Salmon , Hing Y. To
发明人： Joseph H. Salmon , Hing Y. To
IPC分类号： H04L1/24
CPC分类号： G11C29/50 , G06F13/4243 , G11C29/028 , G11C29/50012
摘要： A first device delivers a clock offset message to a second device. The second device offsets its data transmission according to the clock offset message. A test pattern is transmitted from the second device to the first device. The first device then checks the received test pattern to determine whether the transmission was successful. The first device can then deliver an additional clock offset message to the second device to instruct the second device to offset its data transmission by a different value than was used previously. The second device again transmits the test pattern and the first device again checks the received pattern. By trying a number of clock offset values and determining which values result in successful transmissions of data, the first device can determine the optimal clock offset value and instruct the second device to use this value for all transmissions.
摘要翻译：第一设备向第二设备递送时钟偏移消息。第二个设备根据时钟偏移消息来抵消其数据传输。测试模式从第二设备发送到第一设备。然后，第一个设备检查接收的测试模式，以确定传输是否成功。然后，第一设备可以向第二设备传送额外的时钟偏移消息，以指示第二设备将其数据传输偏移与先前使用的不同的值。第二设备再次发送测试模式，并且第一设备再次检查接收到的模式。通过尝试多个时钟偏移值并确定哪些值导致数据的成功传输，第一设备可以确定最佳时钟偏移值，并且指示第二设备将该值用于所有传输。

3. 发明授权

US06973603B2 Method and apparatus for optimizing timing for a multi-drop bus 失效
标题翻译：用于优化多点总线定时的方法和装置
公开(公告)号：US06973603B2
公开(公告)日：2005-12-06
申请号：US10187349
申请日：2002-06-28
申请人： Joseph H. Salmon , Hing Y. To
发明人： Joseph H. Salmon , Hing Y. To
IPC分类号： G06F11/00 , G06F13/42 , G11C8/00 , G11C29/50 , H04J3/06 , H04L1/24
CPC分类号： G11C29/50 , G06F13/4243 , G11C29/028 , G11C29/50012
摘要： A first device delivers a clock offset message to a second device. The second device offsets its data transmission according to the clock offset message. A test pattern is transmitted from the second device to the first device. The first device then checks the received test pattern to determine whether the transmission was successful. The first device can then deliver an additional clock offset message to the second device to instruct the second device to offset its data transmission by a different value than was used previously. The second device again transmits the test pattern and the first device again checks the received pattern. By trying a number of clock offset values and determining which values result in successful transmissions of data, the first device can determine the optimal clock offset value and instruct the second device to use this value for all transmissions.
摘要翻译：第一设备向第二设备递送时钟偏移消息。第二个设备根据时钟偏移消息来抵消其数据传输。测试模式从第二设备发送到第一设备。然后，第一个设备检查接收的测试模式，以确定传输是否成功。然后，第一设备可以向第二设备传送额外的时钟偏移消息，以指示第二设备将其数据传输偏移与先前使用的不同的值。第二设备再次发送测试模式，并且第一设备再次检查接收到的模式。通过尝试多个时钟偏移值并确定哪些值导致数据的成功传输，第一设备可以确定最佳时钟偏移值，并且指示第二设备将该值用于所有传输。

4. 发明授权

US06885959B2 Circuit and method for calibrating DRAM pullup Ron to pulldown Ron 失效
标题翻译：用于校准DRAM上拉电路和方法Ron以下拉Ron
公开(公告)号：US06885959B2
公开(公告)日：2005-04-26
申请号：US10282798
申请日：2002-10-29
申请人： Joseph H. Salmon , Hing Y. To
发明人： Joseph H. Salmon , Hing Y. To
IPC分类号： G01R31/317 , G01R35/00 , G11C29/02 , G06F3/05
CPC分类号： G11C29/022 , G01R31/31703 , G01R31/3172 , G01R35/00 , G11C11/401 , G11C29/02 , G11C29/028
摘要： Embodiments of the present invention enable the matching of pull-up and pull-down driver strengths of a slave device (DDRII SDRAM), i.e., the P-channel/N-channel driver pull-up/pull-down Ron and also calibrates the P-channel/N-channel pull-up/pull-down drivers in their linear region of operation. Specifically, embodiments of the present invention may use the DDR-II Off Chip Driver (OCD) protocol for calibration, in addition to using circuit techniques to calibrate the slave driver pull-up Ron within 1 LSB of the pull-down Ron.
摘要翻译：本发明的实施例使得能够匹配从器件（DDRII SDRAM）的上拉和下拉驱动器强度，即P沟道/ N沟道驱动器上拉/下拉Ron，并且还校准 P通道/ N通道上拉/下拉驱动器处于其线性运行区域。具体来说，本发明的实施例除了使用电路技术来校准下拉式Ron的1LSB内的从驱动器上拉Ron外，还可以使用DDR-II片外驱动器（OCD）协议进行校准。

5. 发明授权

US07194559B2 Slave I/O driver calibration using error-nulling master reference 有权
标题翻译：从站I / O驱动器校准使用错误归零主引用
公开(公告)号：US07194559B2
公开(公告)日：2007-03-20
申请号：US10231863
申请日：2002-08-29
申请人： Joseph H. Salmon , Hing Y. To
发明人： Joseph H. Salmon , Hing Y. To
IPC分类号： G06F3/00 , G06F17/50
CPC分类号： G06F13/4072 , G06F13/1689
摘要： Methods and devices for calibrating a driver on a slave device, using a master device driver as a load, are disclosed. A master reference driver is integrated on the same circuit as the master device driver, with both drivers having the same layout and geometry. The master reference driver is calibrated using a selected load impedance that includes the nominal slave device driver impedance and any other impedance elements. The same calibrated driver setting is concurrently applied to both the master driver and the master reference driver, while the slave device drives the master driver. The voltage at the master driver is compared to the voltage at the master reference driver, and the slave device driver impedance is adjusted until those voltages match. The resulting calibration of the slave device driver impedance is largely independent of the actual impedance of the master device driver.
摘要翻译：公开了使用主设备驱动器作为负载来校准从设备上的驱动器的方法和设备。主引导驱动器集成在与主器件驱动程序相同的电路上，两个驱动器具有相同的布局和几何形状。主参考驱动器使用选定的负载阻抗进行校准，该负载阻抗包括标称从器件驱动器阻抗和任何其他阻抗元件。相同的校准驱动程序设置同时应用于主驱动器和主引导驱动器，而从器件驱动主驱动器。将主驱动器处的电压与主参考驱动器上的电压进行比较，并调整从器件驱动器阻抗直到那些电压匹配。所产生的从设备驱动器阻抗的校准在很大程度上与主设备驱动器的实际阻抗无关。

6. 发明授权

US06771515B2 Systems having modules with on die terminations 失效
标题翻译：具有模具终端的模块的系统
公开(公告)号：US06771515B2
公开(公告)日：2004-08-03
申请号：US09970442
申请日：2001-10-04
申请人： James A. McCall , Hing Y. To
发明人： James A. McCall , Hing Y. To
IPC分类号： H05K706
CPC分类号： H05K1/0246 , G11C5/063 , H05K1/117 , H05K1/141 , H05K2201/044 , H05K2201/09254 , H05K2201/10022
摘要： In some embodiments, the invention includes a system having first and second modules and a circuit board including first and second module connectors to receive the first and second modules, respectively. A first path of conductors extends from the circuit board to the first module connector, to the first module, back to the first module connector, to the circuit board, to the second module connector and to the second module. The first path couples to chips of the first and second modules, and each of the chips include on die terminations, but only some of the chips include on die terminations that are enabled.
摘要翻译：在一些实施例中，本发明包括具有第一和第二模块的系统以及包括分别用于接收第一和第二模块的第一和第二模块连接器的电路板。导体的第一路径从电路板延伸到第一模块连接器，第一模块，第一模块连接器，电路板，第二模块连接器和第二模块。第一路径耦合到第一和第二模块的芯片，并且每个芯片包括芯片端子，但是仅一些芯片包括能够启用的芯片端子。

7. 发明授权

US06725390B1 Method and an apparatus for adjusting clock signal to sample data 失效
标题翻译：用于将时钟信号调整为采样数据的方法和装置
公开(公告)号：US06725390B1
公开(公告)日：2004-04-20
申请号：US09608343
申请日：2000-06-29
申请人： Jonathan H. Liu , Hing Y. To
发明人： Jonathan H. Liu , Hing Y. To
IPC分类号： G06F112
CPC分类号： G06F1/10
摘要： The invention includes a method to communicate a data packet. At a second input of a variable delay device, a first clock signal having at least one edge is received. At a first input of a detector, a first data packet having data that defines a second clock signal is received. At a second input of the detector, an output of the variable delay device is received. The output of the variable delay device is then compared to the second clock signal to produce an offset signal. The first clock signal is adjusted as a function of the offset signal to produce an output of the variable delay device.
摘要翻译：本发明包括一种传送数据包的方法。在可变延迟装置的第二输入端，接收具有至少一个边缘的第一时钟信号。在检测器的第一输入端，接收具有定义第二时钟信号的数据的第一数据分组。在检测器的第二输入端处，接收可变延迟装置的输出。然后将可变延迟装置的输出与第二时钟信号进行比较以产生偏移信号。第一时钟信号被调整为偏移信号的函数，以产生可变延迟装置的输出。

8. 发明授权

US06631083B2 Systems with modules and clocking therefore 有权
标题翻译：因此，具有模块和时钟的系统
公开(公告)号：US06631083B2
公开(公告)日：2003-10-07
申请号：US09911756
申请日：2001-07-23
申请人： James A. McCall , Michael W. Leddige , Hing Y. To
发明人： James A. McCall , Michael W. Leddige , Hing Y. To
IPC分类号： G11C502
CPC分类号： G11C5/063 , G06F1/10 , G11C5/04 , H05K1/023 , H05K1/0237 , H05K1/14
摘要： In some embodiments, the invention includes a system having first and second modules; and a circuit board including first and second module connectors to receive the first and second modules, respectively. The system also includes a first clock path of conductors to carry a first clock signal to first, second, third, and fourth chips on the first module and then to first, second, third, and fourth chips on the second module; and a second clock path of conductors to carry a second clock signal to the first, second, third, and fourth chips on the second module and then to the first, second, third, and fourth chips on the first module.
摘要翻译：在一些实施例中，本发明包括具有第一和第二模块的系统; 以及电路板，包括分别接收第一和第二模块的第一和第二模块连接器。该系统还包括导体的第一时钟路径，以将第一时钟信号传送到第一模块上的第一，第二，第三和第四芯片，然后传送到第二模块上的第一，第二，第三和第四芯片; 以及导体的第二时钟路径，以将第二时钟信号传送到第二模块上的第一，第二，第三和第四芯片，然后传送到第一模块上的第一，第二，第三和第四芯片。

9. 发明授权

US07602859B2 Calibrating integrating receivers for source synchronous protocol 有权
标题翻译：校准源同步协议的集成接收器
公开(公告)号：US07602859B2
公开(公告)日：2009-10-13
申请号：US11118228
申请日：2005-04-28
申请人： Roger K. Cheng , Harishankar Sridharan , Navneet Dour , Hing Y. To
发明人： Roger K. Cheng , Harishankar Sridharan , Navneet Dour , Hing Y. To
IPC分类号： H04L27/00
CPC分类号： H04L25/20
摘要： An embodiment of the present invention is a technique to calibrate an integrating receiver. A delay calibration circuit calibrates an adjusting code of a chain of delay elements and positioning of at least an integrating strobe used to define an integration window for the integrating receiver. An integrating receiver pulse generator generates an IR pulse from the at least integrating strobe. A calibration controller controls calibrating the adjusting code and the positioning of the at least integrating strobe.
摘要翻译：本发明的实施例是校准积分接收器的技术。延迟校准电路校准延迟元件链的调整代码，并且至少定位用于为积分接收器定义积分窗口的积分选通脉冲。积分接收器脉冲发生器从至少积分选通器产生IR脉冲。校准控制器控制校准调整代码和至少积分选通脉冲的定位。

10. 发明授权

US07334148B2 Optimization of integrated circuit device I/O bus timing 有权
标题翻译：集成电路设备I / O总线时序优化
公开(公告)号：US07334148B2
公开(公告)日：2008-02-19
申请号：US10761604
申请日：2004-01-20
申请人： Jonathan H. Liu , Hing Y. To
发明人： Jonathan H. Liu , Hing Y. To
IPC分类号： H03M13/00
CPC分类号： G06F1/10
摘要： The invention includes a method to adjust integrated circuit device I/O bus timing. In one embodiment, the method includes comparing an alignment between an edge of a first clock signal to a center of a data packet to produce an alignment offset signal and adjusting the first clock signal using a variable delay device in response to the alignment offset signal to substantially align the edge of the first clock signal to the center of the data packet. Other embodiments are claimed and described.
摘要翻译：本发明包括一种调整集成电路设备I / O总线时序的方法。在一个实施例中，该方法包括比较第一时钟信号的边沿与数据分组的中心之间的对准以产生对准偏移信号，并且响应于对准偏移信号而使用可变延迟装置来调整第一时钟信号将第一时钟信号的边缘基本对齐到数据包的中心。要求保护和描述其它实施例。

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