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1. 发明授权

US06421801B1 Testing IO timing in a delay locked system using separate transmit and receive loops 有权
标题翻译：使用单独的发送和接收循环来测试延迟锁定系统中的IO时序
公开(公告)号：US06421801B1
公开(公告)日：2002-07-16
申请号：US09327942
申请日：1999-06-08
申请人： John T. Maddux , Joseph H. Salmon
发明人： John T. Maddux , Joseph H. Salmon
IPC分类号： G06F1100
CPC分类号： G01R31/319
摘要： A method and apparatus for testing an input data path of an integrated circuit. Dual transmit and receive delay locked loops (DLLs) provide clocks for test mode data transmit and receive. Test mode logic drives a data pattern into an input receiver with the data pattern clocked by the transmit DLL and the input receiver clock by the receive DLL. The output of the input receiver is compared with the data pattern. The transmit DLL is adjusted relative to the receive DLL to measure setup and hold times of the data pattern driven through the input receiver.
摘要翻译：一种用于测试集成电路的输入数据路径的方法和装置。双发送和接收延迟锁定环（DLL）为测试模式数据发送和接收提供时钟。测试模式逻辑将数据模式驱动到具有由发送DLL定时的数据模式和由接收DLL输入的接收器时钟的输入接收器中。将输入接收机的输出与数据模式进行比较。发送DLL相对于接收DLL进行调整，以测量通过输入接收器驱动的数据模式的建立和保持时间。

2. 发明授权

US06381722B1 Method and apparatus for testing high speed input paths 失效
标题翻译：用于测试高速输入路径的方法和装置
公开(公告)号：US06381722B1
公开(公告)日：2002-04-30
申请号：US09327943
申请日：1999-06-08
申请人： Joseph H. Salmon , John T. Maddux
发明人： Joseph H. Salmon , John T. Maddux
IPC分类号： G01R3130
CPC分类号： G01R31/3016
摘要： A method and circuit to test for defects in the input path of an integrated circuit by providing a logic pattern data to a scan chain of the integrated circuit and testing setup and hold timing parameters. The method including determining a maximum value for a timing parameter and generating a data pattern with the timing parameter having the maximum value. The method also including monitoring an output of a logic function performed on the data pattern and adjusting the value of the timing parameter based on the output of the logic function.
摘要翻译：一种用于通过向集成电路的扫描链提供逻辑图案数据并测试建立和保持定时参数来测试集成电路的输入路径中的缺陷的方法和电路。该方法包括确定定时参数的最大值并且产生具有最大值的定时参数的数据模式。该方法还包括监视对数据模式执行的逻辑功能的输出，并且基于逻辑功能的输出来调整定时参数的值。

3. 发明授权

US06864726B2 Output signal control from a DAC-driven amplifier-based driver 有权
标题翻译：来自DAC驱动的基于放大器的驱动器的输出信号控制
公开(公告)号：US06864726B2
公开(公告)日：2005-03-08
申请号：US10464232
申请日：2003-06-17
申请人： Alexander Levin , Surya N. Koneru , John T. Maddux
发明人： Alexander Levin , Surya N. Koneru , John T. Maddux
IPC分类号： H03F3/72 , H03K17/16 , H03B1/00
CPC分类号： H03F3/72 , H03K17/165
摘要： An apparatus and a method to control an output signal from a DAC-driven amplifier-based driver are disclosed. The apparatus includes an amplifier and a driver. The amplifier has a negative input terminal, a positive input terminal, and a first output terminal. The driver has an input terminal and a second output terminal, the input terminal coupled to the first output terminal of the amplifier and the second output terminal coupled to the positive input terminal of the amplifier to provide a positive feedback to the amplifier. In another embodiment, the apparatus includes a first driver to drive an output signal, the first driver having a first input terminal and a first output terminal, a second driver to generate a feedback, the second driver having a second input terminal and a second output terminal, and an amplifier having a third input terminal to receive an input signal, a fourth input terminal, and a third output terminal, the third output terminal coupled to the first input terminal of the first driver and the second input terminal of the second driver, the fourth input terminal coupled to the second output terminal of the second driver.
摘要翻译：公开了一种用于控制来自DAC驱动的基于放大器的驱动器的输出信号的装置和方法。该装置包括放大器和驱动器。放大器具有负输入端子，正输入端子和第一输出端子。驱动器具有输入端子和第二输出端子，输入端子耦合到放大器的第一输出端子，第二输出端子耦合到放大器的正输入端子，以向放大器提供正反馈。在另一实施例中，该装置包括驱动输出信号的第一驱动器，第一驱动器具有第一输入端和第一输出端，产生反馈的第二驱动器，第二驱动器具有第二输入端和第二输出以及具有用于接收输入信号的第三输入端子的放大器，第四输入端子和第三输出端子，所述第三输出端子耦合到所述第一驱动器的第一输入端子和所述第二驱动器的第二输入端子，第四输入端耦合到第二驱动器的第二输出端。

4. 发明授权

US06580305B1 Generating a clock signal 有权
标题翻译：产生时钟信号
公开(公告)号：US06580305B1
公开(公告)日：2003-06-17
申请号：US09474652
申请日：1999-12-29
申请人： Jonathan H. Liu , John T. Maddux
发明人： Jonathan H. Liu , John T. Maddux
IPC分类号： G06F104
CPC分类号： G06F1/04
摘要： An apparatus which generates a clock signal includes a first phase mixer which generates an initial clock signal based on a first set of reference clocks and a buffer which adds a first predetermined delay to the initial clock signal to produce a first clock signal. A phase detection circuit detects a difference in phase between the first clock signal and a master clock signal, and a control circuit selects a second set of reference clocks based on the difference in phase and a second predetermined delay. A second phase mixer generates an output clock signal based on the second set of reference clocks.
摘要翻译：产生时钟信号的装置包括：第一相位混频器，其基于第一组参考时钟产生初始时钟信号;以及缓冲器，其将第一预定延迟与初始时钟信号相加以产生第一时钟信号。相位检测电路检测第一时钟信号和主时钟信号之间的相位差，并且控制电路基于相位差和第二预定延迟选择第二组参考时钟。第二相混频器基于第二组参考时钟产生输出时钟信号。

5. 发明授权

US07349507B2 Extending PPM tolerance using a tracking data recovery algorithm in a data recovery circuit 有权
标题翻译：在数据恢复电路中使用跟踪数据恢复算法来扩展PPM容限
公开(公告)号：US07349507B2
公开(公告)日：2008-03-25
申请号：US10458030
申请日：2003-06-09
申请人： John T. Maddux
发明人： John T. Maddux
IPC分类号： H04L7/00
CPC分类号： H04L7/0331 , H03L7/0814 , H03L7/091 , H03L7/093 , H04L7/0025
摘要： A circuit comprising a sampling logic to sample an incoming signal. A phase detection logic to determine a phase error associated with the sample of the incoming signal and to output an out-of-phase detection signal based on the phase error. A control logic coupled to the phase detection logic to output a periodic error signal at a periodic rate. A phase adjustment logic to adjust the phase of the sampling logic based on the out-of-phase detection signal and the periodic error signal.
摘要翻译：一种电路，包括用于对输入信号进行采样的采样逻辑。相位检测逻辑，用于确定与输入信号的采样相关联的相位误差，并且基于相位误差输出异相检测信号。耦合到相位检测逻辑的控制逻辑以周期性速率输出周期性误差信号。相位调整逻辑，用于基于异相检测信号和周期性误差信号来调整采样逻辑的相位。

6. 发明授权

US06631338B2 Dynamic current calibrated driver circuit 有权
公开(公告)号：US06631338B2
公开(公告)日：2003-10-07
申请号：US09752258
申请日：2000-12-29
申请人： Hing “Thomas” Y. To , John T. Maddux , Jonathan H. Liu
发明人： Hing “Thomas” Y. To , John T. Maddux , Jonathan H. Liu
IPC分类号： G06F1900
CPC分类号： H03K19/018585
摘要： A local driver circuit to drive a logic voltage at an output pad includes an adder having K bits to add a K-bit control value to a local value, the adder producing a K-bit calibrated value. The circuit further includes K field-effect transistors (FETs), the drain of each FET being coupled to the output pad, and logic circuitry to perform a logical-AND function between a data input and the K-bit calibrated value. The logic circuitry providing a K-bit output with each of the K output bits being coupled to the gate of a corresponding one of the FETs. A comparator produces a correction value from a comparison of the logic voltage at the output pad and a reference voltage. A control unit sets a least significant bit (LSB) portion of the local value responsive to the correction value so as to make the logic voltage at the output pad in the reference voltage substantially equal.

7. 发明授权

US06529148B1 Apparatus and method for acquisition of an incoming data stream 失效
标题翻译：用于获取输入数据流的装置和方法
公开(公告)号：US06529148B1
公开(公告)日：2003-03-04
申请号：US10095589
申请日：2002-03-11
申请人： John T. Maddux
发明人： John T. Maddux
IPC分类号： H03M900
CPC分类号： H04L7/0338 , H04L7/0004 , H04L7/10
摘要： In general, one embodiment of the invention involves an apparatus that comprises a fast acquisition logic coupled to an oversampler. The fast acquisition logic is configured to detect whether any of a plurality of data samples produced by the oversampler is inaccurate, and if so, to cause data to be recovered from a new data sample different from the data sample previously being used for data recovery. The new data sample would be multiple sampling states away from the previous data sample.
摘要翻译：通常，本发明的一个实施例涉及一种装置，其包括耦合到过采样器的快速采集逻辑。快速采集逻辑被配置为检测由过采样器产生的多个数据样本中的任一个是否不准确，如果是，则使数据从与先前用于数据恢复的数据样本不同的新数据样本恢复。新的数据样本将是与先前数据样本相比的多个采样状态。

8. 发明授权

US06947859B2 Dynamic current calibrated driver circuit 失效
标题翻译：动态电流校准驱动电路
公开(公告)号：US06947859B2
公开(公告)日：2005-09-20
申请号：US10623396
申请日：2003-07-18
申请人： Hing “Thomas” Y. To , John T. Maddux , Jonathan H. Liu
发明人： Hing “Thomas” Y. To , John T. Maddux , Jonathan H. Liu
IPC分类号： H03K19/003 , H03K19/0185
CPC分类号： H03K19/018585
摘要： A method to calibrate I/O cell current has been described. The method includes setting a global control value provided to the I/O cells. Then, for each I/O cell, the method includes comparing the logic voltage at the output pad of the I/O cell with a reference voltage, and sinking more current at the output pad by enabling additional driver bits associated with the I/O cell if the logic voltage is higher than the reference voltage, or sinking less current at the output pad by disabling additional driver bits associated with the I/O cell if the logic voltage is lower than the reference voltage.
摘要翻译：已经描述了校准I / O电池电流的方法。该方法包括设置提供给I / O单元的全局控制值。然后，对于每个I / O单元，该方法包括将I / O单元的输出焊盘处的逻辑电压与参考电压进行比较，并通过启用与I / O相关联的附加驱动器位在输出焊盘上吸收更多电流如果逻辑电压高于参考电压，或者如果逻辑电压低于参考电压，则通过禁用与I / O单元相关联的附加驱动器位来吸收输出焊盘上的较小电流。

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