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1. 发明申请

US20110320867A1 METHOD AND APPARATUS FOR TRAINING A MEMORY SIGNAL VIA AN ERROR SIGNAL OF A MEMORY 有权
标题翻译：用于通过存储器的错误信号训练存储信号的方法和装置
公开(公告)号：US20110320867A1
公开(公告)日：2011-12-29
申请号：US12824675
申请日：2010-06-28
申请人： Santanu Chaudhuri , Joseph H. Salmon , Kuljit S. Bains
发明人： Santanu Chaudhuri , Joseph H. Salmon , Kuljit S. Bains
IPC分类号： G06F11/07
CPC分类号： G06F11/0793 , G06F11/073 , G06F13/1689 , G11C2207/2254
摘要： Described herein is a method and an apparatus for training a memory signal via an error signal of a memory. The method comprises transmitting from a memory controller a command-address (C/A) signal to a memory module; determining by the memory controller an error in the memory module via an error signal from an error pin of the memory module, the error associated with the C/A signal transmitted to the memory module; and modifying by the memory controller the C/A signal in response to determining an error in the memory module, wherein the error pin is a parity error pin of the memory module, and wherein the memory module comprises a Double Data Rate 4 (DDR4) interface.
摘要翻译：这里描述了一种通过存储器的误差信号来训练存储器信号的方法和装置。该方法包括从存储器控制器向存储器模块发送命令地址（C / A）信号; 由存储器控制器通过来自存储器模块的错误引脚的错误信号确定存储器模块中的错误，该错误与传送到存储器模块的C / A信号相关联; 以及响应于确定所述存储器模块中的错误，由所述存储器控制器修改所述C / A信号，其中所述错误引脚是所述存储器模块的奇偶校验错误引脚，并且其中所述存储器模块包括双倍数据速率4（DDR4）接口。

2. 发明授权

US08533538B2 Method and apparatus for training a memory signal via an error signal of a memory 有权
标题翻译：用于通过存储器的误差信号训练存储器信号的方法和装置
公开(公告)号：US08533538B2
公开(公告)日：2013-09-10
申请号：US12824675
申请日：2010-06-28
申请人： Santanu Chaudhuri , Joseph H. Salmon , Kuljit S. Bains
发明人： Santanu Chaudhuri , Joseph H. Salmon , Kuljit S. Bains
IPC分类号： G06F11/00
CPC分类号： G06F11/0793 , G06F11/073 , G06F13/1689 , G11C2207/2254
摘要： Described herein is a method and an apparatus for training a memory signal via an error signal of a memory. The method comprises transmitting from a memory controller a command-address (C/A) signal to a memory module; determining by the memory controller an error in the memory module via an error signal from an error pin of the memory module, the error associated with the C/A signal transmitted to the memory module; and modifying by the memory controller the C/A signal in response to determining an error in the memory module, wherein the error pin is a parity error pin of the memory module, and wherein the memory module comprises a Double Data Rate 4 (DDR4) interface.
摘要翻译：这里描述了一种通过存储器的误差信号来训练存储器信号的方法和装置。该方法包括从存储器控制器向存储器模块发送命令地址（C / A）信号; 由存储器控制器通过来自存储器模块的错误引脚的错误信号确定存储器模块中的错误，该错误与传送到存储器模块的C / A信号相关联; 以及响应于确定所述存储器模块中的错误，由所述存储器控制器修改所述C / A信号，其中所述错误引脚是所述存储器模块的奇偶校验错误引脚，并且其中所述存储器模块包括双倍数据速率4（DDR4）接口。

3. 发明授权

US08595428B2 Memory controller functionalities to support data swizzling 有权
标题翻译：内存控制器功能支持数据转换
公开(公告)号：US08595428B2
公开(公告)日：2013-11-26
申请号：US12644803
申请日：2009-12-22
申请人： Kuljit S. Bains , Joseph H. Salmon
发明人： Kuljit S. Bains , Joseph H. Salmon
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G06F13/1678
摘要： A memory controller that can determine a swizzling pattern between the memory controller and memory devices. The memory controller generates a swizzling map based on the determined swizzling pattern. The memory controller may internally swizzle data using the swizzling map before writing the data to memory so that the data appears in the correct order at the pins of the memory chip(s). On reads, the controller can internally de-swizzle the data before performing the error correction operations using the swizzling map.
摘要翻译：可以确定存储器控制器和存储器件之间的旋转模式的存储器控制器。存储器控制器基于确定的旋转模式产生旋转图。在将数据写入存储器之前，存储器控制器可以使用转动图来内部转换数据，使得数据以存储器芯片的引脚上的正确顺序出现。在读取时，控制器可以在执行使用旋转映射的纠错操作之前对数据进行内部转换。

4. 发明授权

US08392796B2 Reliability, availability, and serviceability solution for memory technology 有权
标题翻译：内存技术的可靠性，可用性和可维护性解决方案
公开(公告)号：US08392796B2
公开(公告)日：2013-03-05
申请号：US13361769
申请日：2012-01-30
申请人： Kuljit S. Bains , Joseph H. Salmon
发明人： Kuljit S. Bains , Joseph H. Salmon
IPC分类号： H03M13/00
CPC分类号： G06F11/1004
摘要： Embodiments of the invention are generally directed to systems, methods, and apparatuses for reliability, availability, and serviceability solutions for memory technology. In some embodiments, a host determines the configuration of the memory subsystem during initialization. The host selects a write cyclic redundancy code (CRC) mechanism and a read CRC mechanism based, at least in part, on the configuration of the memory subsystem. Other embodiments are described and claimed.
摘要翻译：本发明的实施例通常涉及用于存储器技术的可靠性，可用性和可服务性解决方案的系统，方法和装置。在一些实施例中，主机在初始化期间确定存储器子系统的配置。主机至少部分地基于存储器子系统的配置来选择写入循环冗余码（CRC）机制和读取CRC机制。描述和要求保护其他实施例。

5. 发明授权

US08132074B2 Reliability, availability, and serviceability solutions for memory technology 有权
标题翻译：内存技术的可靠性，可用性和可维护性解决方案
公开(公告)号：US08132074B2
公开(公告)日：2012-03-06
申请号：US11942621
申请日：2007-11-19
申请人： Kuljit S. Bains , Joseph H. Salmon
发明人： Kuljit S. Bains , Joseph H. Salmon
IPC分类号： H03M13/00
CPC分类号： G06F11/1004
摘要： Embodiments of the invention are generally directed to systems, methods, and apparatuses for reliability, availability, and serviceability solutions for memory technology. In some embodiments, a host determines the configuration of the memory subsystem during initialization. The host selects a write cyclic redundancy code (CRC) mechanism and a read CRC mechanism based, at least in part, on the configuration of the memory subsystem. Other embodiments are described and claimed.
摘要翻译：本发明的实施例通常涉及用于存储器技术的可靠性，可用性和可服务性解决方案的系统，方法和装置。在一些实施例中，主机在初始化期间确定存储器子系统的配置。主机至少部分地基于存储器子系统的配置来选择写入循环冗余码（CRC）机制和读取CRC机制。描述和要求保护其他实施例。

6. 发明授权

US09442871B2 Accessing data stored in a command/address register device 有权
标题翻译：访问存储在命令/地址寄存器中的数据
公开(公告)号：US09442871B2
公开(公告)日：2016-09-13
申请号：US13995477
申请日：2011-12-22
申请人： Kuljit S. Bains , Klaus J. Ruff , George Vergis , Suneeta Sah
发明人： Kuljit S. Bains , Klaus J. Ruff , George Vergis , Suneeta Sah
IPC分类号： G06F13/28 , G06F11/10 , G06F11/16 , G11C29/44 , G06F13/16
CPC分类号： G11C7/1072 , G06F11/073 , G06F11/0787 , G06F11/10 , G06F11/1004 , G06F11/1016 , G06F11/1612 , G06F13/16 , G06F13/28 , G11C7/1006 , G11C29/44 , G11C2029/0411 , G11C2029/4402
摘要： A register not connected to a data bus is read by transferring data across an address bus to a device connected to the data bus, from which the data is read by a device connected to the data bus. The register resides in a register device connected via the address bus to a memory device that is connected to both the address bus and the data bus. A host processor triggers the register device to transfer information over the address bus to a register on the memory device. The host processor then reads the information from the register of the memory device.
摘要翻译：通过将地址总线上的数据传送到连接到数据总线的设备，可以读取未连接到数据总线的寄存器，数据由连接到数据总线的设备读取。寄存器位于通过地址总线连接到连接到地址总线和数据总线两者的存储器件的寄存器中。主处理器触发寄存器设备通过地址总线将信息传送到存储器设备上的寄存器。然后主机处理器从存储器件的寄存器读取信息。

7. 发明申请

US20160093344A1 METHOD, APPARATUS AND SYSTEM TO MANAGE IMPLICIT PRE-CHARGE COMMAND SIGNALING 有权
标题翻译：方法，装置和系统来管理隐式预充电指令信号
公开(公告)号：US20160093344A1
公开(公告)日：2016-03-31
申请号：US14498509
申请日：2014-09-26
申请人： John B. Halbert , Bruce A. Christenson , Kuljit S. Bains
发明人： John B. Halbert , Bruce A. Christenson , Kuljit S. Bains
IPC分类号： G11C7/10
CPC分类号： G11C7/1072 , G06F13/1668 , G06F13/1689 , G06F21/79 , G11C7/1045 , G11C7/1048 , G11C7/1063 , G11C7/109 , G11C11/4076 , G11C11/4093 , G11C11/4094 , Y02D10/14
摘要： Techniques and mechanisms for exchanging information between a memory controller and a memory device. In an embodiment, a memory controller receives information indicating for a memory device a threshold number of pending consolidated activation commands to access that memory device. The threshold number indicated by the information is less than a theoretical maximum number of pending consolidated activation commands, the theoretical maximum number defined based on timing parameters of the memory device. In another embodiment, the memory controller limits communication of consolidated activation commands to the memory device based on the information indicating the threshold number.
摘要翻译：用于在存储器控制器和存储器件之间交换信息的技术和机制。在一个实施例中，存储器控制器接收指示存储器设备访问该存储器设备的临时统一激活命令的阈值数量的信息。由信息指示的阈值数小于待处理的合并激活命令的理论最大数量，基于存储器件的定时参数定义的理论最大数量。在另一个实施例中，存储器控制器基于指示阈值数量的信息来限制合并的激活命令到存储器设备的通信。

8. 发明授权

US09053812B2 Fast exit from DRAM self-refresh 有权
标题翻译：快速退出DRAM自刷新
公开(公告)号：US09053812B2
公开(公告)日：2015-06-09
申请号：US13533476
申请日：2012-06-26
申请人： Kuljit S. Bains
发明人： Kuljit S. Bains
IPC分类号： G06F12/00 , G11C11/406
CPC分类号： G11C11/40615 , G11C11/4076 , G11C2211/4067
摘要： Embodiments of the invention describe a dynamic random access memory (DRAM) device that may abort a self-refresh mode to improve the exit time from a DRAM low power state of self-refresh. During execution of a self-refresh mode, the DRAM device may receive a signal (e.g., a device enable signal) from a memory controller operatively coupled to the DRAM device. The DRAM device may abort the self-refresh mode in response to receiving the signal from the memory controller.
摘要翻译：本发明的实施例描述了一种动态随机存取存储器（DRAM）装置，其可以中止自刷新模式以改善从自动刷新的DRAM低功率状态的退出时间。在执行自刷新模式期间，DRAM设备可以从可操作地耦合到DRAM设备的存储器控制器接收信号（例如，器件使能信号）。响应于接收到来自存储器控制器的信号，DRAM设备可以中止自刷新模式。

9. 发明授权

US08938573B2 Row hammer condition monitoring 有权
标题翻译：行锤状态监测
公开(公告)号：US08938573B2
公开(公告)日：2015-01-20
申请号：US13539417
申请日：2012-06-30
申请人： Zvika Greenfield , Kuljit S. Bains , Theodore Z. Schoenborn , Christopher P. Mozak , John B. Halbert
发明人： Zvika Greenfield , Kuljit S. Bains , Theodore Z. Schoenborn , Christopher P. Mozak , John B. Halbert
IPC分类号： G06F12/06 , G11C11/406 , G06F11/30
CPC分类号： G06F11/3037 , G06F11/004 , G06F11/3471 , G06F2201/81 , G06F2201/88 , G11C11/40611 , G11C11/40618 , G11C11/40622
摘要： A system monitors data accesses to specific rows of memory to determine if a row hammer condition exists. The system can monitor accessed rows of memory to determine if the number of accesses to any of the rows exceeds a threshold associated with risk of data corruption on a row of memory physically adjacent to the row with high access. Based on the monitoring, a memory controller can determine if the number of accesses to a row exceeds the threshold, and indicate address information for the row whose access count reaches the threshold.
摘要翻译：系统监视对特定行存储器的数据访问，以确定是否存在行锤条件。该系统可以监视所访问的存储行，以确定对任何行的访问次数是否超过与物理上与高访问行相邻的存储体上的数据损坏风险相关联的阈值。基于监视，存储器控制器可以确定对行的访问次数是否超过阈值，并且指示访问计数达到阈值的行的地址信息。

10. 发明授权

US08806298B2 Reliability, availability, and serviceability in a memory device 有权
标题翻译：内存设备的可靠性，可用性和可维护性
公开(公告)号：US08806298B2
公开(公告)日：2014-08-12
申请号：US12824298
申请日：2010-06-28
申请人： Kuljit S. Bains
发明人： Kuljit S. Bains
IPC分类号： H03M13/00
CPC分类号： G06F11/1008
摘要： Embodiments of the invention are generally directed to improving the reliability, availability, and serviceability of a memory device. In some embodiments, a memory device includes a memory core having a first portion to store data bits and a second portion to store error correction code (ECC) bits corresponding to the data bits. The memory device may also include error correction logic on the same die as the memory core. In some embodiments, the error correction logic enables the memory device to compute ECC bits and to compare the stored ECC bits with the computed ECC bits.
摘要翻译：本发明的实施例一般涉及提高存储器件的可靠性，可用性和可服务性。在一些实施例中，存储器设备包括具有存储数据位的第一部分的存储器核心和存储对应于数据位的纠错码（ECC）位的第二部分。存储器件还可以包括与存储器核心相同的管芯上的纠错逻辑。在一些实施例中，纠错逻辑使得存储器设备能够计算ECC比特并将所存储的ECC比特与所计算的ECC比特进行比较。

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