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1. 发明授权

US07081393B2 Reduced dielectric constant spacer materials integration for high speed logic gates 失效
标题翻译：降低介电常数间隔材料集成用于高速逻辑门
公开(公告)号：US07081393B2
公开(公告)日：2006-07-25
申请号：US10709652
申请日：2004-05-20
申请人： Michael P. Belyansky , Joyce C. Liu , Hsing Jen Wann , Richard Stephen Wise , Hongwen Yan
发明人： Michael P. Belyansky , Joyce C. Liu , Hsing Jen Wann , Richard Stephen Wise , Hongwen Yan
IPC分类号： H01L21/336
CPC分类号： H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： An FET transistor has a gate disposed between a source and a drain; a gate dielectric layer disposed underneath the gate; and a spacer on a side of the gate. The gate dielectric layer is conventional oxide and the spacer has a reduced dielectric constant (k). The reduced dielectric constant (k) may be less than 3.85, or it may be less than 7.0 (˜nitride), but greater than 3.85 (˜oxide). Preferably, the spacer comprises a material which can be etched selectively to the gate dielectric layer. The spacer may be porous, and a thin layer is deposited on the porous spacer to prevent moisture absorption. The spacer may comprise a material selected from the group consisting of Black Diamond, Coral, TERA and Blok type materials. Pores may be formed in the spacer material by exposing the spacers to an oxygen plasma.
摘要翻译： FET晶体管具有设置在源极和漏极之间的栅极; 设置在栅极下方的栅介质层; 和在门侧的间隔物。栅极电介质层是常规的氧化物，间隔物具有降低的介电常数（k）。降低的介电常数（k）可以小于3.85，或者可以小于7.0（〜氮化物），但大于3.85（〜氧化物）。优选地，间隔物包括可以选择性地蚀刻到栅极介电层的材料。间隔物可以是多孔的，并且在多孔间隔物上沉积薄层以防止吸湿。间隔物可以包括选自黑钻石，珊瑚，TERA和Blok型材料的材料。可以通过将间隔物暴露于氧等离子体来在间隔物材料中形成孔。

2. 发明申请

US20080194112A1 METHOD AND SYSTEM FOR PLASMA ETCHING HAVING IMPROVED ACROSS-WAFER ETCH UNIFORMITY 审中-公开
标题翻译：等离子体蚀刻的方法和系统具有改进的跨越蚀刻均匀性
公开(公告)号：US20080194112A1
公开(公告)日：2008-08-14
申请号：US11673128
申请日：2007-02-09
申请人： Qingyun Yang , Joyce C. Liu , Hongwen Yan , Ying Zhang
发明人： Qingyun Yang , Joyce C. Liu , Hongwen Yan , Ying Zhang
IPC分类号： H01L21/3065
CPC分类号： H01L21/32136 , H01L21/32137 , H01L21/6708
摘要： A method for improving across-wafer etch uniformity of semiconductor devices in an etching chamber, wherein the method includes: introducing a first flow of gas mixtures from a central gas distribution plate manifold; introducing a second flow of gas mixtures from an auxiliary gas feed; and controlling process parameters including one or more of: duration, power, pressure, and gas flow rates for the first and second flow of gas mixtures; wherein the central gas distribution plate manifold is positioned above the semiconductor wafer; wherein the auxiliary gas feed is positioned around the perimeter of the semiconductor wafer; and wherein the controlling of the process parameters of the central gas distribution plate manifold and the auxiliary gas feed is facilitated by independent controls.
摘要翻译：一种用于改善蚀刻室中的半导体器件的跨晶片蚀刻均匀性的方法，其中所述方法包括：从中央气体分配板歧管引入第一气体混合物流; 从辅助气体进料引入第二气体混合物流; 以及控制过程参数，包括以下一个或多个：气体混合物的第一和第二流动的持续时间，功率，压力和气体流速; 其中所述中央气体分配板歧管位于所述半导体晶片的上方; 其中所述辅助气体进料围绕所述半导体晶片的周边定位; 并且其中通过独立控制来促进对中央气体分配板歧管和辅助气体进料的工艺参数的控制。

3. 发明申请

US20080182372A1 METHOD OF FORMING DISPOSABLE SPACERS FOR IMPROVED STRESSED NITRIDE FILM EFFECTIVENESS 审中-公开
标题翻译：形成改善间隔物的方法，用于改善耐压氮化膜的有效性
公开(公告)号：US20080182372A1
公开(公告)日：2008-07-31
申请号：US11669645
申请日：2007-01-31
申请人： Joyce C. Liu , Hongwen Yan , Qingyun Yang , Ying Zhang
发明人： Joyce C. Liu , Hongwen Yan , Qingyun Yang , Ying Zhang
IPC分类号： H01L21/8238
CPC分类号： H01L29/6653 , H01L21/3146 , H01L21/823864 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/7843
摘要： A method of forming a complementary metal oxide semiconductor (CMOS) device includes forming an oxide layer on sidewalls and a top surface of a patterned gate conductor, and on sidewalls of a gate insulating layer formed on a semiconductor substrate; forming a first carbon-based layer over the gate conductor, gate insulating layer, and substrate; etching the first carbon-based layer so as to create a first set of carbon spacers; forming a second carbon-based layer over the gate conductor, gate insulating layer, substrate, and first set of carbon spacers; etching the second carbon-based layer so as to create a second set of carbon spacers; forming silicide contacts on the gate conductor, and on source and drain regions formed in the substrate; removing the first and second sets of carbon spacers; and forming a stress-inducing nitride layer over the substrate, silicide contacts, gate conductor, and gate insulating layer.
摘要翻译：形成互补金属氧化物半导体（CMOS）器件的方法包括在图案化栅极导体的侧壁和顶表面上以及形成在半导体衬底上的栅极绝缘层的侧壁上形成氧化物层; 在栅极导体，栅极绝缘层和衬底上形成第一碳基层; 蚀刻第一碳基层以产生第一组碳间隔物; 在栅极导体，栅极绝缘层，衬底和第一组碳隔离物上形成第二碳基层; 蚀刻第二碳基层以产生第二组碳间隔物; 在栅极导体上形成硅化物触点，以及在衬底中形成的源极和漏极区上; 去除第一和第二组碳间隔物; 以及在衬底上形成应力诱导氮化物层，硅化物接触，栅极导体和栅极绝缘层。

4. 发明授权

US06838347B1 Method for reducing line edge roughness of oxide material using chemical oxide removal 失效
标题翻译：使用化学氧化物去除减少氧化物材料的线边缘粗糙度的方法
公开(公告)号：US06838347B1
公开(公告)日：2005-01-04
申请号：US10605331
申请日：2003-09-23
申请人： Joyce C. Liu , Wesley C. Natzle , Richard S. Wise , Hongwen Yan , Bidan Zhang
发明人： Joyce C. Liu , Wesley C. Natzle , Richard S. Wise , Hongwen Yan , Bidan Zhang
IPC分类号： H01L21/311 , H01L21/3205 , H01L21/3213 , H01L21/336 , H01L21/4763
CPC分类号： H01L21/32139 , H01L21/31116
摘要： A method for reducing line edge roughness (LER) of a semiconductor gate structure includes patterning a photoresist layer formed over an oxide hardmask layer. The photoresist layer is etched so as to transfer a photoresist pattern to the oxide hardmask layer, the photoresist pattern having an initial LER. The exposed surfaces of the oxide hardmask are etched with a chemical oxide removal (COR) so as to form a reaction product on the exposed surfaces, wherein concave portions of the exposed surfaces are etched at a reduced rate with respect to convex portions of the exposed surfaces.

5. 发明申请

US20090104776A1 METHODS FOR FORMING NESTED AND ISOLATED LINES IN SEMICONDUCTOR DEVICES 审中-公开
标题翻译：在半导体器件中形成嵌套和隔离线的方法
公开(公告)号：US20090104776A1
公开(公告)日：2009-04-23
申请号：US11874392
申请日：2007-10-18
申请人： David M. Dobuzinsky , Johnathan E. Faltermeier , Naoyoshi Kusaba , Joyce C. Liu , Munir D. Naeem , Siddhartha Panda , Richard S. Wise , Hongwen Yan
发明人： David M. Dobuzinsky , Johnathan E. Faltermeier , Naoyoshi Kusaba , Joyce C. Liu , Munir D. Naeem , Siddhartha Panda , Richard S. Wise , Hongwen Yan
IPC分类号： H01L21/4763
CPC分类号： H01L21/76838 , H01L21/0337 , H01L21/0338 , H01L21/32137 , H01L21/32139
摘要： A method for forming lines for semiconductor devices including, depositing a shallow trench isolation (STI) film stack on a silicon substrate, depositing a layer of polysilicon on the STI film stack, depositing a layer of antireflective coating on the layer of polysilicon, developing a phototoresist on the antireflective coating, wherein the photoresist defines a line, etching the layer of antireflective coating and the layer of polysilicon using RIE with a low bias power, removing the photoresist, removing the layer of antireflective coating, etching the STI film stack to form the line, wherein the layer of polysilicon further defines the line.
摘要翻译：一种用于形成用于半导体器件的线的方法，包括：在硅衬底上沉积浅沟槽隔离（STI）膜堆叠，在所述STI膜堆叠上沉积多晶硅层，在所述多晶硅层上沉积一层抗反射涂层，在抗反射涂层上光致抗蚀剂，其中光致抗蚀剂限定线，使用具有低偏压功率的RIE蚀刻抗反射涂层和多晶硅层，去除光致抗蚀剂，去除抗反射涂层，蚀刻STI膜叠层以形成所述线，其中所述多晶硅层进一步限定所述线。

6. 发明授权

US06518151B1 Dual layer hard mask for eDRAM gate etch process 失效
标题翻译：双层硬掩模，用于eDRAM门蚀刻工艺
公开(公告)号：US06518151B1
公开(公告)日：2003-02-11
申请号：US09924118
申请日：2001-08-07
申请人： David Mark Dobuzinsky , Babar Ali Khan , Joyce C. Liu , Paul R. Wensley , Chienfan Yu
发明人： David Mark Dobuzinsky , Babar Ali Khan , Joyce C. Liu , Paul R. Wensley , Chienfan Yu
IPC分类号： H01L2122
CPC分类号： H01L27/10894 , H01L21/32139 , H01L21/76897 , H01L21/823437 , H01L21/823475 , H01L27/10873
摘要： A method of fabricating an integrated circuit chip having a first region of a first layout rule and a second region of a second layout rule. The method includes using a first material to establish a first hard mask pattern in only the first region and using a second material to establish a second hard mask pattern on top of the first hard mask pattern. The second material is additionally used to establish a third hard mask pattern in the second region.
摘要翻译：一种制造集成电路芯片的方法，该集成电路芯片具有第一布局规则的第一区域和第二布局规则的第二区域。该方法包括使用第一材料仅在第一区域中建立第一硬掩模图案，并且使用第二材料在第一硬掩模图案的顶部上建立第二硬掩模图案。第二材料另外用于在第二区域中建立第三硬掩模图案。

7. 发明申请

US20100038751A1 STRUCTURE AND METHOD FOR MANUFACTURING TRENCH CAPACITANCE 有权
标题翻译：用于制造TRENCH电容的结构和方法
公开(公告)号：US20100038751A1
公开(公告)日：2010-02-18
申请号：US12191430
申请日：2008-08-14
申请人： HUILONG ZHU , Babar A. Khan , Xi Li , Joyce C. Liu , Thomas A. Wallner
发明人： HUILONG ZHU , Babar A. Khan , Xi Li , Joyce C. Liu , Thomas A. Wallner
IPC分类号： H01L29/00 , H01L21/20
CPC分类号： H01L29/66181 , H01L27/10861
摘要： A deep trench (DT) capacitor comprises a trench in a silicon layer, a buried plate surrounding the trench, a dielectric layer lining the trench, and a node conductor in the trench. The top surface of the poly node is higher than the surface of the silicon layer, so that it is high enough to ensure that a nitride liner used as a CMP etch stop for STI oxide surrounding a top portion of the poly node will be higher than the STI oxide, so that the nitride liner can be removed prior to forming a silicide contact on top of the poly node.
摘要翻译：深沟槽（DT）电容器包括硅层中的沟槽，围绕沟槽的掩埋板，衬套沟槽的电介质层和沟槽中的节点导体。多晶硅节点的顶表面高于硅层的表面，使得其足够高以确保用作CMP蚀刻的氮化物衬垫停止用于围绕多晶硅节点的顶部的STI氧化物将高于 STI氧化物，使得氮化物衬垫可以在在多晶硅节点的顶部形成硅化物接触之前被去除。

8. 发明授权

US06821890B2 Method for improving adhesion to copper 有权
标题翻译：提高与铜的附着力的方法
公开(公告)号：US06821890B2
公开(公告)日：2004-11-23
申请号：US09849530
申请日：2001-05-07
申请人： Vincent J. McGahay , Thomas H. Ivers , Joyce C. Liu , Henry A. Nye, III
发明人： Vincent J. McGahay , Thomas H. Ivers , Joyce C. Liu , Henry A. Nye, III
IPC分类号： H01L2144
CPC分类号： H01L21/76849 , H01L21/76834 , H01L21/76867 , H01L21/76879 , H01L21/76886 , H01L21/76888 , H01L23/53233 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： Poorly adherent layers such as silicon nitride and silicon dioxide exhibit improved adhesion to copper member by providing an intervening germanium-containing layer. The germanium-containing layer is copper germanide, germanium oxide, germanium nitride or combinations thereof. The germanium-containing layer enhances the adhesion such that the poorly adherent layer is less susceptible to delamination from the copper member.
摘要翻译：通过提供介入的含锗层，差的粘附层如氮化硅和二氧化硅表现出改善的对铜构件的粘合性。含锗层是锗锗化锗，氧化锗，氮化锗或其组合。含锗层增强粘合性，使得不良粘附层不易受到铜构件的分层影响。

9. 发明授权

US06429067B1 Dual mask process for semiconductor devices 失效
标题翻译：半导体器件的双掩模工艺
公开(公告)号：US06429067B1
公开(公告)日：2002-08-06
申请号：US09765036
申请日：2001-01-17
申请人： Joyce C. Liu , James C. Brighten , Jeffrey J. Brown , John Golz , George A. Kaplita , Rebecca Mih , Senthil Srinivasan , Jin Jwang Wu , Teresa J. Wu , Chienfan Yu
发明人： Joyce C. Liu , James C. Brighten , Jeffrey J. Brown , John Golz , George A. Kaplita , Rebecca Mih , Senthil Srinivasan , Jin Jwang Wu , Teresa J. Wu , Chienfan Yu
IPC分类号： H01L218242
CPC分类号： H01L27/10894 , H01L21/823842 , H01L27/10873
摘要： A method for fabricating a dual gate structure, comprising providing a semiconductor substrate having a first device area and a second device area covered by a gate oxide layer and a polysilicon layer, forming a first hard mask over the polysilicon layer, said first hard mask being a material that is resistant to a first etching, but susceptible to a second etching forming a second hard mask over the first hard mask and the polysilicon layer, said second hard mask being a material that is resistant to a second etching, but susceptible to a first etching, patterning and etching said second hard mask with a first etch to form a gate pattern on a first device area, and patterning and etching said first hard mask with a second etch to transfer gate patterns on the first and second device areas.
摘要翻译：一种制造双栅结构的方法，包括提供半导体衬底，其具有由栅极氧化层和多晶硅层覆盖的第一器件区域和第二器件区域，在所述多晶硅层上形成第一硬掩模，所述第一硬掩模为耐受第一蚀刻的材料，但易于在第一硬掩模和多晶硅层上形成第二硬掩模的第二蚀刻，所述第二硬掩模是耐第二蚀刻的材料，但易受第首先用第一蚀刻蚀刻图案并蚀刻所述第二硬掩模，以在第一器件区域上形成栅极图案，并用第二蚀刻图案化和蚀刻所述第一硬掩模以在第一和第二器件区域上传输栅极图案。

10. 发明授权

US06271595B1 Method for improving adhesion to copper 失效
标题翻译：提高与铜的附着力的方法
公开(公告)号：US06271595B1
公开(公告)日：2001-08-07
申请号：US09231618
申请日：1999-01-14
申请人： Vincent J. McGahay , Thomas H. Ivers , Joyce C. Liu , Henry A. Nye, III
发明人： Vincent J. McGahay , Thomas H. Ivers , Joyce C. Liu , Henry A. Nye, III
IPC分类号： H01L21328
CPC分类号： H01L21/76849 , H01L21/76834 , H01L21/76867 , H01L21/76879 , H01L21/76886 , H01L21/76888 , H01L23/53233 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： Poorly adherent layers such as silicon nitride and silicon dioxide exhibit improved adhesion to copper member by providing an intervening germanium-containing layer. The germanium-containing layer is copper germanide, germanium oxide, germanium bitride or combinations thereof. The germanium-containing layer enhances the adhesion such that the poorly adherent layer is less susceptible to delamination from the copper member.
摘要翻译：通过提供介入的含锗层，差的粘附层如氮化硅和二氧化硅表现出改善的对铜构件的粘合性。含锗层是锗锗，锗，锗或其组合。含锗层增强粘合性，使得不良粘附层不易受到铜构件的分层影响。

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