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1. 发明申请

US20050153530A1 FET GATE STRUCTURE WITH METAL GATE ELECTRODE AND SILICIDE CONTACT 有权
标题翻译：具有金属栅极电极和硅化物接触的FET栅结构
公开(公告)号：US20050153530A1
公开(公告)日：2005-07-14
申请号：US10707757
申请日：2004-01-09
申请人： Victor Ku , An Steegen , Hsing-Jen Wann
发明人： Victor Ku , An Steegen , Hsing-Jen Wann
IPC分类号： H01L21/28 , H01L21/3205 , H01L21/335 , H01L21/336 , H01L21/8238 , H01L27/092 , H01L29/423 , H01L29/49 , H01L29/78
CPC分类号： H01L29/66583 , H01L21/28079 , H01L21/28247 , H01L21/823835 , H01L29/66545
摘要： A method is provided for fabricating a single-metal or dual metal replacement gate structure for a semiconductor device; the structure includes a silicide contact to the gate region. A dummy gate structure and sacrificial gate dielectric are removed to expose a portion of the substrate; a gate dielectric is formed thereon. A metal layer is formed overlying the gate dielectric and the dielectric material. This metal layer may conveniently be a blanket metal layer covering a device wafer. A silicon layer is then formed overlying the metal layer; this layer may also be a blanket wafer. A planarization or etchback process is then performed, so that the top surface of the dielectric material is exposed while other portions of the metal layer and the silicon layer remain in the gate region and have surfaces coplanar with the top surface of the dielectric material. A silicide contact is then formed which is in contact with the metal layer in the gate region.
摘要翻译：提供一种用于制造用于半导体器件的单金属或双金属替代栅极结构的方法; 该结构包括与栅极区域的硅化物接触。去除伪栅极结构和牺牲栅极电介质以暴露衬底的一部分; 在其上形成栅极电介质。形成覆盖栅极电介质和电介质材料的金属层。该金属层可以方便地覆盖覆盖器件晶片的覆盖金属层。然后形成覆盖在金属层上的硅层; 该层也可以是覆盖晶片。然后执行平面化或回蚀工艺，使得介电材料的顶表面被暴露，而金属层和硅层的其它部分保留在栅极区域中并具有与电介质材料的顶表面共面的表面。然后形成与栅极区域中的金属层接触的硅化物接触。

2. 发明授权

US06297127B1 Self-aligned deep trench isolation to shallow trench isolation 失效
标题翻译：自对准深沟槽隔离到浅沟槽隔离
公开(公告)号：US06297127B1
公开(公告)日：2001-10-02
申请号：US09599699
申请日：2000-06-22
申请人： Bomy A. Chen , Liang-Kai Han , Robert Hannon , Jay G. Harrington , Herbert L. Ho , Hsing-Jen Wann
发明人： Bomy A. Chen , Liang-Kai Han , Robert Hannon , Jay G. Harrington , Herbert L. Ho , Hsing-Jen Wann
IPC分类号： H01L2176
CPC分类号： H01L21/76232
摘要： Shallow trench isolation is combined with optional deep trenches that are self-aligned with the shallow trenches, at the corners of the shallow trenches, and have a deep trench width that is controlled by the thickness of a temporary sidewall deposited in the interior of the shallow trench and is limited by the sidewall deposition thickness of the deep trench fill.
摘要翻译：浅沟槽隔离与在浅沟槽的角部处与浅沟槽自对准的可选深沟槽组合，并且具有深沟槽宽度，其由沉积在浅层的内部中的临时侧壁的厚度控制并且受到深沟槽填充物的侧壁沉积厚度的限制。

3. 发明授权

US07081393B2 Reduced dielectric constant spacer materials integration for high speed logic gates 失效
标题翻译：降低介电常数间隔材料集成用于高速逻辑门
公开(公告)号：US07081393B2
公开(公告)日：2006-07-25
申请号：US10709652
申请日：2004-05-20
申请人： Michael P. Belyansky , Joyce C. Liu , Hsing Jen Wann , Richard Stephen Wise , Hongwen Yan
发明人： Michael P. Belyansky , Joyce C. Liu , Hsing Jen Wann , Richard Stephen Wise , Hongwen Yan
IPC分类号： H01L21/336
CPC分类号： H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： An FET transistor has a gate disposed between a source and a drain; a gate dielectric layer disposed underneath the gate; and a spacer on a side of the gate. The gate dielectric layer is conventional oxide and the spacer has a reduced dielectric constant (k). The reduced dielectric constant (k) may be less than 3.85, or it may be less than 7.0 (˜nitride), but greater than 3.85 (˜oxide). Preferably, the spacer comprises a material which can be etched selectively to the gate dielectric layer. The spacer may be porous, and a thin layer is deposited on the porous spacer to prevent moisture absorption. The spacer may comprise a material selected from the group consisting of Black Diamond, Coral, TERA and Blok type materials. Pores may be formed in the spacer material by exposing the spacers to an oxygen plasma.
摘要翻译： FET晶体管具有设置在源极和漏极之间的栅极; 设置在栅极下方的栅介质层; 和在门侧的间隔物。栅极电介质层是常规的氧化物，间隔物具有降低的介电常数（k）。降低的介电常数（k）可以小于3.85，或者可以小于7.0（〜氮化物），但大于3.85（〜氧化物）。优选地，间隔物包括可以选择性地蚀刻到栅极介电层的材料。间隔物可以是多孔的，并且在多孔间隔物上沉积薄层以防止吸湿。间隔物可以包括选自黑钻石，珊瑚，TERA和Blok型材料的材料。可以通过将间隔物暴露于氧等离子体来在间隔物材料中形成孔。

4. 发明申请

US20050264320A1 LOGIC CIRCUITS HAVING LINEAR AND CELLULAR GATE TRANSISTORS 失效
标题翻译：具有线性和细胞栅极晶体管的逻辑电路
公开(公告)号：US20050264320A1
公开(公告)日：2005-12-01
申请号：US10709784
申请日：2004-05-27
申请人： Victor Chan , Hsing-Jen Wann , Shih-Fen Huang , Oleg Gluschenkov
发明人： Victor Chan , Hsing-Jen Wann , Shih-Fen Huang , Oleg Gluschenkov
IPC分类号： H01L27/02 , H03K17/16 , H03K19/017 , H03K19/094 , H03K19/0948
CPC分类号： H03K19/0948 , H01L27/0203 , H03K19/01707
摘要： A logic circuit is provided with a first inverter having a plurality of linear gate transistors driving a first capacitive load and a second inverter having a plurality of cellular gate transistors driving a second capacitive load. The first inverter is serially connected to the second inverter. The second capacitive load is larger than the first capacitive load.
摘要翻译：逻辑电路设置有具有驱动第一电容性负载的多个线性栅极晶体管的第一反相器和驱动第二电容负载的多个蜂窝状栅极晶体管的第二反相器。第一个逆变器串联连接到第二个逆变器。第二容性负载大于第一容性负载。

5. 发明授权

US6121077A Silicon-on-insulator transistors having improved current characteristics and reduced electrostatic discharge susceptibility 失效
标题翻译：具有改善的电流特性和降低的静电放电敏感性的绝缘体上硅晶体管
公开(公告)号：US6121077A
公开(公告)日：2000-09-19
申请号：US393767
申请日：1999-09-10
申请人： Chenming Hu , Mansun John Chan , Hsing-Jen Wann , Ping Keung Ko
发明人： Chenming Hu , Mansun John Chan , Hsing-Jen Wann , Ping Keung Ko
IPC分类号： H01L21/336 , H01L29/423 , H01L29/786 , H01L21/00
CPC分类号： H01L29/42384 , H01L29/66537 , H01L29/66772 , H01L29/78615 , H01L29/78618 , H01L29/78621 , H01L29/78624 , H01L29/78696 , H01L27/1207
摘要： An SOI MOSFET having improved electrical characteristics includes a low barrier body contact under the source region, and alternatively under the drain region, to facilitate collection and removal of current carriers generated by impact ionization. Fully-depleted and non-fully-depleted SOI MOSFETs can be integrated on the same chip by providing some transistors with thicker source and drain regions with a recessed channel therebetween and by selective channel dopant implant. Accordingly, digital circuitry and analog circuitry can be combined on one substrate. Improved electrostatic discharge protection is provided by fabricating transistors for the protection circuit directly in the supporting substrate by first removing the silicon thin film and underlying insulation barrier. Alternatively, improved transistors for electrostatic discharge protection can be formed in the silicon film by fabricating the transistor in a plurality of electrically isolated segments, each segment having source and drain regions separated by a channel region with the regions being electrically interconnected with like regions in other segments. Increased ESD current can be realized as compared to the ESD current for a wider unsegmented device.
摘要翻译：具有改善的电特性的SOI MOSFET包括在源极区域下方的低阻挡体接触，以及在漏极区域下方，以便于收集和去除由冲击电离产生的电流载流子。完全耗尽和非完全耗尽的SOI MOSFET可以集成在同一芯片上，通过提供一些具有较厚源极和漏极区域的晶体管，其间具有凹陷沟道并且通过选择性沟道掺杂剂注入。因此，数字电路和模拟电路可以组合在一个基板上。通过首先去除硅薄膜和下面的绝缘屏障，通过制造直接在支撑衬底中的保护电路的晶体管来提供改进的静电放电保护。或者，通过在多个电隔离段中制造晶体管，可以在硅膜中形成用于静电放电保护的改进的晶体管，每个段具有由沟道区分开的源极和漏极区域，其中该区域与其它区域中的相似区域电互连细分。与较宽的未分段器件的ESD电流相比，可以实现增加的ESD电流。

6. 发明授权

US07923786B2 Selective silicon-on-insulator isolation structure and method 有权
标题翻译：选择性绝缘体上硅绝缘体隔离结构及方法
公开(公告)号：US07923786B2
公开(公告)日：2011-04-12
申请号：US11871249
申请日：2007-10-12
申请人： An L. Steegen , Maheswaran Surendra , Hsing-Jen Wann , Ying Zhang , Franz Zach , Robert Wong
发明人： An L. Steegen , Maheswaran Surendra , Hsing-Jen Wann , Ying Zhang , Franz Zach , Robert Wong
IPC分类号： H01L21/70
CPC分类号： H01L29/66651 , H01L21/823481 , H01L21/823878 , H01L21/84 , H01L27/1203 , H01L29/0653 , H01L29/66772
摘要： A first aspect of the present invention is a method of forming an isolation structure including: (a) providing a semiconductor substrate; (b) forming a buried N-doped region in the substrate; (c) forming a vertical trench in the substrate, the trench extending into the N-doped region; (d) removing the N-doped region to form a lateral trench communicating with and extending perpendicular to the vertical trench; and (e) at least partially filling the lateral trench and filling the vertical trench with one or more insulating materials.
摘要翻译：本发明的第一方面是一种形成隔离结构的方法，包括：（a）提供半导体衬底; （b）在衬底中形成掩埋的N掺杂区域; （c）在所述衬底中形成垂直沟槽，所述沟槽延伸到所述N掺杂区域中; （d）去除所述N掺杂区域以形成与所述垂直沟槽连通并垂直于所述垂直沟槽延伸的横向沟槽; 和（e）至少部分地填充横向沟槽并用一种或多种绝缘材料填充垂直沟槽。

7. 发明申请

US20080029818A1 SELECTIVE SILICON-ON-INSULATOR ISOLATION STRUCTURE AND METHOD 有权
标题翻译：选择性绝缘子绝缘体隔离结构和方法
公开(公告)号：US20080029818A1
公开(公告)日：2008-02-07
申请号：US11871249
申请日：2007-10-12
申请人： An Steegen , Maheswaran Surendra , Hsing-Jen Wann , Ying Zhang , Franz Zach , Robert Wong
发明人： An Steegen , Maheswaran Surendra , Hsing-Jen Wann , Ying Zhang , Franz Zach , Robert Wong
IPC分类号： H01L27/12
CPC分类号： H01L29/66651 , H01L21/823481 , H01L21/823878 , H01L21/84 , H01L27/1203 , H01L29/0653 , H01L29/66772
摘要： A first aspect of the present invention is a method of forming an isolation structure including: (a) providing a semiconductor substrate; (b) forming a buried N-doped region in the substrate; (c) forming a vertical trench in the substrate, the trench extending into the N-doped region; (d) removing the N-doped region to form a lateral trench communicating with and extending perpendicular to the vertical trench; and (e) at least partially filling the lateral trench and filling the vertical trench with one or more insulating materials.
摘要翻译：本发明的第一方面是一种形成隔离结构的方法，包括：（a）提供半导体衬底; （b）在衬底中形成掩埋的N掺杂区域; （c）在所述衬底中形成垂直沟槽，所述沟槽延伸到所述N掺杂区域中; （d）去除所述N掺杂区域以形成与所述垂直沟槽连通并垂直于所述垂直沟槽延伸的横向沟槽; 和（e）至少部分地填充横向沟槽并用一种或多种绝缘材料填充垂直沟槽。

8. 发明授权

US06936522B2 Selective silicon-on-insulator isolation structure and method 失效
标题翻译：选择性绝缘体上硅绝缘体隔离结构及方法
公开(公告)号：US06936522B2
公开(公告)日：2005-08-30
申请号：US10604102
申请日：2003-06-26
申请人： An L. Steegen , Maheswaran Surendra , Hsing-Jen Wann , Ying Zhang , Franz Zach , Robert Wong
发明人： An L. Steegen , Maheswaran Surendra , Hsing-Jen Wann , Ying Zhang , Franz Zach , Robert Wong
IPC分类号： H01L21/336 , H01L21/76 , H01L21/8234 , H01L21/8238 , H01L21/8242 , H01L21/84 , H01L27/12 , H01L29/76 , H01L31/062
CPC分类号： H01L29/66651 , H01L21/823481 , H01L21/823878 , H01L21/84 , H01L27/1203 , H01L29/0653 , H01L29/66772
摘要： A first aspect of the present invention is a method of forming an isolation structure including: (a) providing a semiconductor substrate; (b) forming a buried N-doped region in the substrate; (c) forming a vertical trench in the substrate, the trench extending into the N-doped region; (d) removing the N-doped region to form a lateral trench communicating with and extending perpendicular to the vertical trench; and (e) at least partially filling the lateral trench and filling the vertical trench with one or more insulating materials.
摘要翻译：本发明的第一方面是一种形成隔离结构的方法，包括：（a）提供半导体衬底; （b）在衬底中形成掩埋的N掺杂区域; （c）在所述衬底中形成垂直沟槽，所述沟槽延伸到所述N掺杂区域中; （d）去除所述N掺杂区域以形成与所述垂直沟槽连通并垂直于所述垂直沟槽延伸的横向沟槽; 和（e）至少部分地填充横向沟槽并用一种或多种绝缘材料填充垂直沟槽。

9. 发明授权

US5982003A Silicon-on-insulator transistors having improved current characteristics and reduced electrostatic discharge susceptibility 失效
公开(公告)号：US5982003A
公开(公告)日：1999-11-09
申请号：US461355
申请日：1995-06-05
申请人： Chenming Hu , Mansun John Chan , Hsing-Jen Wann , Ping Keung Ko
发明人： Chenming Hu , Mansun John Chan , Hsing-Jen Wann , Ping Keung Ko
IPC分类号： H01L21/336 , H01L29/423 , H01L29/786 , H01L27/01 , H01L27/12 , H01L29/04 , H01L31/0392
CPC分类号： H01L29/42384 , H01L29/66537 , H01L29/66772 , H01L29/78615 , H01L29/78618 , H01L29/78621 , H01L29/78624 , H01L29/78696 , H01L27/1207
摘要： An SOI MOSFET having improved electrical characteristics includes a low barrier body contact under the source region, and alternatively under the drain region, to facilitate collection and removal of current carriers generated by impact ionization. Fully-depleted and non-fully-depleted SOI MOSFETs can be integrated on the same chip by providing some transistors with thicker source and drain regions with a recessed channel therebetween and by selective channel dopant implant. Accordingly, digital circuitry and analog circuitry can be combined on one substrate. Improved electrostatic discharge protection is provided by fabricating transistors for the protection circuit directly in the supporting substrate by first removing the silicon thin film and underlying insulation barrier. Alternatively, improved transistors for electrostatic discharge protection can be formed in the silicon film by fabricating the transistor in a plurality of electrically isolated segments, each segment having source and drain regions separated by a channel region with the regions being electrically interconnected with like regions in other segments. Increased ESD current can be realized as compared to the ESD current for a wider unsegmented device.

10. 发明授权

US5780899A Delta doped and counter doped dynamic threshold voltage MOSFET for ultra-low voltage operation 失效
标题翻译： Delta掺杂和反掺杂动态阈值电压MOSFET用于超低电压操作
公开(公告)号：US5780899A
公开(公告)日：1998-07-14
申请号：US534527
申请日：1995-09-27
申请人： Chenming Hu , Hsing-Jen Wann
发明人： Chenming Hu , Hsing-Jen Wann
IPC分类号： H01L27/092 , H01L29/78 , H01L29/786 , H01L29/76 , H01L27/01 , H01L29/94
CPC分类号： H01L27/092 , H01L29/783 , H01L29/7838 , H01L29/78606 , H01L29/78696
摘要： A dynamic threshold voltage IGFET such as a MOSFET is operable at voltages of 0.6 volt or less. The threshold voltage of the transistor is reduced to zero volt or less by interconnecting the gate contact and the device body in which the voltage controlled channel is located. The channel region is delta-doped or counter-doped which permits superior performance for high-end VSLI applications. A selective epitaxy on a counter-doped substrate can be used in a counter-doped device. Doped wells can be used in a bulk silicon substrate in forming the devices. Trenching can be used to isolate devices in the doped wells.
摘要翻译：诸如MOSFET的动态阈值电压IGFET可在0.6伏或更小的电压下工作。通过互连栅极接触和电压控制通道所在的器件主体，将晶体管的阈值电压降低到零伏特以下。沟道区域是δ掺杂或反掺杂的，这为高端VSLI应用提供了优异的性能。反掺杂衬底上的选择性外延可以用在反掺杂器件中。掺杂的阱可以用于体硅衬底中以形成器件。沟渠可用于隔离掺杂井中的设备。

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