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1. 发明申请

US20090104776A1 METHODS FOR FORMING NESTED AND ISOLATED LINES IN SEMICONDUCTOR DEVICES 审中-公开
标题翻译：在半导体器件中形成嵌套和隔离线的方法
公开(公告)号：US20090104776A1
公开(公告)日：2009-04-23
申请号：US11874392
申请日：2007-10-18
申请人： David M. Dobuzinsky , Johnathan E. Faltermeier , Naoyoshi Kusaba , Joyce C. Liu , Munir D. Naeem , Siddhartha Panda , Richard S. Wise , Hongwen Yan
发明人： David M. Dobuzinsky , Johnathan E. Faltermeier , Naoyoshi Kusaba , Joyce C. Liu , Munir D. Naeem , Siddhartha Panda , Richard S. Wise , Hongwen Yan
IPC分类号： H01L21/4763
CPC分类号： H01L21/76838 , H01L21/0337 , H01L21/0338 , H01L21/32137 , H01L21/32139
摘要： A method for forming lines for semiconductor devices including, depositing a shallow trench isolation (STI) film stack on a silicon substrate, depositing a layer of polysilicon on the STI film stack, depositing a layer of antireflective coating on the layer of polysilicon, developing a phototoresist on the antireflective coating, wherein the photoresist defines a line, etching the layer of antireflective coating and the layer of polysilicon using RIE with a low bias power, removing the photoresist, removing the layer of antireflective coating, etching the STI film stack to form the line, wherein the layer of polysilicon further defines the line.
摘要翻译：一种用于形成用于半导体器件的线的方法，包括：在硅衬底上沉积浅沟槽隔离（STI）膜堆叠，在所述STI膜堆叠上沉积多晶硅层，在所述多晶硅层上沉积一层抗反射涂层，在抗反射涂层上光致抗蚀剂，其中光致抗蚀剂限定线，使用具有低偏压功率的RIE蚀刻抗反射涂层和多晶硅层，去除光致抗蚀剂，去除抗反射涂层，蚀刻STI膜叠层以形成所述线，其中所述多晶硅层进一步限定所述线。

2. 发明申请

US20090047791A1 SEMICONDUCTOR ETCHING METHODS 审中-公开
标题翻译：半导体蚀刻方法
公开(公告)号：US20090047791A1
公开(公告)日：2009-02-19
申请号：US11839681
申请日：2007-08-16
申请人： David M. Dobuzinsky , Johnathan E. Faltermeier , Munir D. Naeem , William C. Wille , Richard S. Wise
发明人： David M. Dobuzinsky , Johnathan E. Faltermeier , Munir D. Naeem , William C. Wille , Richard S. Wise
IPC分类号： H01L21/302
CPC分类号： H01L21/3081 , H01L27/10844 , H01L27/11
摘要： A method of etching semiconductor structures is disclosed. The method may include etching an SRAM portion of a semiconductor device, the method comprising: providing a silicon substrate layer, a nitride layer thereover, an optical dispersive layer over the nitride layer, and a silicon anti-reflective coating layer thereover; etching the silicon anti-reflective coating layer using an image layer; removing the image layer; etching the optical dispersive layer while removing the silicon anti-reflective coating layer; etching the optical dispersive layer and the nitride layer simultaneously; and etching the optical dispersive layer, the nitride layer, and the silicon substrate simultaneously.
摘要翻译：公开了蚀刻半导体结构的方法。该方法可以包括蚀刻半导体器件的SRAM部分，该方法包括：提供硅衬底层，其上的氮化物层，氮化物层上的光学色散层和其上的硅抗反射涂层; 使用图像层蚀刻硅抗反射涂层; 去除图像层; 在去除硅抗反射涂层的同时蚀刻光学色散层; 同时蚀刻光学色散层和氮化物层; 并同时蚀刻光学色散层，氮化物层和硅衬底。

3. 发明授权

US06838347B1 Method for reducing line edge roughness of oxide material using chemical oxide removal 失效
标题翻译：使用化学氧化物去除减少氧化物材料的线边缘粗糙度的方法
公开(公告)号：US06838347B1
公开(公告)日：2005-01-04
申请号：US10605331
申请日：2003-09-23
申请人： Joyce C. Liu , Wesley C. Natzle , Richard S. Wise , Hongwen Yan , Bidan Zhang
发明人： Joyce C. Liu , Wesley C. Natzle , Richard S. Wise , Hongwen Yan , Bidan Zhang
IPC分类号： H01L21/311 , H01L21/3205 , H01L21/3213 , H01L21/336 , H01L21/4763
CPC分类号： H01L21/32139 , H01L21/31116
摘要： A method for reducing line edge roughness (LER) of a semiconductor gate structure includes patterning a photoresist layer formed over an oxide hardmask layer. The photoresist layer is etched so as to transfer a photoresist pattern to the oxide hardmask layer, the photoresist pattern having an initial LER. The exposed surfaces of the oxide hardmask are etched with a chemical oxide removal (COR) so as to form a reaction product on the exposed surfaces, wherein concave portions of the exposed surfaces are etched at a reduced rate with respect to convex portions of the exposed surfaces.

4. 发明授权

US07645356B2 Method of processing wafers with resonant heating 失效
标题翻译：用共振加热处理晶片的方法
公开(公告)号：US07645356B2
公开(公告)日：2010-01-12
申请号：US10721657
申请日：2003-11-25
申请人： Siddhartha Panda , Richard S. Wise
发明人： Siddhartha Panda , Richard S. Wise
IPC分类号： C23F1/00
CPC分类号： H01J37/32339 , H01L21/3065 , H01L21/32136
摘要： A method of etching a wafer using resonant infrared energy and a filter to control non-uniformities during plasma etch processing. The filter includes a predetermined array or stacked arrangement of variable transmission regions that mirror the spatial etch distortions caused by the plasma etching process. By spatially attenuating the levels of IR energy that reach the wafer, the filter improves uniformity in the etching process. Filters may be designed to compensate for edge fast etching due to macro-loading, asymmetric pumping in a plasma chamber, and magnetic field cusping.
摘要翻译：使用谐振红外能量蚀刻晶片的方法和用于在等离子体蚀刻处理期间控制不均匀性的滤光器。滤波器包括可反映由等离子体蚀刻工艺引起的空间蚀刻失真的可变透射区域的预定阵列或堆叠布置。通过空间衰减到达晶片的IR能量的水平，滤波器改善了蚀刻工艺中的均匀性。滤波器可以被设计为补偿由于宏载荷，等离子体室中的不对称泵浦和磁场冲击造成的边缘快速蚀刻。

5. 发明申请

US20080118955A1 METHOD FOR PRECISE TEMPERATURE CYCLING IN CHEMICAL / BIOCHEMICAL PROCESSES 审中-公开
标题翻译：化学/生化过程中精确循环的方法
公开(公告)号：US20080118955A1
公开(公告)日：2008-05-22
申请号：US11858280
申请日：2007-09-20
申请人： Siddhartha Panda , Richard S. Wise
发明人： Siddhartha Panda , Richard S. Wise
IPC分类号： C12P19/34 , B01J19/12
CPC分类号： C12Q1/686 , B01L7/52 , B01L7/5255 , B01L2300/1872 , C12Q2523/313
摘要： A method for implementing a temperature cycling operation for a biochemical sample to be reacted includes applying an infrared (IR) heating source to the biochemical sample to be reacted at a first infrared wavelength selected so as to generate a first desired temperature for a first duration and produce a first desired reaction within the biochemical sample; following the first desired reaction, applying the infrared (IR) heating source to the biochemical sample at a second infrared wavelength selected so as to generate a second desired temperature for a second duration and produce a second desired reaction within the biochemical sample; and wherein the first and second wavelengths generated by the IR source are selected to be coincident with corresponding absorptive wavelengths of the biochemical sample so as to heat the biochemical sample without directly heating a fluid medium containing the biochemical sample.
摘要翻译：用于实施待反应的生物化学样品的温度循环操作的方法包括将红外（IR）加热源施加到生物化学样品以在被选择的第一红外波长处反应，以便产生第一期望的第一期望温度，以及在生物化学样品中产生第一个所需的反应; 在第一期望的反应之后，以选择的第二红外波长将红外（IR）加热源施加到生物化学样品，以产生第二期望的第二期望温度，并在生化试样中产生第二所需反应; 并且其中由IR源产生的第一和第二波长被选择为与生物化学样品的相应吸收波长一致，以便加热生化样品而不直接加热含有生物化学样品的流体介质。

6. 发明授权

US07256399B2 Non-destructive in-situ elemental profiling 失效
标题翻译：非破坏性原位元素分析
公开(公告)号：US07256399B2
公开(公告)日：2007-08-14
申请号：US10907591
申请日：2005-04-07
申请人： Siddhartha Panda , Michael R. Sievers , Richard S. Wise
发明人： Siddhartha Panda , Michael R. Sievers , Richard S. Wise
IPC分类号： G01N23/227
CPC分类号： G01N23/2273
摘要： A non-destructive in-situ elemental profiling of a layer in a set of layers method and system are disclosed. In one embodiment, a first emission of a plurality of photoelectrons is caused from the layer to be elementally profiled. An elemental profile of the layer is determined based on the emission. In another embodiment, a second emission of a plurality of photoelectrons is also received from the layer, and an elemental profile is determined by comparison of the resulting signals. A process that is altering the layer can then be controlled “on-the-fly” to obtain a desired material composition. Since the method can be employed in-situ and is non-destructive, it reduces turn around time and lowers wafer consumption. The invention also records the composition of all processed wafers, hence, removing the conventional statistical sampling problem.
摘要翻译：公开了一组层中的层的非破坏性原位元素分析方法和系统。在一个实施例中，多个光电子的第一次发射是从该层进行元素分析。基于发射确定层的元素分布。在另一个实施例中，也从该层接收多个光电子的第二次发射，并且通过比较所得到的信号来确定元素分布。然后可以“即时”控制改变层的方法以获得所需的材料组成。由于该方法可以原位使用并且是非破坏性的，所以可以减少周转时间并降低晶片消耗。本发明还记录了所有加工晶片的组成，因此，去除了常规统计抽样问题。

7. 发明授权

US07186660B2 Silicon precursors for deep trench silicon etch processes 失效
标题翻译：用于深沟槽硅蚀刻工艺的硅前体
公开(公告)号：US07186660B2
公开(公告)日：2007-03-06
申请号：US10338964
申请日：2003-01-08
申请人： Siddhartha Panda , Richard S. Wise
发明人： Siddhartha Panda , Richard S. Wise
IPC分类号： H01L21/302
CPC分类号： H01L21/3065 , H01L27/10861
摘要： The present invention relates to etch chemistry and methods for the etching of silicon substrates. The method is particularly useful for deep trench etching of silicon substrates and produces a trench having a high aspect ratio. In this type of deep trench etching, control of the profile of the trench is addressed by the etch chemistry disclosed herein. The etchant described in the present invention comprises silicon and a halogen component, and may be gaseous, liquid or solid. The etchant disclosed is also substantially free of hydrogen and carbon.
摘要翻译：本发明涉及用于蚀刻硅衬底的蚀刻化学和方法。该方法对于硅衬底的深沟槽蚀刻特别有用，并且产生具有高纵横比的沟槽。在这种类型的深沟槽蚀刻中，通过本文公开的蚀刻化学处理对沟槽轮廓的控制。本发明中描述的蚀刻剂包括硅和卤素组分，并且可以是气态，液态或固体。所公开的蚀刻剂也基本上不含氢和碳。

8. 发明授权

US06656375B1 Selective nitride: oxide anisotropic etch process 失效
标题翻译：选择性氮化物：氧化物各向异性蚀刻工艺
公开(公告)号：US06656375B1
公开(公告)日：2003-12-02
申请号：US09014806
申请日：1998-01-28
申请人： Michael D. Armacost , David M. Dobuzinsky , John C. Malinowski , Hung Y. Ng , Richard S. Wise , Chienfan Yu
发明人： Michael D. Armacost , David M. Dobuzinsky , John C. Malinowski , Hung Y. Ng , Richard S. Wise , Chienfan Yu
IPC分类号： C23F100
CPC分类号： H01L21/31116
摘要： An anisotropic etching process for a nitride layer of a substrate, the process comprising using an etchant gas which comprises a hydrogen-rich fluorohydrocarbon, an oxidant and a carbon source. The hydrogen-rich fluorohydrocarbon is preferably one of CH3F or CH2F2, the carbon source is preferably one of CO2 or CO, and the oxidant is preferably O2. The fluorohydrocarbon is preferably present in the gas at approximately 7%-35% by volume, the oxidant is preferably present in the gas at approximately 1%-35% by volume, and the carbon source is preferably present in the gas at approximately 30%-92%.
摘要翻译：用于衬底的氮化物层的各向异性蚀刻工艺，该方法包括使用包含富氢氟代烃，氧化剂和碳源的蚀刻剂气体。富氢氟烃优选为CH 3 F或CH 2 F 2之一，碳源优选为CO 2或CO之一，氧化剂优选为O 2。氟烃优选以约7％-35体积％存在于气体中，氧化剂优选以约1％-35％体积的比例存在于气体中，并且碳源优选以约30％的比例存在于气体中， -92％。

9. 发明授权

US6093281A Baffle plate design for decreasing conductance lost during precipitation of polymer precursors in plasma etching chambers 失效
标题翻译：挡板设计，用于降低等离子体蚀刻室中聚合物前体沉淀过程中的电导损失
公开(公告)号：US6093281A
公开(公告)日：2000-07-25
申请号：US31232
申请日：1998-02-26
申请人： Richard S. Wise , David M. Dobuzinsky , William C. Wille
发明人： Richard S. Wise , David M. Dobuzinsky , William C. Wille
IPC分类号： C23C16/44 , H01J37/32 , C23C16/00
CPC分类号： H01J37/32834 , C23C16/4412 , H01J37/3244
摘要： A baffle plate for semiconductor processing apparatus. The baffle plate includes a plurality of slits. A plurality of fins are located between adjacent slits. The fins have varying heights and a supporting portion interconnects the fins.
摘要翻译：一种用于半导体处理装置的挡板。挡板包括多个狭缝。多个翅片位于相邻狭缝之间。翅片具有不同的高度，并且支撑部分互连翅片。

10. 发明授权

US07329602B2 Wiring structure for integrated circuit with reduced intralevel capacitance 有权
标题翻译：具有降低的体积电容的集成电路的接线结构
公开(公告)号：US07329602B2
公开(公告)日：2008-02-12
申请号：US11203944
申请日：2005-08-15
申请人： Richard S. Wise , Bomy A. Chen , Mark C. Hakey , Hongwen Yan
发明人： Richard S. Wise , Bomy A. Chen , Mark C. Hakey , Hongwen Yan
IPC分类号： H01L21/4763
CPC分类号： H01L23/5222 , H01L21/7682 , H01L23/53295 , H01L2221/1057 , H01L2924/0002 , H01L2924/00
摘要： A method of forming a wiring structure for an integrated circuit includes the steps of forming a plurality of features in a layer of dielectric material, and forming spacers on sidewalls of the features. Conductors are then formed in the features, being separated from the sidewalls by the spacers. The spacers are then removed, forming air gaps at the sidewalls so that the conductors are separated from the sidewalls by the air gaps. Dielectric layers above and below the conductors may be low-k dielectrics having a dielectric constant less than that of the dielectric between the conductors. A cross-section of each of the conductors has a bottom in contact with the a low-k dielectric layer, a top in contact with another low-k dielectric, and sides in contact only with the air gaps. The air gaps serve to reduce the intralevel capacitance.
摘要翻译：形成用于集成电路的布线结构的方法包括以下步骤：在介电材料层中形成多个特征，以及在特征的侧壁上形成间隔物。然后在特征中形成导体，通过间隔件与侧壁分离。然后去除间隔物，在侧壁处形成气隙，使得导体通过气隙与侧壁分离。导体之上和之下的介电层可以是具有比导体之间的电介质的介电常数小的介电常数的低k电介质。每个导体的横截面具有与低k电介质层接触的底部，与另一低k电介质接触的顶部和仅与气隙接触的侧面。气隙用于降低电容值。

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