专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20090104776A1 METHODS FOR FORMING NESTED AND ISOLATED LINES IN SEMICONDUCTOR DEVICES 审中-公开
标题翻译：在半导体器件中形成嵌套和隔离线的方法
公开(公告)号：US20090104776A1
公开(公告)日：2009-04-23
申请号：US11874392
申请日：2007-10-18
申请人： David M. Dobuzinsky , Johnathan E. Faltermeier , Naoyoshi Kusaba , Joyce C. Liu , Munir D. Naeem , Siddhartha Panda , Richard S. Wise , Hongwen Yan
发明人： David M. Dobuzinsky , Johnathan E. Faltermeier , Naoyoshi Kusaba , Joyce C. Liu , Munir D. Naeem , Siddhartha Panda , Richard S. Wise , Hongwen Yan
IPC分类号： H01L21/4763
CPC分类号： H01L21/76838 , H01L21/0337 , H01L21/0338 , H01L21/32137 , H01L21/32139
摘要： A method for forming lines for semiconductor devices including, depositing a shallow trench isolation (STI) film stack on a silicon substrate, depositing a layer of polysilicon on the STI film stack, depositing a layer of antireflective coating on the layer of polysilicon, developing a phototoresist on the antireflective coating, wherein the photoresist defines a line, etching the layer of antireflective coating and the layer of polysilicon using RIE with a low bias power, removing the photoresist, removing the layer of antireflective coating, etching the STI film stack to form the line, wherein the layer of polysilicon further defines the line.
摘要翻译：一种用于形成用于半导体器件的线的方法，包括：在硅衬底上沉积浅沟槽隔离（STI）膜堆叠，在所述STI膜堆叠上沉积多晶硅层，在所述多晶硅层上沉积一层抗反射涂层，在抗反射涂层上光致抗蚀剂，其中光致抗蚀剂限定线，使用具有低偏压功率的RIE蚀刻抗反射涂层和多晶硅层，去除光致抗蚀剂，去除抗反射涂层，蚀刻STI膜叠层以形成所述线，其中所述多晶硅层进一步限定所述线。

2. 发明申请

US20090072355A1 DUAL SHALLOW TRENCH ISOLATION STRUCTURE 审中-公开
标题翻译：双层隔离隔离结构
公开(公告)号：US20090072355A1
公开(公告)日：2009-03-19
申请号：US11856260
申请日：2007-09-17
申请人： Kangguo Cheng , Lisa F. Edge , Johnathan E. Faltermeier , Naoyoshi Kusaba
发明人： Kangguo Cheng , Lisa F. Edge , Johnathan E. Faltermeier , Naoyoshi Kusaba
IPC分类号： H01L29/06 , H01L21/311
CPC分类号： H01L21/76229 , H01L21/76232
摘要： A protective dielectric layer is formed on a first shallow trench having straight sidewalls, while exposing a second shallow trench. An oxidation barrier layer is formed on the semiconductor substrate. A resist is applied and recessed within the second shallow trench. The oxidation barrier layer is removed above the recessed resist. The resist is removed and thermal oxidation is performed so that a thermal oxide collar is formed above the remaining oxidation mask layer. The oxidation barrier layer is thereafter removed and exposed semiconductor area therebelow depth is etched to form a bottle shaped shallow trench. The first and the bottle shaped trenches are filled with a dielectric material to form a straight sidewall shallow trench isolation structure and a bottle shallow trench isolation structure, respectively. Both shallow trench isolation structures may be employed to provide optimal electrical isolation and device performance to semiconductor devices having different depths.
摘要翻译：在具有直的侧壁的第一浅沟槽上形成保护电介质层，同时暴露第二浅沟槽。在半导体衬底上形成氧化阻挡层。抗蚀剂被施加并凹入第二浅沟槽内。在凹陷的抗蚀剂上方去除氧化阻挡层。去除抗蚀剂并进行热氧化，使得在剩余的氧化掩模层上方形成热氧化物环。之后除去氧化阻挡层，并对其下方的暴露的半导体区域进行蚀刻以形成瓶状浅沟槽。第一和瓶形沟槽填充有电介质材料，分别形成直的侧壁浅沟槽隔离结构和瓶浅沟槽隔离结构。可以使用浅沟槽隔离结构来为具有不同深度的半导体器件提供最佳的电隔离和器件性能。

3. 发明授权

US08673737B2 Array and moat isolation structures and method of manufacture 有权
标题翻译：阵列和护城隔离结构及其制造方法
公开(公告)号：US08673737B2
公开(公告)日：2014-03-18
申请号：US13274389
申请日：2011-10-17
申请人： Naoyoshi Kusaba , Oh-jung Kwon , Zhengwen Li , Hongwen Yan
发明人： Naoyoshi Kusaba , Oh-jung Kwon , Zhengwen Li , Hongwen Yan
IPC分类号： H01L21/76
CPC分类号： H01L29/423 , H01L21/762 , H01L27/10805 , H01L27/10829 , H01L27/1087 , H01L29/66181 , H01L29/945
摘要： An array or moat isolation structure for eDRAM and methods of manufacture is provided. The method includes forming a deep trench for a memory array and an isolation region. The method includes forming a node dielectric on exposed surfaces of the deep trench for the memory array and the isolation region. The method includes filling remaining portions of the deep trench for the memory array with a metal, and lining the deep trench of the isolation region with the metal. The method includes filling remaining portions of the deep trench for the isolation region with a material, on the metal within the deep trench for the memory array. The method includes recessing the metal within the deep trench for the memory array and the isolation region. The metal in the deep trench of the memory array is recessed to a greater depth than the metal in the isolation region.
摘要翻译：提供了一种用于eDRAM的阵列或护城隔离结构及其制造方法。该方法包括形成用于存储器阵列的深沟槽和隔离区域。该方法包括在用于存储器阵列和隔离区域的深沟槽的暴露表面上形成节点电介质。该方法包括用金属填充用于存储器阵列的深沟槽的剩余部分，并用金属衬里隔离区域的深沟槽。该方法包括用用于存储器阵列的深沟槽内的金属上的材料填充用于隔离区域的深沟槽的剩余部分。该方法包括使用于存储器阵列和隔离区域的深沟槽内的金属凹陷。存储器阵列的深沟槽中的金属凹陷到比隔离区域中的金属更深的深度。

4. 发明申请

US20130099354A1 CAPACITOR WITH DEEP TRENCH ION IMPLANTATION 失效
标题翻译：电容器与深层离子植入
公开(公告)号：US20130099354A1
公开(公告)日：2013-04-25
申请号：US13279877
申请日：2011-10-24
申请人： Chengwen Pei , Roger Allen Booth, JR. , Herbert Lei Ho , Naoyoshi Kusaba
发明人： Chengwen Pei , Roger Allen Booth, JR. , Herbert Lei Ho , Naoyoshi Kusaba
IPC分类号： H01L29/92 , H01L21/02
CPC分类号： H01L29/945 , H01L29/66181
摘要： An improved semiconductor capacitor and method of fabrication is disclosed. Embodiments utilize a deep trench which is then processed by performing a pre-amorphous implant on the trench interior to transform the interior surface of the trench to amorphous silicon which eliminates the depletion region that can degrade capacitor performance.
摘要翻译：公开了一种改进的半导体电容器和制造方法。实施例利用深沟槽，然后通过在沟槽内部执行预非晶体植入来将沟槽的内表面转变为非晶硅来处理，以消除可能降低电容器性能的耗尽区。

5. 发明申请

US20120175694A1 STRUCTURE AND METHOD OF FORMING ENHANCED ARRAY DEVICE ISOLATION FOR IMPLANTED PLATE EDRAM 有权
标题翻译：形成增强板阵列隔离装置的结构和方法
公开(公告)号：US20120175694A1
公开(公告)日：2012-07-12
申请号：US13408187
申请日：2012-02-29
申请人： Herbert L. Ho , Naoyoshi Kusaba , Karen A. Nummy , Carl J. Radens , Ravi M. Todi , Geng Wang
发明人： Herbert L. Ho , Naoyoshi Kusaba , Karen A. Nummy , Carl J. Radens , Ravi M. Todi , Geng Wang
IPC分类号： H01L27/108
CPC分类号： H01L27/10823 , H01L21/76264 , H01L21/84 , H01L27/10829 , H01L27/1087 , H01L27/10897 , H01L27/1203 , H01L29/0653 , H01L29/66181
摘要： A memory device is provided including a semiconductor on insulator (SOI) substrate including a first semiconductor layer atop a buried dielectric layer, wherein the buried dielectric layer is overlying a second semiconductor layer. A capacitor is present in a trench, wherein the trench extends from an upper surface of the first semiconductor layer through the buried dielectric layer and extends into the second semiconductor layer. A protective oxide is present in a void that lies adjacent the first semiconductor layer, and a pass transistor is present atop the semiconductor on insulator substrate in electrical communication with the capacitor.
摘要翻译：提供了一种存储器件，其包括绝缘体上半导体（SOI）衬底，其包括位于掩埋介电层顶部的第一半导体层，其中所述掩埋介电层覆盖在第二半导体层上。电容器存在于沟槽中，其中沟槽从第一半导体层的上表面延伸穿过埋入介质层并延伸到第二半导体层。保护性氧化物存在于位于第一半导体层附近的空隙中，并且传导晶体管存在于与电容器电连通的绝缘体上半导体衬底上。

6. 发明授权

US08298907B2 Structure and method of forming enhanced array device isolation for implanted plate eDRAM 有权
标题翻译：为植入板eDRAM形成增强阵列器件隔离的结构和方法
公开(公告)号：US08298907B2
公开(公告)日：2012-10-30
申请号：US13323033
申请日：2011-12-12
申请人： Herbert L. Ho , Naoyoshi Kusaba , Karen A. Nummy , Carl J. Radens , Ravi M. Todi , Geng Wang
发明人： Herbert L. Ho , Naoyoshi Kusaba , Karen A. Nummy , Carl J. Radens , Ravi M. Todi , Geng Wang
IPC分类号： H01L21/20
CPC分类号： H01L27/10823 , H01L21/76264 , H01L21/84 , H01L27/10829 , H01L27/1087 , H01L27/10897 , H01L27/1203 , H01L29/0653 , H01L29/66181
摘要： A method for forming a memory device in a semiconductor on insulator substrate is provided, in which a protective oxide that is present on the sidewalls of the trench protects the first semiconductor layer, i.e., SOI layer, of the semiconductor on insulator substrate during bottle etching of the trench. In one embodiment, the protective oxide reduces back channel effects of the transistors to the memory devices in the trench that are formed in the semiconductor on insulator substrate. In another embodiment, a thermal oxidation process increases the thickness of the buried dielectric layer of a bonded semiconductor on insulator substrate by oxidizing the bonded interface between the buried dielectric layer and at least one semiconductor layers of the semiconductor on insulator substrate. The increased thickness of the buried dielectric layer may reduce back channel effects in devices formed on the substrate having trench memory structures.
摘要翻译：提供了一种在半导体绝缘体衬底上形成存储器件的方法，其中存在于沟槽的侧壁上的保护氧化物在瓶蚀刻期间保护半导体绝缘体衬底上的第一半导体层即SOI层的沟槽。在一个实施例中，保护氧化物减少晶体管对形成在绝缘体上半导体衬底上的沟槽中的存储器件的反向沟道效应。在另一个实施例中，热氧化工艺通过氧化掩埋介电层和绝缘体上半导体衬底的至少一个半导体层之间的键合界面来增加绝缘体衬底上键合的半导体的掩埋介电层的厚度。掩埋介电层的增加的厚度可以减少在具有沟槽存储器结构的衬底上形成的器件中的反向沟道效应。

7. 发明申请

US20110042731A1 STRUCTURE AND METHOD OF FORMING ENHANCED ARRAY DEVICE ISOLATION FOR IMPLANTED PLATE EDRAM 有权
标题翻译：形成增强板阵列隔离装置的结构和方法
公开(公告)号：US20110042731A1
公开(公告)日：2011-02-24
申请号：US12545116
申请日：2009-08-21
申请人： Herbert L. Ho , Naoyoshi Kusaba , Karen A. Nummy , Carl J. Radens , Ravi M. Todi , Geng Wang
发明人： Herbert L. Ho , Naoyoshi Kusaba , Karen A. Nummy , Carl J. Radens , Ravi M. Todi , Geng Wang
IPC分类号： H01L27/108 , H01L21/28 , H01L21/8242
CPC分类号： H01L27/10823 , H01L21/76264 , H01L21/84 , H01L27/10829 , H01L27/1087 , H01L27/10897 , H01L27/1203 , H01L29/0653 , H01L29/66181
摘要： A method for forming a memory device in a semiconductor on insulator substrate is provided, in which a protective oxide that is present on the sidewalls of the trench protects the first semiconductor layer, i.e., SOI layer, of the semiconductor on insulator substrate during bottle etching of the trench. In one embodiment, the protective oxide reduces back channel effects of the transistors to the memory devices in the trench that are formed in the semiconductor on insulator substrate. In another embodiment, a thermal oxidation process increases the thickness of the buried dielectric layer of a bonded semiconductor on insulator substrate by oxidizing the bonded interface between the buried dielectric layer and at least one semiconductor layers of the semiconductor on insulator substrate. The increased thickness of the buried dielectric layer may reduce back channel effects in devices formed on the substrate having trench memory structures.
摘要翻译：提供了一种在半导体绝缘体衬底上形成存储器件的方法，其中存在于沟槽的侧壁上的保护氧化物在瓶蚀刻期间保护半导体绝缘体衬底上的第一半导体层即SOI层的沟槽。在一个实施例中，保护氧化物减少晶体管对形成在绝缘体上半导体衬底上的沟槽中的存储器件的反向沟道效应。在另一个实施例中，热氧化工艺通过氧化掩埋介电层和绝缘体上半导体衬底的至少一个半导体层之间的键合界面来增加绝缘体衬底上键合的半导体的掩埋介电层的厚度。掩埋介电层的增加的厚度可以减少在具有沟槽存储器结构的衬底上形成的器件中的反向沟道效应。

8. 发明授权

US08642440B2 Capacitor with deep trench ion implantation 失效
标题翻译：具有深沟槽离子注入的电容器
公开(公告)号：US08642440B2
公开(公告)日：2014-02-04
申请号：US13279877
申请日：2011-10-24
申请人： Chengwen Pei , Roger Allen Booth, Jr. , Herbert Lei Ho , Naoyoshi Kusaba
发明人： Chengwen Pei , Roger Allen Booth, Jr. , Herbert Lei Ho , Naoyoshi Kusaba
IPC分类号： H01L21/20
CPC分类号： H01L29/945 , H01L29/66181
摘要： An improved semiconductor capacitor and method of fabrication is disclosed. Embodiments utilize a deep trench which is then processed by performing a pre-amorphous implant on the trench interior to transform the interior surface of the trench to amorphous silicon which eliminates the depletion region that can degrade capacitor performance.
摘要翻译：公开了一种改进的半导体电容器和制造方法。实施例利用深沟槽，然后通过在沟槽内部执行预非晶体植入来将沟槽的内表面转变为非晶硅来处理，以消除可能降低电容器性能的耗尽区。

9. 发明申请

US20120083092A1 STRUCTURE AND METHOD OF FORMING ENHANCED ARRAY DEVICE ISOLATION FOR IMPLANTED PLATE EDRAM 有权
标题翻译：形成增强板阵列隔离装置的结构和方法
公开(公告)号：US20120083092A1
公开(公告)日：2012-04-05
申请号：US13323033
申请日：2011-12-12
申请人： Herbert L. Ho , Naoyoshi Kusaba , Karen A. Nummy , Carl J. Radens , Ravi M. Todi , Geng Wang
发明人： Herbert L. Ho , Naoyoshi Kusaba , Karen A. Nummy , Carl J. Radens , Ravi M. Todi , Geng Wang
IPC分类号： H01L21/02
CPC分类号： H01L27/10823 , H01L21/76264 , H01L21/84 , H01L27/10829 , H01L27/1087 , H01L27/10897 , H01L27/1203 , H01L29/0653 , H01L29/66181
摘要： A method for forming a memory device in a semiconductor on insulator substrate is provided, in which a protective oxide that is present on the sidewalls of the trench protects the first semiconductor layer, i.e., SOI layer, of the semiconductor on insulator substrate during bottle etching of the trench. In one embodiment, the protective oxide reduces back channel effects of the transistors to the memory devices in the trench that are formed in the semiconductor on insulator substrate. In another embodiment, a thermal oxidation process increases the thickness of the buried dielectric layer of a bonded semiconductor on insulator substrate by oxidizing the bonded interface between the buried dielectric layer and at least one semiconductor layers of the semiconductor on insulator substrate. The increased thickness of the buried dielectric layer may reduce back channel effects in devices formed on the substrate having trench memory structures.
摘要翻译：提供了一种在半导体绝缘体衬底上形成存储器件的方法，其中存在于沟槽的侧壁上的保护氧化物在瓶蚀刻期间保护半导体绝缘体衬底上的第一半导体层即SOI层的沟槽。在一个实施例中，保护氧化物减少晶体管对形成在绝缘体上半导体衬底上的沟槽中的存储器件的反向沟道效应。在另一个实施例中，热氧化工艺通过氧化掩埋介电层和绝缘体上半导体衬底的至少一个半导体层之间的键合界面来增加绝缘体衬底上键合的半导体的掩埋介电层的厚度。掩埋介电层的增加的厚度可以减少在具有沟槽存储器结构的衬底上形成的器件中的反向沟道效应。

10. 发明授权

US09059320B2 Structure and method of forming enhanced array device isolation for implanted plate EDRAM 有权
标题翻译：形成植入板EDRAM的增强阵列器件隔离的结构和方法
公开(公告)号：US09059320B2
公开(公告)日：2015-06-16
申请号：US13408187
申请日：2012-02-29
申请人： Herbert L. Ho , Naoyoshi Kusaba , Karen A. Nummy , Carl J. Radens , Ravi M. Todi , Geng Wang
发明人： Herbert L. Ho , Naoyoshi Kusaba , Karen A. Nummy , Carl J. Radens , Ravi M. Todi , Geng Wang
IPC分类号： H01L27/108 , H01L29/94 , H01L21/84 , H01L21/762 , H01L29/66
CPC分类号： H01L27/10823 , H01L21/76264 , H01L21/84 , H01L27/10829 , H01L27/1087 , H01L27/10897 , H01L27/1203 , H01L29/0653 , H01L29/66181
摘要： A memory device is provided including a semiconductor on insulator (SOI) substrate including a first semiconductor layer atop a buried dielectric layer, wherein the buried dielectric layer is overlying a second semiconductor layer. A capacitor is present in a trench, wherein the trench extends from an upper surface of the first semiconductor layer through the buried dielectric layer and extends into the second semiconductor layer. A protective oxide is present in a void that lies adjacent the first semiconductor layer, and a pass transistor is present atop the semiconductor on insulator substrate in electrical communication with the capacitor.
摘要翻译：提供了一种存储器件，其包括绝缘体上半导体（SOI）衬底，其包括位于掩埋介电层顶部的第一半导体层，其中所述掩埋介电层覆盖在第二半导体层上。电容器存在于沟槽中，其中沟槽从第一半导体层的上表面延伸穿过埋入介质层并延伸到第二半导体层。保护性氧化物存在于位于第一半导体层附近的空隙中，并且传导晶体管存在于与电容器电连通的绝缘体上半导体衬底上。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式