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1. 发明申请

US20060189063A1 Insulated gate power semiconductor devices 失效
标题翻译：绝缘栅功率半导体器件
公开(公告)号：US20060189063A1
公开(公告)日：2006-08-24
申请号：US10564214
申请日：2003-07-12
申请人： Raymond Hueting , Erwin Hijzen , Michael In't Zandt
发明人： Raymond Hueting , Erwin Hijzen , Michael In't Zandt
IPC分类号： H01L21/8238 , H01L29/76
CPC分类号： H01L29/7813 , H01L29/4236 , H01L29/42368 , H01L29/4238
摘要： A trench-gate semiconductor device (100) has a trench network (STR1), ITR1) surrounding a plurality of closed transistor cells (TCS). The trench network comprises segment trench regions (STR1) adjacent sides of the transistor cells (TCS) and intersection trench regions (ITR1) adjacent corners of the transistor cells. As shown in FIG. 16 which is a section view along the line II-II of FIG. 11, the intersection trench regions (ITR1) each include insulating material (21D) which extends from the bottom of the intersection trench region with a thickness which is greater than the thickness of the insulating material (21B1) at the bottom of the segment trench regions (STR1). The greater thickness of the insulating material (21D) extending from the bottom of the intersection trench regions (ITR1) is effective to increase the drain-source reverse breakdown voltage of the device (100). The insulating material (21D) which extends from the bottom of each intersection trench region (ITR1) may extend upwards to thicken the insulating material at the corners of the cells (TCS) over at least part of the vertical extent of the channel-accommodating body region (23) so as to increase the threshold voltage of the device.
摘要翻译：沟槽栅极半导体器件（100）具有围绕多个闭合晶体管单元（TCS）的沟槽网络（STR1），ITR 1）。沟槽网络包括晶体管单元（TCS）的相邻侧的分段沟槽区域（STR 1）和晶体管单元的相邻角的交叉沟槽区域（ITR 1）。如图所示。图16是沿图1的II-II线的剖视图。如图11所示，交点沟槽区域（ITR 1）各自包括从交叉沟槽区域的底部延伸的绝缘材料（21D），其厚度大于绝缘材料（21B 1）的底部的厚度段沟槽区域（STR 1）。从交叉沟槽区域（ITR 1）的底部延伸的绝缘材料（21D）的较大厚度对于增加器件（100）的漏 - 源反向击穿电压是有效的。从每个交叉沟槽区域（ITR 1）的底部延伸的绝缘材料（21D）可以向上延伸，以在通道的垂直方向的至少一部分的至少部分的细胞（TCS）上增厚绝缘材料，容纳体区域（23），以增加装置的阈值电压。

2. 发明申请

US20060205222A1 Manufacture of trench-gate semiconductor devices 有权
标题翻译：沟槽栅半导体器件的制造
公开(公告)号：US20060205222A1
公开(公告)日：2006-09-14
申请号：US10538214
申请日：2003-12-08
申请人： Michael In't Zandt , Erwin Hijzen
发明人： Michael In't Zandt , Erwin Hijzen
IPC分类号： H01L21/8242 , H01L21/311
CPC分类号： H01L29/7813 , H01L29/42368 , H01L29/4238 , H01L29/511 , H01L29/513 , H01L29/518
摘要： A method of manufacturing a trench-gate semiconductor device (1), the method including forming trenches (20) in a semiconductor body (10) in an active transistor cell area of the device, the trenches (20) each having a trench bottom and trench sidewalls, and providing silicon oxide gate insulation (21) in the trenches such that the gate insulation (33) at the trench bottoms is thicker than the gate insulation (21) at the trench sidewalls in order to reduce the gate-drain capacitance of the device. The method includes, after forming the trenches (20), the steps of: (a) forming a silicon oxide layer (21) at the trench bottoms and trench sidewalls; (b) depositing a layer of doped polysilicon (31) adjacent the trench bottoms and trench side walls; (c) forming silicon nitride spacers (32) on the doped polysilicon (21) adjacent the trench sidewalls leaving the doped polysilicon exposed at the trench bottoms; (d) thermally oxidising the exposed doped polysilicon to grow said thicker gate insulation (33) at the trench bottoms; (e) removing the silicon nitride spacers (32); and (f) depositing gate conductive material (34) within the trenches to form a gate electrode for the device. The final thickness of the thicker gate insulation (33) at the trench bottoms is well controlled by the thickness of the layer of doped polysilicon (31) deposited in step (b). Also the doped (preferably greater than 5 e 19 cm-3) polysilicon oxidises fast at low temperatures (preferably 700-800° C.), reducing the risk of diffusing (e.g. p body) implantations present in the device at that stage.
摘要翻译：一种制造沟槽栅极半导体器件（1）的方法，所述方法包括在器件的有源晶体管单元区域中的半导体本体（10）中形成沟槽（20），所述沟槽（20）各自具有沟槽底部和沟槽侧壁，并且在沟槽中提供氧化硅栅极绝缘体（21），使得在沟槽底部处的栅极绝缘体（33）比沟槽侧壁处的栅极绝缘体（21）更厚，以便降低栅极 - 漏极电容装置。该方法包括在形成沟槽（20）之后的步骤：（a）在沟槽底部和沟槽侧壁处形成氧化硅层（21）; （b）在沟槽底部和沟槽侧壁附近沉积一层掺杂多晶硅（31）; （c）在与沟槽侧壁相邻的掺杂多晶硅（21）上形成氮化硅间隔物（32），留下在沟槽底部暴露的掺杂多晶硅; （d）热氧化暴露的掺杂多晶硅以在沟槽底部生长所述较厚的栅极绝缘体（33）; （e）去除氮化硅间隔物（32）; 和（f）在所述沟槽内淀积栅极导电材料（34）以形成所述器件的栅电极。沟槽底部较厚的栅极绝缘体（33）的最终厚度由步骤（b）中沉积的掺杂多晶硅层（31）的厚度很好地控制。此外，掺杂（优选大于5埃19厘米3）的多晶硅在低温（优选700-800℃）下快速氧化，降低了在该阶段存在于器件中的扩散（例如p体）植入的风险。

3. 发明申请

US20050156232A1 Edge termination in MOS transistors 失效
公开(公告)号：US20050156232A1
公开(公告)日：2005-07-21
申请号：US11066408
申请日：2005-02-25
申请人： Raymond Hueting , Erwin Hijzen , Michael In't Zandt
发明人： Raymond Hueting , Erwin Hijzen , Michael In't Zandt
IPC分类号： H01L29/06 , H01L29/40 , H01L29/423 , H01L29/739 , H01L29/78 , H01L29/76 , H01L21/336
CPC分类号： H01L29/7813 , H01L29/0696 , H01L29/402 , H01L29/407 , H01L29/4236 , H01L29/4238 , H01L29/7397 , H01L29/7811
摘要： A RESURF trench gate MOSFET has a sufficiently small pitch (close spacing of neighbouring trenches) that intermediate areas of the drain drift region are depleted in the blocking condition of the MOSFET. However, premature breakdown can still occur in this known device structure at the perimeter/edge of the active device area and/or adjacent the gate bondpad. To counter premature breakdown, the invention adopts two principles: the gate bondpad is either connected to an underlying stripe trench network surrounded by active cells, or is directly on top of the active cells, and a compatible 2D edge termination scheme is provided around the RESURF active device area. These principles can be implemented in various cellular layouts e.g. a concentric annular device geometry, which may be circular or rectangular or ellipsoidal, in the active area and in the edge termination, or a device array of such concentric hexagonal or circular stripe cells, or a device array of square active cells with stripe edge cells, or a device array of hexagonal active cells with an edge termination of hexagonal edge cells.

4. 发明申请

US20060049453A1 Vertical insulated gate transistor and manufacturing method 有权
标题翻译：垂直绝缘栅晶体管及其制造方法
公开(公告)号：US20060049453A1
公开(公告)日：2006-03-09
申请号：US10538216
申请日：2003-12-08
申请人： Jurriaan Schmitz , Raymond Hueting , Erwin Hijzen , Andreas Montree , Michael In't Zandt , Gerrit Koops
发明人： Jurriaan Schmitz , Raymond Hueting , Erwin Hijzen , Andreas Montree , Michael In't Zandt , Gerrit Koops
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7813 , H01L29/4236 , H01L29/42368 , H01L29/66666 , H01L29/7827
摘要： A vertical insulated gate transistor is manufactured by providing a trench (26) extending through a source layer (8) and a channel layer (6) towards a drain layer (2). A spacer etch is used to form gate portions (20) along the trench side walls, a dielectric material (30) is filled into the trench between the sidewalls gate portions (20), and a gate electrical connection layer (30) is formed at the top of the trench electrically connecting the gate portions (20) across the trench.
摘要翻译：通过向漏极层（2）提供延伸穿过源极层（8）和沟道层（6）的沟槽（26）来制造垂直绝缘栅极晶体管。使用间隔物蚀刻沿着沟槽侧壁形成栅极部分（20），电介质材料（30）被填充到侧壁栅极部分（20）之间的沟槽中，并且栅极电连接层（30）形成在所述沟槽的顶部电连接所述栅极部分（20）穿过所述沟槽。

5. 发明申请

US20060017097A1 Method of manufacturing a trench-gate semiconductor device 有权
标题翻译：制造沟槽栅半导体器件的方法
公开(公告)号：US20060017097A1
公开(公告)日：2006-01-26
申请号：US10538212
申请日：2003-12-08
申请人： Erwin Hijzen , Raymond Hueting , Michael In't Zandt
发明人： Erwin Hijzen , Raymond Hueting , Michael In't Zandt
IPC分类号： H01L21/336 , H01L29/80 , H01L29/94 , H01L21/3205
CPC分类号： H01L29/7813 , H01L21/28202 , H01L21/28211 , H01L29/42368 , H01L29/4238 , H01L29/511 , H01L29/518
摘要： A method of making a trench MOSFET includes forming a nitride liner 50 on the sidewalls 28 of a trench and a plug of doped polysilicon 26 at the bottom of a trench. The plug of polysilicon 26 may then be oxidised to form a thick oxide plug 30 at the bottom of the trench whilst the nitride liner 50 protects the sidewalls 28 from oxidation. This forms a thick oxide plug at the bottom of the trench thereby reducing capacitance between gate and drain.
摘要翻译：制造沟槽MOSFET的方法包括在沟槽的侧壁28上形成氮化物衬垫50，在沟槽的底部形成掺杂多晶硅26的插塞。然后可以将多晶硅26的塞子氧化以在沟槽的底部形成厚的氧化物塞30，而氮化物衬垫50保护侧壁28免受氧化。这在沟槽的底部形成厚的氧化物塞，从而减小栅极和漏极之间的电容。

6. 发明授权

US08476675B2 Semiconductor device and method of manufacture thereof 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08476675B2
公开(公告)日：2013-07-02
申请号：US12918524
申请日：2009-02-26
申请人： Philippe Meunier-Beillard , Johannes J. T. M. Donkers , Erwin Hijzen
发明人： Philippe Meunier-Beillard , Johannes J. T. M. Donkers , Erwin Hijzen
IPC分类号： H01L29/66
CPC分类号： H01L21/8249 , H01L27/0623 , H01L29/0649 , H01L29/0821 , H01L29/1004 , H01L29/165 , H01L29/42304 , H01L29/456 , H01L29/66242 , H01L29/7378
摘要： A semiconductor device (10) comprising a bipolar transistor and a field 5 effect transistor within a semiconductor body (1) comprising a projecting mesa (5) within which are at least a portion of a collector region (22c and 22d) and a base region (33c) of the bipolar transistor. The bipolar transistor is provided with an insulating cavity (92b) provided in the collector region (22c and 22d). The insulating cavity (92b) may be provided by providing a layer (33a) in the collector region (22c), creating an access path, for example by selectively etching polysilicon towards monocrystalline, and removing a portion of the layer (33a) to provide the cavity using the access path. The layer (33a) provided in the collector region may be of SiGe:C. By blocking diffusion from the base region the insulating cavity (92b) provides a reduction in the base collector capacitance and can be described as defining the base contact.
摘要翻译：一种半导体器件（10），包括在半导体本体（1）内的双极晶体管和场效应晶体管，包括突出的台面（5），其中集电极区域（22c和22d）的至少一部分和基极区域（33c）。双极晶体管设置有设置在集电区域（22c和22d）中的绝缘腔（92b）。可以通过在集电极区域（22c）中设置层（33a）来提供绝缘腔（92b），从而产生存取路径，例如通过选择性地将多晶硅蚀刻成单晶，并去除层（33a）的一部分以提供使用进入路径的空腔。设置在集电区域中的层（33a）可以是SiGe：C。通过阻挡从基极区域的扩散，绝缘腔（92b）提供基极集电极电容的减小，并且可以被描述为限定基极接触。

7. 发明授权

US07939416B2 Method of making bipolar transistor 有权
标题翻译：制造双极晶体管的方法
公开(公告)号：US07939416B2
公开(公告)日：2011-05-10
申请号：US12935924
申请日：2009-03-30
申请人： Sebastien Nuttinck , Erwin Hijzen , Johannes J. T. M. Donkers , Guillaume L. R. Boccardi
发明人： Sebastien Nuttinck , Erwin Hijzen , Johannes J. T. M. Donkers , Guillaume L. R. Boccardi
IPC分类号： H01L21/8222
CPC分类号： H01L29/66242 , H01L21/8249 , H01L29/0634 , H01L29/0692 , H01L29/66287 , H01L29/66795 , H01L29/732 , H01L29/7371
摘要： A method of manufacturing a bipolar transistor is compatible with FinFET processing. A collector region (18) is formed and patterned, base contact regions (26) formed on either side, and a gap formed between the base contact region. A base (28), spacers (30) and an emitter (32) are formed in the gap.
摘要翻译：制造双极晶体管的方法与FinFET处理兼容。形成集电极区域（18）并构图，形成在两侧的基极接触区域（26）和形成在基极接触区域之间的间隙。在间隙中形成基座（28），间隔件（30）和发射极（32）。

8. 发明授权

US07867864B2 Method of manufacturing a semiconductor device and semiconductor device obtained with such a method 有权
标题翻译：利用这种方法制造半导体器件和半导体器件的制造方法
公开(公告)号：US07867864B2
公开(公告)日：2011-01-11
申请号：US12160210
申请日：2007-01-04
申请人： Sebastien Nuttinck , Giberto Curatola , Erwin Hijzen , Philippe Meunier-Beillard
发明人： Sebastien Nuttinck , Giberto Curatola , Erwin Hijzen , Philippe Meunier-Beillard
IPC分类号： H01L21/336
CPC分类号： H01L29/0653 , H01L21/02381 , H01L21/02532 , H01L21/0262 , H01L29/66545 , H01L29/66628 , H01L29/66636 , H01L29/7834
摘要： The invention relates to a method of manufacturing a semiconductor device comprising a field effect transistor, in which method a semiconductor body of silicon with a substrate is provided at a surface thereof with a source region and a drain region of a first conductivity type which are situated above a buried isolation region and with a channel region, between the source and drain regions, of a second conductivity type, opposite to the first conductivity type, and with a gate region separated from the surface of the semiconductor body by a gate dielectric and situated above the channel region, wherein a mesa is formed in the semiconductor body in which the channel region is formed and wherein the source and drain regions are formed on both sides of the mesa in a semiconductor region that is formed using epitaxial growth, the source and drain regions thereby contacting the channel region.
摘要翻译：本发明涉及一种制造半导体器件的方法，该半导体器件包括场效应晶体管，其中在其表面上提供具有衬底的硅半导体本体，其具有位于第一导电类型的源区和漏区位于源极和漏极区之间的与第一导电类型相反的第二导电类型的沟道区，以及通过栅极电介质与半导体本体的表面分离的栅极区，位于在沟道区域的上方，其中在形成沟道区的半导体本体中形成台面，并且其中源极和漏极区域形成在使用外延生长形成的半导体区域中的台面的两侧，源极和漏极区域漏区，从而接触沟道区。

9. 发明申请

US20100289022A1 METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE OBTAINED WITH SUCH A METHOD 有权
标题翻译：制造半导体器件的方法和采用这种方法获得的半导体器件
公开(公告)号：US20100289022A1
公开(公告)日：2010-11-18
申请号：US12094303
申请日：2006-10-29
申请人： Joost Melai , Erwin Hijzen , Philippe Meunier-Beillard , Johannes J.T.M. Donkers
发明人： Joost Melai , Erwin Hijzen , Philippe Meunier-Beillard , Johannes J.T.M. Donkers
IPC分类号： H01L29/73 , H01L21/331 , H01L29/02
CPC分类号： H01L29/66242 , H01L29/66287
摘要： The invention relates to a method of manufacturing a semiconductor device (10) with a substrate (11) and a semiconductor body (12) which is provided with at least one bipolar transistor having an emitter region (1), a base region (2) and a collector region (3), wherein in the semiconductor body (12) a first semiconductor region (13) is formed that forms one (3) of the collector and emitter regions (1,3) and on the surface of the semiconductor body (12) a stack of layers is formed comprising a first insulating layer (4), a polycrystalline semiconductor layer (5) and a second insulating layer (6) in which stack an opening (7) is formed, after which by non-selective epitaxial growth a further semiconductor layer (22) is deposited of which a monocrystalline horizontal part on the bottom of the opening (7) forms the base region (2) and of which a polycrystalline vertical part (2A) on a side face of the opening (7) is connected to the polycrystalline semiconductor layer (5), after which spacers (S) are formed parallel to the side face of the opening (7) and a second semiconductor region (31) is formed between said spacers (S) forming the other one (1) of the emitter and collector regions (1,3). According to the invention the above method is characterized in that before the further semiconductor layer (22) is deposited, the second insulating layer (6) is provided with an end portion (6A) that viewed in projection overhangs an end portion (5A) of the underlying semiconductor layer (5). In this way bipolar transistor devices can be obtained with good high frequency properties in a cost effective manner.
摘要翻译：本发明涉及一种制造半导体器件（10）的方法，所述半导体器件（10）具有衬底（11）和半导体本体（12），所述半导体器件（12）具有至少一个具有发射极区域（1），基极区域（2）和集电极区域（3），其中在所述半导体本体（12）中形成第一半导体区域（13），所述第一半导体区域形成所述集电极和发射极区域（1,3）中的一个（3）并且在所述半导体主体（12）形成一叠层，其包括形成有开口（7）的第一绝缘层（4），多晶半导体层（5）和第二绝缘层（6），之后通过非选择性外延生长沉积另外的半导体层（22），其中开口（7）的底部上的单晶水平部分形成基部区域（2），并且在该开口的侧面上具有多晶垂直部分（2A）（7）连接到多晶半导体层（5），之后是间隔（S）形成为平行于开口（7）的侧面，并且在形成发射极和集电极区域（1,3）的另一个（1）的所述间隔物（S）之间形成第二半导体区域（31））。根据本发明，上述方法的特征在于，在沉积另外的半导体层（22）之前，第二绝缘层（6）设置有端部（6A），其从突出部分观察到突出部分底层半导体层（5）。以这种方式，可以以成本有效的方式获得具有良好高频特性的双极晶体管器件。

10. 发明申请

US20100068863A1 Method of Manufacturing a Bipolar Transistor and Bipolar Transistor Obtained Therewith 有权
标题翻译：制造双极晶体管和双极晶体管的方法
公开(公告)号：US20100068863A1
公开(公告)日：2010-03-18
申请号：US12306653
申请日：2007-06-12
申请人： Erwin Hijzen
发明人： Erwin Hijzen
IPC分类号： H01L21/331
CPC分类号： H01L29/66287 , H01L29/66242
摘要： The invention relates to a method of manufacturing a semiconductor device (10) comprising a substrate (12) and a silicon semiconductor body (11) and comprising a bipolar transistor with an emitter region (1) of a first conductivity type, a base region (2) of a second conductivity type opposite to the first conductivity type, and a collector region (3) of the first conductivity type, on the surface of the semiconductor body (11) in which the collector region (3) is formed at least an epitaxial semiconductor layer (20,21,22) being deposited in which the base region (2) is formed, on top of this an etch stop layer (15) being deposited on which a silicon low-crystalline semiconductor layer (24) is deposited in which a connection zone of the base region (2) is formed and in which at the location of an emitter region (1) to be formed an opening (7) is provided running up to the etch stop layer (15), a portion of the etch stop layer (15) covering the opening (7) being removed by means of etching and also an adjoining portion of the etch stop layer (15), a hollow being created underneath the silicon low-crystalline semiconductor layer (24) adjoining and connected the opening (7), whereinafter a high-crystalline semiconductor layer (5) is formed within the hollow. In a method according to the invention the formation of the high-crystalline semiconductor layer (5) is carried out in such a way that a part of the surface of the semiconductor body (11) adjoining the opening (7) is kept free from the high-crystalline semiconductor layer (5). In this way a high-quality device (10) is obtained in easy manner. The relevant surface is kept free using a cover layer (6) or in a preferred manner even without the use of such a layer.
摘要翻译：本发明涉及一种制造半导体器件（10）的方法，该半导体器件（10）包括衬底（12）和硅半导体本体（11），并且包括具有第一导电类型的发射极区域（1），基极区域 2）与第一导电类型相反的第二导电类型和第一导电类型的集电极区域（3），其中集电区域（3）至少形成在半导体本体（11）的表面上，外延半导体层（20,21,22）被沉积在其中形成有基极区域（2）的上方，沉积有沉积有硅低温半导体层（24）的蚀刻停止层（15）在其中形成基部区域（2）的连接区域，并且其中在要形成开口（7）的发射极区域（1）的位置处设置有延伸到蚀刻停止层（15）的部分通过蚀刻去除覆盖开口（7）的蚀刻停止层（15）以及蚀刻停止层（15）的相邻部分，在邻接和连接开口（7）的硅低温半导体层（24）下方形成中空，其后，高结晶半导体层（5）为形成在空心中。在根据本发明的方法中，高结晶半导体层（5）的形成是这样一种方式进行的：半导体本体（11）的与开口（7）相邻的表面的一部分保持与高结晶半导体层（5）。以这种方式，以容易的方式获得了高质量的装置（10）。使用覆盖层（6）或以优选的方式即使不使用这种层也可以使相关表面保持自由。

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