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1. 发明申请

US20060049453A1 Vertical insulated gate transistor and manufacturing method 有权
标题翻译：垂直绝缘栅晶体管及其制造方法
公开(公告)号：US20060049453A1
公开(公告)日：2006-03-09
申请号：US10538216
申请日：2003-12-08
申请人： Jurriaan Schmitz , Raymond Hueting , Erwin Hijzen , Andreas Montree , Michael In't Zandt , Gerrit Koops
发明人： Jurriaan Schmitz , Raymond Hueting , Erwin Hijzen , Andreas Montree , Michael In't Zandt , Gerrit Koops
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7813 , H01L29/4236 , H01L29/42368 , H01L29/66666 , H01L29/7827
摘要： A vertical insulated gate transistor is manufactured by providing a trench (26) extending through a source layer (8) and a channel layer (6) towards a drain layer (2). A spacer etch is used to form gate portions (20) along the trench side walls, a dielectric material (30) is filled into the trench between the sidewalls gate portions (20), and a gate electrical connection layer (30) is formed at the top of the trench electrically connecting the gate portions (20) across the trench.
摘要翻译：通过向漏极层（2）提供延伸穿过源极层（8）和沟道层（6）的沟槽（26）来制造垂直绝缘栅极晶体管。使用间隔物蚀刻沿着沟槽侧壁形成栅极部分（20），电介质材料（30）被填充到侧壁栅极部分（20）之间的沟槽中，并且栅极电连接层（30）形成在所述沟槽的顶部电连接所述栅极部分（20）穿过所述沟槽。

2. 发明申请

US20060189063A1 Insulated gate power semiconductor devices 失效
标题翻译：绝缘栅功率半导体器件
公开(公告)号：US20060189063A1
公开(公告)日：2006-08-24
申请号：US10564214
申请日：2003-07-12
申请人： Raymond Hueting , Erwin Hijzen , Michael In't Zandt
发明人： Raymond Hueting , Erwin Hijzen , Michael In't Zandt
IPC分类号： H01L21/8238 , H01L29/76
CPC分类号： H01L29/7813 , H01L29/4236 , H01L29/42368 , H01L29/4238
摘要： A trench-gate semiconductor device (100) has a trench network (STR1), ITR1) surrounding a plurality of closed transistor cells (TCS). The trench network comprises segment trench regions (STR1) adjacent sides of the transistor cells (TCS) and intersection trench regions (ITR1) adjacent corners of the transistor cells. As shown in FIG. 16 which is a section view along the line II-II of FIG. 11, the intersection trench regions (ITR1) each include insulating material (21D) which extends from the bottom of the intersection trench region with a thickness which is greater than the thickness of the insulating material (21B1) at the bottom of the segment trench regions (STR1). The greater thickness of the insulating material (21D) extending from the bottom of the intersection trench regions (ITR1) is effective to increase the drain-source reverse breakdown voltage of the device (100). The insulating material (21D) which extends from the bottom of each intersection trench region (ITR1) may extend upwards to thicken the insulating material at the corners of the cells (TCS) over at least part of the vertical extent of the channel-accommodating body region (23) so as to increase the threshold voltage of the device.
摘要翻译：沟槽栅极半导体器件（100）具有围绕多个闭合晶体管单元（TCS）的沟槽网络（STR1），ITR 1）。沟槽网络包括晶体管单元（TCS）的相邻侧的分段沟槽区域（STR 1）和晶体管单元的相邻角的交叉沟槽区域（ITR 1）。如图所示。图16是沿图1的II-II线的剖视图。如图11所示，交点沟槽区域（ITR 1）各自包括从交叉沟槽区域的底部延伸的绝缘材料（21D），其厚度大于绝缘材料（21B 1）的底部的厚度段沟槽区域（STR 1）。从交叉沟槽区域（ITR 1）的底部延伸的绝缘材料（21D）的较大厚度对于增加器件（100）的漏 - 源反向击穿电压是有效的。从每个交叉沟槽区域（ITR 1）的底部延伸的绝缘材料（21D）可以向上延伸，以在通道的垂直方向的至少一部分的至少部分的细胞（TCS）上增厚绝缘材料，容纳体区域（23），以增加装置的阈值电压。

3. 发明申请

US20050156232A1 Edge termination in MOS transistors 失效
公开(公告)号：US20050156232A1
公开(公告)日：2005-07-21
申请号：US11066408
申请日：2005-02-25
申请人： Raymond Hueting , Erwin Hijzen , Michael In't Zandt
发明人： Raymond Hueting , Erwin Hijzen , Michael In't Zandt
IPC分类号： H01L29/06 , H01L29/40 , H01L29/423 , H01L29/739 , H01L29/78 , H01L29/76 , H01L21/336
CPC分类号： H01L29/7813 , H01L29/0696 , H01L29/402 , H01L29/407 , H01L29/4236 , H01L29/4238 , H01L29/7397 , H01L29/7811
摘要： A RESURF trench gate MOSFET has a sufficiently small pitch (close spacing of neighbouring trenches) that intermediate areas of the drain drift region are depleted in the blocking condition of the MOSFET. However, premature breakdown can still occur in this known device structure at the perimeter/edge of the active device area and/or adjacent the gate bondpad. To counter premature breakdown, the invention adopts two principles: the gate bondpad is either connected to an underlying stripe trench network surrounded by active cells, or is directly on top of the active cells, and a compatible 2D edge termination scheme is provided around the RESURF active device area. These principles can be implemented in various cellular layouts e.g. a concentric annular device geometry, which may be circular or rectangular or ellipsoidal, in the active area and in the edge termination, or a device array of such concentric hexagonal or circular stripe cells, or a device array of square active cells with stripe edge cells, or a device array of hexagonal active cells with an edge termination of hexagonal edge cells.

4. 发明申请

US20060017097A1 Method of manufacturing a trench-gate semiconductor device 有权
标题翻译：制造沟槽栅半导体器件的方法
公开(公告)号：US20060017097A1
公开(公告)日：2006-01-26
申请号：US10538212
申请日：2003-12-08
申请人： Erwin Hijzen , Raymond Hueting , Michael In't Zandt
发明人： Erwin Hijzen , Raymond Hueting , Michael In't Zandt
IPC分类号： H01L21/336 , H01L29/80 , H01L29/94 , H01L21/3205
CPC分类号： H01L29/7813 , H01L21/28202 , H01L21/28211 , H01L29/42368 , H01L29/4238 , H01L29/511 , H01L29/518
摘要： A method of making a trench MOSFET includes forming a nitride liner 50 on the sidewalls 28 of a trench and a plug of doped polysilicon 26 at the bottom of a trench. The plug of polysilicon 26 may then be oxidised to form a thick oxide plug 30 at the bottom of the trench whilst the nitride liner 50 protects the sidewalls 28 from oxidation. This forms a thick oxide plug at the bottom of the trench thereby reducing capacitance between gate and drain.
摘要翻译：制造沟槽MOSFET的方法包括在沟槽的侧壁28上形成氮化物衬垫50，在沟槽的底部形成掺杂多晶硅26的插塞。然后可以将多晶硅26的塞子氧化以在沟槽的底部形成厚的氧化物塞30，而氮化物衬垫50保护侧壁28免受氧化。这在沟槽的底部形成厚的氧化物塞，从而减小栅极和漏极之间的电容。

5. 发明申请

US20060205222A1 Manufacture of trench-gate semiconductor devices 有权
标题翻译：沟槽栅半导体器件的制造
公开(公告)号：US20060205222A1
公开(公告)日：2006-09-14
申请号：US10538214
申请日：2003-12-08
申请人： Michael In't Zandt , Erwin Hijzen
发明人： Michael In't Zandt , Erwin Hijzen
IPC分类号： H01L21/8242 , H01L21/311
CPC分类号： H01L29/7813 , H01L29/42368 , H01L29/4238 , H01L29/511 , H01L29/513 , H01L29/518
摘要： A method of manufacturing a trench-gate semiconductor device (1), the method including forming trenches (20) in a semiconductor body (10) in an active transistor cell area of the device, the trenches (20) each having a trench bottom and trench sidewalls, and providing silicon oxide gate insulation (21) in the trenches such that the gate insulation (33) at the trench bottoms is thicker than the gate insulation (21) at the trench sidewalls in order to reduce the gate-drain capacitance of the device. The method includes, after forming the trenches (20), the steps of: (a) forming a silicon oxide layer (21) at the trench bottoms and trench sidewalls; (b) depositing a layer of doped polysilicon (31) adjacent the trench bottoms and trench side walls; (c) forming silicon nitride spacers (32) on the doped polysilicon (21) adjacent the trench sidewalls leaving the doped polysilicon exposed at the trench bottoms; (d) thermally oxidising the exposed doped polysilicon to grow said thicker gate insulation (33) at the trench bottoms; (e) removing the silicon nitride spacers (32); and (f) depositing gate conductive material (34) within the trenches to form a gate electrode for the device. The final thickness of the thicker gate insulation (33) at the trench bottoms is well controlled by the thickness of the layer of doped polysilicon (31) deposited in step (b). Also the doped (preferably greater than 5 e 19 cm-3) polysilicon oxidises fast at low temperatures (preferably 700-800° C.), reducing the risk of diffusing (e.g. p body) implantations present in the device at that stage.
摘要翻译：一种制造沟槽栅极半导体器件（1）的方法，所述方法包括在器件的有源晶体管单元区域中的半导体本体（10）中形成沟槽（20），所述沟槽（20）各自具有沟槽底部和沟槽侧壁，并且在沟槽中提供氧化硅栅极绝缘体（21），使得在沟槽底部处的栅极绝缘体（33）比沟槽侧壁处的栅极绝缘体（21）更厚，以便降低栅极 - 漏极电容装置。该方法包括在形成沟槽（20）之后的步骤：（a）在沟槽底部和沟槽侧壁处形成氧化硅层（21）; （b）在沟槽底部和沟槽侧壁附近沉积一层掺杂多晶硅（31）; （c）在与沟槽侧壁相邻的掺杂多晶硅（21）上形成氮化硅间隔物（32），留下在沟槽底部暴露的掺杂多晶硅; （d）热氧化暴露的掺杂多晶硅以在沟槽底部生长所述较厚的栅极绝缘体（33）; （e）去除氮化硅间隔物（32）; 和（f）在所述沟槽内淀积栅极导电材料（34）以形成所述器件的栅电极。沟槽底部较厚的栅极绝缘体（33）的最终厚度由步骤（b）中沉积的掺杂多晶硅层（31）的厚度很好地控制。此外，掺杂（优选大于5埃19厘米3）的多晶硅在低温（优选700-800℃）下快速氧化，降低了在该阶段存在于器件中的扩散（例如p体）植入的风险。

6. 发明申请

US20070126055A1 Trench insulated gate field effect transistor 审中-公开
标题翻译：沟槽绝缘栅场效应晶体管
公开(公告)号：US20070126055A1
公开(公告)日：2007-06-07
申请号：US10580625
申请日：2004-11-26
申请人： Raymond Hueting , Erwin Hijzen
发明人： Raymond Hueting , Erwin Hijzen
IPC分类号： H01L29/94
CPC分类号： H01L29/7813 , H01L29/0696 , H01L29/0847 , H01L29/0878 , H01L29/402 , H01L29/407 , H01L29/41766 , H01L29/42368 , H01L29/42376 , H01L29/4238 , H01L29/4916
摘要： The invention relates to a trench MOSFET with drain (8), drift (10) body (12) and source (14) regions. The drift region is doped to have a high concentration gradient. A field plate electrode (34) is provided adjacent to the drift region (10) and a gate electrode (32) next to the body region (12).
摘要翻译：本发明涉及一种具有漏极（8），漂移（10）主体（12）和源极（14）区域的沟槽MOSFET。漂移区被掺杂以具有高浓度梯度。邻近漂移区（10）设置的场板电极（34）和邻近体区（12）的栅电极（32）。

7. 发明申请

US20080029909A1 Nanowire Semiconductor Device 有权
标题翻译：纳米线半导体器件
公开(公告)号：US20080029909A1
公开(公告)日：2008-02-07
申请号：US11629657
申请日：2005-06-07
申请人： Erwin Hijzen , Erik Bakkers , Raymond Hueting , Abraham Balkenende
发明人： Erwin Hijzen , Erik Bakkers , Raymond Hueting , Abraham Balkenende
IPC分类号： H01L23/48 , H01L21/44
CPC分类号： H01L29/775 , B82Y10/00 , H01L21/0237 , H01L21/02458 , H01L21/02532 , H01L21/0254 , H01L21/02603 , H01L21/02639 , H01L21/02653 , H01L29/0665 , H01L29/0673 , H01L29/0676 , H01L29/267 , H01L29/66666 , H01L29/78642 , H01L29/78681 , H01L29/78696 , H01L29/861 , H01L29/872 , H01L51/0048 , H01L51/0052 , H01L51/0512 , H01L2924/0002 , Y10S977/70 , Y10S977/701 , Y10S977/707 , Y10S977/72 , Y10S977/721 , Y10S977/722 , Y10S977/723 , Y10S977/742 , Y10S977/762 , Y10S977/938 , H01L2924/00
摘要： Semiconductor devices are fabricated using nanowires 16. A conductive gate 22 may be used to control conduction along the nanowires 16, in which case one of the contacts is a drain 12 and the other a source 18. The nanowires 16 may be grown in a trench or through-hole 8 in a substrate 2 or in particular in epilayer 3 on substrate 2. The gate 22 may be provided only at one end of the nanowires 16. The nanowires 16 can be of the same material along their length; alternatively different materials can be used, especially different materials adjacent to the gate 22 and between the gate 22 and the base of the trench.
摘要翻译：使用纳米线16制造半导体器件。可以使用导电栅极22来控制沿着纳米线16的导通，在这种情况下，一个触点是漏极12，另一个是源极18。纳米线16可以在衬底2中的沟槽或通孔8中生长，或特别是在衬底2上的外延层3中生长。栅极22可以仅设置在纳米线16的一端。纳米线16沿其长度可以是相同的材料; 可以使用不同的材料，特别是与栅极22相邻并且在栅极22和沟槽的基底之间的不同材料。

8. 发明申请

US20070108515A1 Trench mosfet 有权
标题翻译：沟渠mosfet
公开(公告)号：US20070108515A1
公开(公告)日：2007-05-17
申请号：US10580619
申请日：2004-11-26
申请人： Raymond Hueting , Erwin Hijzen
发明人： Raymond Hueting , Erwin Hijzen
IPC分类号： H01L29/94
CPC分类号： H01L29/7813 , H01L29/0653 , H01L29/0696 , H01L29/0847 , H01L29/0878 , H01L29/42368 , H01L29/4238
摘要： The invention relates to a trench MOSFET with drain (8), dπ ft region (10) body (12) and source (14). In order to improve the figure of meπt for use of the MOSFET as control and sync FETs, the trench (20) is partially filled with dielectric (24) adjacent to the drift region (10) and a graded doping profile is used in the dπft region (10)
摘要翻译：本发明涉及一种具有漏极（8），dpi ft（10）主体（12）和源极（14）的沟槽MOSFET。为了改善使用MOSFET作为控制和同步FET的mepit图，沟槽（20）部分地被与漂移区（10）相邻的电介质（24）填充，并且在dpift中使用渐变掺杂分布地区（10）

9. 发明申请

US20060008991A1 Trenched semiconductor devices and their manufacture 失效
公开(公告)号：US20060008991A1
公开(公告)日：2006-01-12
申请号：US11220297
申请日：2005-09-02
申请人： Erwin Hijzen , Michael In'tZandt , Raymond Hueting
发明人： Erwin Hijzen , Michael In'tZandt , Raymond Hueting
IPC分类号： H01L21/336
CPC分类号： H01L29/7813 , H01L21/28211 , H01L29/4232 , H01L29/42368 , H01L29/4238 , H01L29/51 , H01L29/511 , H01L29/872
摘要： In semiconductor devices which include an insulated trench electrode (11) in a trench (20), for example, trench-gate field effect power transistors and trenched Schottky diodes, a cavity (23) is provided between the bottom (25) of the trench electrode (11) and the bottom (27) of the trench (20) to reduce the dielectric coupling between the trench electrode (11) and the body portion at the bottom (27) of the trench in a compact manner. In power transistors, the reduction in dielectric coupling reduces switching power losses, and in Schottky diodes, it enables the trench width to be reduced.

10. 发明授权

US08476675B2 Semiconductor device and method of manufacture thereof 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08476675B2
公开(公告)日：2013-07-02
申请号：US12918524
申请日：2009-02-26
申请人： Philippe Meunier-Beillard , Johannes J. T. M. Donkers , Erwin Hijzen
发明人： Philippe Meunier-Beillard , Johannes J. T. M. Donkers , Erwin Hijzen
IPC分类号： H01L29/66
CPC分类号： H01L21/8249 , H01L27/0623 , H01L29/0649 , H01L29/0821 , H01L29/1004 , H01L29/165 , H01L29/42304 , H01L29/456 , H01L29/66242 , H01L29/7378
摘要： A semiconductor device (10) comprising a bipolar transistor and a field 5 effect transistor within a semiconductor body (1) comprising a projecting mesa (5) within which are at least a portion of a collector region (22c and 22d) and a base region (33c) of the bipolar transistor. The bipolar transistor is provided with an insulating cavity (92b) provided in the collector region (22c and 22d). The insulating cavity (92b) may be provided by providing a layer (33a) in the collector region (22c), creating an access path, for example by selectively etching polysilicon towards monocrystalline, and removing a portion of the layer (33a) to provide the cavity using the access path. The layer (33a) provided in the collector region may be of SiGe:C. By blocking diffusion from the base region the insulating cavity (92b) provides a reduction in the base collector capacitance and can be described as defining the base contact.
摘要翻译：一种半导体器件（10），包括在半导体本体（1）内的双极晶体管和场效应晶体管，包括突出的台面（5），其中集电极区域（22c和22d）的至少一部分和基极区域（33c）。双极晶体管设置有设置在集电区域（22c和22d）中的绝缘腔（92b）。可以通过在集电极区域（22c）中设置层（33a）来提供绝缘腔（92b），从而产生存取路径，例如通过选择性地将多晶硅蚀刻成单晶，并去除层（33a）的一部分以提供使用进入路径的空腔。设置在集电区域中的层（33a）可以是SiGe：C。通过阻挡从基极区域的扩散，绝缘腔（92b）提供基极集电极电容的减小，并且可以被描述为限定基极接触。

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