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1. 发明授权

US07939416B2 Method of making bipolar transistor 有权
标题翻译：制造双极晶体管的方法
公开(公告)号：US07939416B2
公开(公告)日：2011-05-10
申请号：US12935924
申请日：2009-03-30
申请人： Sebastien Nuttinck , Erwin Hijzen , Johannes J. T. M. Donkers , Guillaume L. R. Boccardi
发明人： Sebastien Nuttinck , Erwin Hijzen , Johannes J. T. M. Donkers , Guillaume L. R. Boccardi
IPC分类号： H01L21/8222
CPC分类号： H01L29/66242 , H01L21/8249 , H01L29/0634 , H01L29/0692 , H01L29/66287 , H01L29/66795 , H01L29/732 , H01L29/7371
摘要： A method of manufacturing a bipolar transistor is compatible with FinFET processing. A collector region (18) is formed and patterned, base contact regions (26) formed on either side, and a gap formed between the base contact region. A base (28), spacers (30) and an emitter (32) are formed in the gap.
摘要翻译：制造双极晶体管的方法与FinFET处理兼容。形成集电极区域（18）并构图，形成在两侧的基极接触区域（26）和形成在基极接触区域之间的间隙。在间隙中形成基座（28），间隔件（30）和发射极（32）。

2. 发明申请

US20110034001A1 METHOD OF MAKING BIPOLAR TRANSISTOR 有权
标题翻译：制作双极晶体管的方法
公开(公告)号：US20110034001A1
公开(公告)日：2011-02-10
申请号：US12935924
申请日：2009-03-30
申请人： Sebastien Nuttinck , Erwin Hijzen , Johannes J. T. M. Donkers , Guillaume L. R. Boccardi
发明人： Sebastien Nuttinck , Erwin Hijzen , Johannes J. T. M. Donkers , Guillaume L. R. Boccardi
IPC分类号： H01L21/8222
CPC分类号： H01L29/66242 , H01L21/8249 , H01L29/0634 , H01L29/0692 , H01L29/66287 , H01L29/66795 , H01L29/732 , H01L29/7371
摘要： A method of manufacturing a bipolar transistor is compatible with FinFET processing. A collector region (18) is formed and patterned, base contact regions (26) formed on either side, and a gap formed between the base contact region. A base (28), spacers (30) and an emitter (32) are formed in the gap.
摘要翻译：制造双极晶体管的方法与FinFET处理兼容。形成集电极区域（18）并构图，形成在两侧的基极接触区域（26）和形成在基极接触区域之间的间隙。在间隙中形成基座（28），间隔件（30）和发射极（32）。

3. 发明授权

US08431966B2 Method of manufacturing a bipolar transistor semiconductor device and semiconductor devices obtained thereby 有权
标题翻译：制造双极晶体管半导体器件的方法和由此获得的半导体器件
公开(公告)号：US08431966B2
公开(公告)日：2013-04-30
申请号：US12994113
申请日：2009-05-11
申请人： Philippe Meunier-Beillard , Erwin Hijzen , Johannes J. T. M. Donkers
发明人： Philippe Meunier-Beillard , Erwin Hijzen , Johannes J. T. M. Donkers
IPC分类号： H01L21/33 , H01L29/732
CPC分类号： H01L29/7378 , H01L29/66242
摘要： Methods for manufacturing a bipolar transistor semiconductor device are described, along with devices fabricated in accordance with the methods. The methods include the steps of forming a stack of layers over a semiconductor body comprising a window definition layer (18,38), a layer (20) of semiconductor material, a first insulating layer (22), and a second insulating layer (24) which is selectively etchable with respect to the first insulating layer. A trench (26) is then etched into the stack down to the window definition layer. The portion of the trench extending through the second insulating layer is widened to form a wider trench portion (28) therethrough. A window (36) is defined in the window definition layer which is aligned with the wider trench portion, and serves to define the base-collector or base-emitter junction in the finished device.
摘要翻译：描述了制造双极晶体管半导体器件的方法以及根据该方法制造的器件。所述方法包括以下步骤：在半导体主体上形成层叠层，其包括窗口界定层（18,38），半导体材料层（20），第一绝缘层（22）和第二绝缘层（24）），其相对于第一绝缘层可选择性地蚀刻。然后将沟槽（26）蚀刻到堆叠中，直到窗口定义层。延伸穿过第二绝缘层的沟槽的部分被加宽以形成穿过其中的较宽的沟槽部分（28）。在窗口定义层中限定窗口（36），其与较宽的沟槽部分对准，并且用于限定最终器件中的基极 - 集电极或基极 - 发射极结。

4. 发明授权

US08476675B2 Semiconductor device and method of manufacture thereof 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08476675B2
公开(公告)日：2013-07-02
申请号：US12918524
申请日：2009-02-26
申请人： Philippe Meunier-Beillard , Johannes J. T. M. Donkers , Erwin Hijzen
发明人： Philippe Meunier-Beillard , Johannes J. T. M. Donkers , Erwin Hijzen
IPC分类号： H01L29/66
CPC分类号： H01L21/8249 , H01L27/0623 , H01L29/0649 , H01L29/0821 , H01L29/1004 , H01L29/165 , H01L29/42304 , H01L29/456 , H01L29/66242 , H01L29/7378
摘要： A semiconductor device (10) comprising a bipolar transistor and a field 5 effect transistor within a semiconductor body (1) comprising a projecting mesa (5) within which are at least a portion of a collector region (22c and 22d) and a base region (33c) of the bipolar transistor. The bipolar transistor is provided with an insulating cavity (92b) provided in the collector region (22c and 22d). The insulating cavity (92b) may be provided by providing a layer (33a) in the collector region (22c), creating an access path, for example by selectively etching polysilicon towards monocrystalline, and removing a portion of the layer (33a) to provide the cavity using the access path. The layer (33a) provided in the collector region may be of SiGe:C. By blocking diffusion from the base region the insulating cavity (92b) provides a reduction in the base collector capacitance and can be described as defining the base contact.
摘要翻译：一种半导体器件（10），包括在半导体本体（1）内的双极晶体管和场效应晶体管，包括突出的台面（5），其中集电极区域（22c和22d）的至少一部分和基极区域（33c）。双极晶体管设置有设置在集电区域（22c和22d）中的绝缘腔（92b）。可以通过在集电极区域（22c）中设置层（33a）来提供绝缘腔（92b），从而产生存取路径，例如通过选择性地将多晶硅蚀刻成单晶，并去除层（33a）的一部分以提供使用进入路径的空腔。设置在集电区域中的层（33a）可以是SiGe：C。通过阻挡从基极区域的扩散，绝缘腔（92b）提供基极集电极电容的减小，并且可以被描述为限定基极接触。

5. 发明授权

US07605027B2 Method of fabricating a bipolar transistor 失效
标题翻译：制造双极晶体管的方法
公开(公告)号：US07605027B2
公开(公告)日：2009-10-20
申请号：US11913049
申请日：2006-04-24
申请人： Philippe Meunier-Beillard , Erwin Hijzen , Johannes J. T. M. Donkers , Francois Neuilly
发明人： Philippe Meunier-Beillard , Erwin Hijzen , Johannes J. T. M. Donkers , Francois Neuilly
IPC分类号： H01L21/00 , H01L21/84
CPC分类号： H01L29/66272 , H01L29/0821
摘要： A method of fabricating a bipolar transistor in a first trench (11) is disclosed wherein only one photolithographic mask is applied which forms a first trench (11) and a second trench (12). A collector region (21) is formed self-aligned in the first trench (11) and the second trench (12). A base region (31) is formed self-aligned on a portion of the collector region (21), which is in the first trench (11). An emitter region (41) is formed self-aligned on a portion of the base region (31). A contact to the collector region (21) is formed in the second trench (12) and a contact to the base region (31) is formed in the first trench (11). The fabrication of the bipolar transistor may be integrated in a standard CMOS process.
摘要翻译：公开了在第一沟槽（11）中制造双极晶体管的方法，其中仅施加一个形成第一沟槽（11）和第二沟槽（12）的光刻掩模。集电极区域（21）在第一沟槽（11）和第二沟槽（12）中自对准地形成。基部区域（31）在位于第一沟槽（11）中的集电极区域（21）的一部分上自对准地形成。发射极区域（41）在基极区域（31）的一部分上自对准地形成。在所述第二沟槽（12）中形成与所述集电极区域（21）的接触，并且在所述第一沟槽（11）中形成与所述基部区域（31）的接触。双极晶体管的制造可以集成在标准CMOS工艺中。

6. 发明申请

US20090159938A1 METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE OBTAINED WITH SUCH A METHOD 有权
标题翻译：制造半导体器件的方法和采用这种方法获得的半导体器件
公开(公告)号：US20090159938A1
公开(公告)日：2009-06-25
申请号：US12160210
申请日：2007-01-04
申请人： Sebastien Nuttinck , Gilberto Curatola , Erwin Hijzen , Philippe Meunier-Beillard
发明人： Sebastien Nuttinck , Gilberto Curatola , Erwin Hijzen , Philippe Meunier-Beillard
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/0653 , H01L21/02381 , H01L21/02532 , H01L21/0262 , H01L29/66545 , H01L29/66628 , H01L29/66636 , H01L29/7834
摘要： The invention relates to a method of manufacturing a semiconductor device (10) comprising a field effect transistor, in which method a semiconductor body of silicon (12) with a substrate (11) is provided at a surface thereof with a source region (1) and a drain region (2) of a first conductivity type which are situated above a buried isolation region (3,4) and with a channel region (5), between the source and drain regions (1,2), of a second conductivity type, opposite to the first conductivity type, and with a gate region (6) separated from the surface of the semiconductor body (12) by a gate dielectric (7) and situated above the channel region (5), and wherein a mesa (M) is formed in the semiconductor body (12) in which the channel region (5) is formed and wherein the source and drain regions (1,2) are formed on both sides of the mesa (M) in a semiconductor region (8) that is formed using epitaxial growth, the source and drain regions (1,2) thereby contacting the channel region (5). According to the invention the semiconductor region (8) is formed contacting the mesa (M) over substantially the whole thickness of the semiconductor region (8) and is formed below the level of the gate dielectric (7). This method is more versatile and the device (10) obtained thus has an improved high-frequency behavior.
摘要翻译：本发明涉及一种制造半导体器件（10）的方法，该半导体器件（10）包括场效应晶体管，其中在其表面上设置有源极区（1）的具有衬底（11）的硅（12）的半导体本体，和位于源极和漏极区域（1,2）之间的第一导电类型的漏极区域（2），其位于掩埋隔离区域（3,4）和沟道区域（5）之上，具有第二导电性类型，与第一导电类型相反，并且具有通过栅极电介质（7）与半导体本体（12）的表面分离并位于沟道区（5）上方的栅极区（6），并且其中台面 M）形成在其中形成沟道区（5）的半导体本体（12）中，并且在半导体区域（8）中在栅极（M）的两侧形成源区和漏区（1,2）），源极和漏极区域（1,2）由此与沟道区域（5）接触。根据本发明，半导体区域（8）形成在半导体区域（8）的基本上整个厚度上与台面（M）接触并形成在栅极电介质（7）的下方。该方法更通用，因此所获得的装置（10）具有改进的高频行为。

7. 发明授权

US07867864B2 Method of manufacturing a semiconductor device and semiconductor device obtained with such a method 有权
标题翻译：利用这种方法制造半导体器件和半导体器件的制造方法
公开(公告)号：US07867864B2
公开(公告)日：2011-01-11
申请号：US12160210
申请日：2007-01-04
申请人： Sebastien Nuttinck , Giberto Curatola , Erwin Hijzen , Philippe Meunier-Beillard
发明人： Sebastien Nuttinck , Giberto Curatola , Erwin Hijzen , Philippe Meunier-Beillard
IPC分类号： H01L21/336
CPC分类号： H01L29/0653 , H01L21/02381 , H01L21/02532 , H01L21/0262 , H01L29/66545 , H01L29/66628 , H01L29/66636 , H01L29/7834
摘要： The invention relates to a method of manufacturing a semiconductor device comprising a field effect transistor, in which method a semiconductor body of silicon with a substrate is provided at a surface thereof with a source region and a drain region of a first conductivity type which are situated above a buried isolation region and with a channel region, between the source and drain regions, of a second conductivity type, opposite to the first conductivity type, and with a gate region separated from the surface of the semiconductor body by a gate dielectric and situated above the channel region, wherein a mesa is formed in the semiconductor body in which the channel region is formed and wherein the source and drain regions are formed on both sides of the mesa in a semiconductor region that is formed using epitaxial growth, the source and drain regions thereby contacting the channel region.
摘要翻译：本发明涉及一种制造半导体器件的方法，该半导体器件包括场效应晶体管，其中在其表面上提供具有衬底的硅半导体本体，其具有位于第一导电类型的源区和漏区位于源极和漏极区之间的与第一导电类型相反的第二导电类型的沟道区，以及通过栅极电介质与半导体本体的表面分离的栅极区，位于在沟道区域的上方，其中在形成沟道区的半导体本体中形成台面，并且其中源极和漏极区域形成在使用外延生长形成的半导体区域中的台面的两侧，源极和漏极区域漏区，从而接触沟道区。

8. 发明申请

US20100289022A1 METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE OBTAINED WITH SUCH A METHOD 有权
标题翻译：制造半导体器件的方法和采用这种方法获得的半导体器件
公开(公告)号：US20100289022A1
公开(公告)日：2010-11-18
申请号：US12094303
申请日：2006-10-29
申请人： Joost Melai , Erwin Hijzen , Philippe Meunier-Beillard , Johannes J.T.M. Donkers
发明人： Joost Melai , Erwin Hijzen , Philippe Meunier-Beillard , Johannes J.T.M. Donkers
IPC分类号： H01L29/73 , H01L21/331 , H01L29/02
CPC分类号： H01L29/66242 , H01L29/66287
摘要： The invention relates to a method of manufacturing a semiconductor device (10) with a substrate (11) and a semiconductor body (12) which is provided with at least one bipolar transistor having an emitter region (1), a base region (2) and a collector region (3), wherein in the semiconductor body (12) a first semiconductor region (13) is formed that forms one (3) of the collector and emitter regions (1,3) and on the surface of the semiconductor body (12) a stack of layers is formed comprising a first insulating layer (4), a polycrystalline semiconductor layer (5) and a second insulating layer (6) in which stack an opening (7) is formed, after which by non-selective epitaxial growth a further semiconductor layer (22) is deposited of which a monocrystalline horizontal part on the bottom of the opening (7) forms the base region (2) and of which a polycrystalline vertical part (2A) on a side face of the opening (7) is connected to the polycrystalline semiconductor layer (5), after which spacers (S) are formed parallel to the side face of the opening (7) and a second semiconductor region (31) is formed between said spacers (S) forming the other one (1) of the emitter and collector regions (1,3). According to the invention the above method is characterized in that before the further semiconductor layer (22) is deposited, the second insulating layer (6) is provided with an end portion (6A) that viewed in projection overhangs an end portion (5A) of the underlying semiconductor layer (5). In this way bipolar transistor devices can be obtained with good high frequency properties in a cost effective manner.
摘要翻译：本发明涉及一种制造半导体器件（10）的方法，所述半导体器件（10）具有衬底（11）和半导体本体（12），所述半导体器件（12）具有至少一个具有发射极区域（1），基极区域（2）和集电极区域（3），其中在所述半导体本体（12）中形成第一半导体区域（13），所述第一半导体区域形成所述集电极和发射极区域（1,3）中的一个（3）并且在所述半导体主体（12）形成一叠层，其包括形成有开口（7）的第一绝缘层（4），多晶半导体层（5）和第二绝缘层（6），之后通过非选择性外延生长沉积另外的半导体层（22），其中开口（7）的底部上的单晶水平部分形成基部区域（2），并且在该开口的侧面上具有多晶垂直部分（2A）（7）连接到多晶半导体层（5），之后是间隔（S）形成为平行于开口（7）的侧面，并且在形成发射极和集电极区域（1,3）的另一个（1）的所述间隔物（S）之间形成第二半导体区域（31））。根据本发明，上述方法的特征在于，在沉积另外的半导体层（22）之前，第二绝缘层（6）设置有端部（6A），其从突出部分观察到突出部分底层半导体层（5）。以这种方式，可以以成本有效的方式获得具有良好高频特性的双极晶体管器件。

9. 发明申请

US20100068863A1 Method of Manufacturing a Bipolar Transistor and Bipolar Transistor Obtained Therewith 有权
标题翻译：制造双极晶体管和双极晶体管的方法
公开(公告)号：US20100068863A1
公开(公告)日：2010-03-18
申请号：US12306653
申请日：2007-06-12
申请人： Erwin Hijzen
发明人： Erwin Hijzen
IPC分类号： H01L21/331
CPC分类号： H01L29/66287 , H01L29/66242
摘要： The invention relates to a method of manufacturing a semiconductor device (10) comprising a substrate (12) and a silicon semiconductor body (11) and comprising a bipolar transistor with an emitter region (1) of a first conductivity type, a base region (2) of a second conductivity type opposite to the first conductivity type, and a collector region (3) of the first conductivity type, on the surface of the semiconductor body (11) in which the collector region (3) is formed at least an epitaxial semiconductor layer (20,21,22) being deposited in which the base region (2) is formed, on top of this an etch stop layer (15) being deposited on which a silicon low-crystalline semiconductor layer (24) is deposited in which a connection zone of the base region (2) is formed and in which at the location of an emitter region (1) to be formed an opening (7) is provided running up to the etch stop layer (15), a portion of the etch stop layer (15) covering the opening (7) being removed by means of etching and also an adjoining portion of the etch stop layer (15), a hollow being created underneath the silicon low-crystalline semiconductor layer (24) adjoining and connected the opening (7), whereinafter a high-crystalline semiconductor layer (5) is formed within the hollow. In a method according to the invention the formation of the high-crystalline semiconductor layer (5) is carried out in such a way that a part of the surface of the semiconductor body (11) adjoining the opening (7) is kept free from the high-crystalline semiconductor layer (5). In this way a high-quality device (10) is obtained in easy manner. The relevant surface is kept free using a cover layer (6) or in a preferred manner even without the use of such a layer.
摘要翻译：本发明涉及一种制造半导体器件（10）的方法，该半导体器件（10）包括衬底（12）和硅半导体本体（11），并且包括具有第一导电类型的发射极区域（1），基极区域 2）与第一导电类型相反的第二导电类型和第一导电类型的集电极区域（3），其中集电区域（3）至少形成在半导体本体（11）的表面上，外延半导体层（20,21,22）被沉积在其中形成有基极区域（2）的上方，沉积有沉积有硅低温半导体层（24）的蚀刻停止层（15）在其中形成基部区域（2）的连接区域，并且其中在要形成开口（7）的发射极区域（1）的位置处设置有延伸到蚀刻停止层（15）的部分通过蚀刻去除覆盖开口（7）的蚀刻停止层（15）以及蚀刻停止层（15）的相邻部分，在邻接和连接开口（7）的硅低温半导体层（24）下方形成中空，其后，高结晶半导体层（5）为形成在空心中。在根据本发明的方法中，高结晶半导体层（5）的形成是这样一种方式进行的：半导体本体（11）的与开口（7）相邻的表面的一部分保持与高结晶半导体层（5）。以这种方式，以容易的方式获得了高质量的装置（10）。使用覆盖层（6）或以优选的方式即使不使用这种层也可以使相关表面保持自由。

10. 发明申请

US20070228496A1 Vertical Semiconductor Devices and Methods of Manufacturing Such Devices 审中-公开
标题翻译：垂直半导体器件及其制造方法
公开(公告)号：US20070228496A1
公开(公告)日：2007-10-04
申请号：US11574334
申请日：2005-09-01
申请人： Christelle Rochefort , Erwin Hijzen , Phillippe Meunier-Beillard
发明人： Christelle Rochefort , Erwin Hijzen , Phillippe Meunier-Beillard
IPC分类号： H01L29/78
CPC分类号： H01L29/7802 , H01L29/0634 , H01L29/0649 , H01L29/0653 , H01L29/66712 , H01L29/7813
摘要： A vertical semiconductor device, for example a trench-gate MOSFET power transistor (1), has a drift region (12) of one conductivity type containing spaced vertical columns (30) of the opposite conductivity type for charge compensation increase of the device breakdown voltage. Insulating material (31) is provided on the sidewalls only of trenches (20) in the drift region (12) and the opposite conductivity type material is epitaxially grown from the bottom of the trenches (20). The presence of the sidewall insulating material (31) reduces the possibility of defects during the epitaxial growth and hence excessive leakage currents in the device (1). The insulating material (31) also prevents epitaxial growth on the trench sidewalls and hence substantially prevents forming voids in the trenches which would lessen the accuracy of charge compensation. The epitaxial growth by this method can be well controlled and may be stopped at an upper level (21) below the top major surface (10a). Thus, for example, trench-gates 22, 23 may be formed in the same trenches (20) above the compensation columns (30).
摘要翻译：垂直半导体器件，例如沟槽栅MOSFET功率晶体管（1）具有一个导电类型的漂移区域（12），其包含相反导电类型的间隔的垂直列（30），用于器件击穿电压的电荷补偿增加。绝缘材料（31）仅设置在漂移区域（12）中的沟槽（20）的侧壁上，并且相反的导电型材料从沟槽（20）的底部外延生长。侧壁绝缘材料（31）的存在降低了在外延生长期间的缺陷的可能性，并因此降低了器件（1）中的过大的漏电流。绝缘材料（31）还防止沟槽侧壁上的外延生长，从而基本上防止在沟槽中形成空穴，这将降低电荷补偿的精度。通过该方法的外延生长可以很好地控制，并且可以在顶部主表面（10a）下方的上层（21）处停止。因此，例如，可以在补偿柱（30）上方的相同沟槽（20）中形成沟槽栅极22,23。

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