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    • 6. 发明授权
    • Flexible I/O routing resources
    • 灵活的I / O路由资源
    • US06826741B1
    • 2004-11-30
    • US10289629
    • 2002-11-06
    • Brian D. JohnsonAndy L. LeeCameron McClintockTriet NguyenDavid JeffersonPaul LeventisDavid LewisVaughn BetzMichael Chan
    • Brian D. JohnsonAndy L. LeeCameron McClintockTriet NguyenDavid JeffersonPaul LeventisDavid LewisVaughn BetzMichael Chan
    • G06F1750
    • H03K19/17736H03K19/17744
    • In one aspect, flexible routing resources provided are comprising an arrangement of staggered line segments on a periphery of an electronic device. In another aspect, I/O bus lines a re coupled to receive signals from and to provide signals to other bus lines, core routing, and I/O circuitry, thus facilitating the use of the I/O bus for a variety of routes that may include I/O-to-core, core-to-I/O and core-to-core routes. In another aspect, a length of I/O bus lines is optimized for speed over long signal routes with high fanout. In another aspect, the loading effects of high fanout are minimized by using a plurality of tapping buffers to couple lines to both core routing and to I/O circuitry. In another aspect, a spiraling technique is provided that allows a continuous bus having line segments of consistent length whether or not the number of I/O blocks is an integral multiple of the selected logical length for line segments.
    • 在一个方面,提供的灵活路由资源包括在电子设备的外围上的交错线段的布置。 在另一方面,I / O总线线路被耦合以从其接收信号并向其它总线线路,核心路由和I / O电路提供信号,从而便于将I / O总线用于各种路由, 可能包括I / O到核心,核到I / O和核心到核心的路由。 在另一方面,I / O总线的长度针对具有高扇出的长信号路由的速度被优化。 在另一方面,通过使用多个分接缓冲器来将线耦合到核心路由和I / O电路两者,高扇出的负载效应被最小化。 在另一方面,提供一种螺旋式技术,其允许具有一致长度的线段的连续总线,无论I / O块的数量是否为线段的所选逻辑长度的整数倍。
    • 7. 发明授权
    • System and method for optimizing routing lines in a programmable logic device
    • 用于优化可编程逻辑器件中路由线路的系统和方法
    • US06895570B2
    • 2005-05-17
    • US10057232
    • 2002-01-25
    • David M. LewisVaughn BetzPaul LeventisMichael ChanCameron R. McClintockAndy L. LeeChristopher F. LaneSrinivas T. ReddyRichard Cliff
    • David M. LewisVaughn BetzPaul LeventisMichael ChanCameron R. McClintockAndy L. LeeChristopher F. LaneSrinivas T. ReddyRichard Cliff
    • G06F17/50H01L21/82H03K19/177
    • H03K19/17736G06F17/5054G06F17/5077
    • An embodiment of this invention pertains to a wire that interconnects multiple function blocks within a programmable logic device (“PLD”). An electrically optimum physical length is determined for the wire. A wire having the electrically optimum physical length transmits a signal down the wire as fast as possible. Some of the wires used in the PLD have a physical length substantially the same as the electrically optimum physical length or an adjustment of the electrically optimum physical length to account for non-electrical considerations. The physical length, as used herein, is the measured length of the wire. A logical length of the wire, as used herein, is the number of function blocks that the wire spans. Given that the function blocks have a different height and width, the logical length of the wire varies depending on the orientation of the wire.A routing architecture is an array that includes rows and columns of function blocks. The columns of the array are connected with horizontal lines (“H-line”) and the rows of the array are connected with vertical lines (“V-line). The types of H-lines include a H4 line that spans four function blocks, a H8 line that spans eight function blocks, and a H24 line that spans twenty-four function blocks. The types of V-lines include a V4 line that spans four function blocks, a V8 line that spans eight function blocks, and a V16 line that spans sixteen function blocks.
    • 本发明的实施例涉及将可编程逻辑器件(“PLD”)内的多个功能块互连的导线。 确定电线最佳物理长度。 具有最佳物理长度的导线尽可能快地将信号沿导线传送。 在PLD中使用的一些电线具有与电最佳物理长度基本相同的物理长度或电学最佳物理长度的调整以考虑非电学考虑。 如本文所使用的物理长度是测量的线的长度。 如本文所使用的,线的逻辑长度是导线跨越的功能块的数量。 假设功能块具有不同的高度和宽度,则线的逻辑长度根据线的方向而变化。 路由架构是包括功能块的行和列的数组。 数组的列与水平线(“H-line”)连接,阵列与垂直线(“V线”)连接,H线的类型包括四条功能块的H4线 ,一个跨越八个功能块的H8线,以及跨越二十四个功能块的H24线,V线的类型包括跨越四个功能块的V4线,跨越八个功能块的V8线,以及V16线 线跨越十六个功能块。