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1. 发明授权

US10026151B2 Head-up display warping controller 有权
公开(公告)号：US10026151B2
公开(公告)日：2018-07-17
申请号：US15024774
申请日：2013-09-27
申请人： Michael Andreas Staudenmaier , Kshitij Bajaj , Chanpreet Singh
发明人： Michael Andreas Staudenmaier , Kshitij Bajaj , Chanpreet Singh
IPC分类号： G06T3/00 , G02B27/00 , G02B27/01
摘要： A script-driven head-up display controller comprising an image warping unit and an image projection unit wherein the image warping unit is coupled to the image projection unit and is adapted to: receive a line-based warping descriptor comprising first information associated with a distortion caused by a non-flat display; and, in response to the reception of the line-based warping descriptor, the image warping unit is further adapted to, based on the line-based warping descriptor: fetch one or more lines of the source image; and, output to the image projection unit at least one output line of the output image associated with an electronic image warping of one or more pixels of the one or more input lines, and wherein the line-based warping descriptor further comprises second information associated with buffer management instructions calculated off-line.

2. 发明申请

US20150235633A1 MULTI-LAYER DISPLAY SYSTEM 审中-公开
标题翻译：多层显示系统
公开(公告)号：US20150235633A1
公开(公告)日：2015-08-20
申请号：US14185866
申请日：2014-02-20
申请人： Chanpreet Singh , Kshitij Bajaj , Michael A. Staudenmaier
发明人： Chanpreet Singh , Kshitij Bajaj , Michael A. Staudenmaier
IPC分类号： G09G5/39 , G06T9/00
CPC分类号： G09G5/001 , G09G5/14 , G09G5/363 , G09G2340/02 , G09G2340/12 , G09G2352/00 , G09G2360/06 , H04N19/42 , H04N19/44
摘要： A multi-layer display system for displaying images including a compressed image, in multiple planes, in a single frame, includes a compressed image decoder for decoding the compressed image, multiple arbiters for reading the decoded image data, and a decoder arbitration and semaphore control unit for splitting the compressed image into segments, assigning the segments to ones of the multiple planes, and allowing at least one arbiter to access the compressed image decoder to read the decoded data of the segment assigned to a plane mapped with the arbiter when the segment is being decoded.
摘要翻译：用于在单个帧中在多个平面中显示包括压缩图像的图像的多层显示系统包括用于对压缩图像进行解码的压缩图像解码器，用于读取解码图像数据的多个仲裁器，以及解码器仲裁和信号量控制单元，用于将压缩图像分割成段，将段分配给多个平面中的一个，并且允许至少一个仲裁器访问压缩图像解码器以读取分配给与仲裁器映射的平面的段的解码数据，当段正在解码。

3. 发明申请

US20160124889A1 ASYNCHRONOUS FIFO BUFFER WITH JOHNSON CODE WRITE POINTER 有权
标题翻译：具有约翰逊代码写入指针的异步FIFO缓冲区
公开(公告)号：US20160124889A1
公开(公告)日：2016-05-05
申请号：US14531992
申请日：2014-11-03
申请人： Chanpreet Singh , Kshitij Bajaj , Abhineet Kumar Bhojak , Anisha Ladsaria , Tejbal Prasad
发明人： Chanpreet Singh , Kshitij Bajaj , Abhineet Kumar Bhojak , Anisha Ladsaria , Tejbal Prasad
IPC分类号： G06F13/42 , G06F5/06 , G06F13/16
CPC分类号： G06F13/4239 , G06F5/065 , G06F5/14 , G06F13/1673 , G06F2205/067 , G06F2205/102
摘要： An asynchronous data transfer system includes a bus interface unit (BIU), a FIFO write logic module, a write pointer synchronizer, a write pointer validator, a FIFO read logic module, and an asynchronous FIFO buffer. The FIFO buffer receives a variable size data from the BIU and stores the variable size data at a write address. The FIFO write logic module generates a write pointer by encoding the write address using a Johnson code. The FIFO read logic module receives a synchronized write pointer at the asynchronous clock domain and generates a read address signal when the synchronized write pointer is a valid Johnson code format. The FIFO buffer transfers the variable size data to a processor based on the read address signal.
摘要翻译：异步数据传输系统包括总线接口单元（BIU），FIFO写逻辑模块，写指针同步器，写指针验证器，FIFO读逻辑模块和异步FIFO缓冲器。 FIFO缓冲器从BIU接收可变大小的数据，并将可变大小数据存储在写入地址。 FIFO写入逻辑模块通过使用Johnson代码对写入地址进行编码来生成写入指针。 FIFO读取逻辑模块在异步时钟域接收同步的写入指针，并且当同步的写入指针是有效的约翰逊码格式时，产生读取地址信号。 FIFO缓冲器基于读取的地址信号将可变大小的数据传送到处理器。

4. 发明授权

US09710415B2 Asynchronous FIFO buffer with Johnson code write pointer 有权
公开(公告)号：US09710415B2
公开(公告)日：2017-07-18
申请号：US14531992
申请日：2014-11-03
申请人： Chanpreet Singh , Kshitij Bajaj , Abhineet Kumar Bhojak , Anisha Ladsaria , Tejbal Prasad
发明人： Chanpreet Singh , Kshitij Bajaj , Abhineet Kumar Bhojak , Anisha Ladsaria , Tejbal Prasad
IPC分类号： G06F13/26 , G06F13/42 , G06F13/16 , G06F5/06 , G06F5/14
CPC分类号： G06F13/4239 , G06F5/065 , G06F5/14 , G06F13/1673 , G06F2205/067 , G06F2205/102
摘要： An asynchronous data transfer system includes a bus interface unit (BIU), a FIFO write logic module, a write pointer synchronizer, a write pointer validator, a FIFO read logic module, and an asynchronous FIFO buffer. The FIFO buffer receives a variable size data from the BIU and stores the variable size data at a write address. The FIFO write logic module generates a write pointer by encoding the write address using a Johnson code. The FIFO read logic module receives a synchronized write pointer at the asynchronous clock domain and generates a read address signal when the synchronized write pointer is a valid Johnson code format. The FIFO buffer transfers the variable size data to a processor based on the read address signal.

5. 发明授权

US09484004B2 Display controller for display panel 有权
标题翻译：显示面板显示控制器
公开(公告)号：US09484004B2
公开(公告)日：2016-11-01
申请号：US14624529
申请日：2015-02-17
申请人： Chanpreet Singh , Kshitij Bajaj , Nakul Grover , Michael A. Staudenmaier
发明人： Chanpreet Singh , Kshitij Bajaj , Nakul Grover , Michael A. Staudenmaier
IPC分类号： G09G5/36 , G06T1/20 , G09G5/393 , G09G3/32 , G09G5/02 , G09G5/06
CPC分类号： G09G5/363 , G09G3/3208 , G09G5/026 , G09G5/06 , G09G5/393 , G09G2320/0693 , G09G2340/0457
摘要： A display controller includes first and second arbitrating units, a pixel data calculating unit, a latency measurement unit, and a clock divider. The first and second arbitrating units fetch first and second pixel data corresponding to at least one pixel from an external memory via a system bus. The pixel data calculating unit determines a size of the first and second pixel data. The latency measuring unit generates a first data rate value that is indicative of a latency of the system bus based on the size of the first and second pixel data. The clock divider receives a first clock signal modulation value corresponding to the first data rate value and alters a modulation of a reference clock signal. The graphics blending unit receives the first and second pixel data and provides blended pixel data to a display panel based on a modulated clock signal.
摘要翻译：显示控制器包括第一和第二仲裁单元，像素数据计算单元，等待时间测量单元和时钟分频器。第一和第二仲裁单元经由系统总线从外部存储器提取对应于至少一个像素的第一和第二像素数据。像素数据计算单元确定第一和第二像素数据的大小。延迟测量单元基于第一和第二像素数据的大小生成指示系统总线的等待时间的第一数据速率值。时钟分频器接收对应于第一数据速率值的第一时钟信号调制值，并改变参考时钟信号的调制。图形混合单元接收第一和第二像素数据，并且基于经调制的时钟信号将混合像素数据提供给显示面板。

6. 发明申请

US20160240172A1 DISPLAY CONTROLLER FOR DISPLAY PANEL 有权
标题翻译：显示面板显示控制器
公开(公告)号：US20160240172A1
公开(公告)日：2016-08-18
申请号：US14624529
申请日：2015-02-17
申请人： CHANPREET SINGH , Kshitij Bajaj , Nakul Grover , Michael A. Staudenmaier
发明人： CHANPREET SINGH , Kshitij Bajaj , Nakul Grover , Michael A. Staudenmaier
IPC分类号： G09G5/36 , G06T1/20 , G09G5/393
CPC分类号： G09G5/363 , G09G3/3208 , G09G5/026 , G09G5/06 , G09G5/393 , G09G2320/0693 , G09G2340/0457
摘要： A display controller includes first and second arbitrating units, a pixel data calculating unit, a latency measurement unit, and a clock divider. The first and second arbitrating units fetch first and second pixel data corresponding to at least one pixel from an external memory via a system bus. The pixel data calculating unit determines a size of the first and second pixel data. The latency measuring unit generates a first data rate value that is indicative of a latency of the system bus based on the size of the first and second pixel data. The clock divider receives a first clock signal modulation value corresponding to the first data rate value and alters a modulation of a reference clock signal. The graphics blending unit receives the first and second pixel data and provides blended pixel data to a display panel based on a modulated clock signal.
摘要翻译：显示控制器包括第一和第二仲裁单元，像素数据计算单元，等待时间测量单元和时钟分频器。第一和第二仲裁单元经由系统总线从外部存储器提取对应于至少一个像素的第一和第二像素数据。像素数据计算单元确定第一和第二像素数据的大小。延迟测量单元基于第一和第二像素数据的大小生成指示系统总线的等待时间的第一数据速率值。时钟分频器接收对应于第一数据速率值的第一时钟信号调制值，并改变参考时钟信号的调制。图形混合单元接收第一和第二像素数据，并且基于经调制的时钟信号将混合像素数据提供给显示面板。

7. 发明授权

US09900548B2 Display control unit and method for generating a video signal 有权
公开(公告)号：US09900548B2
公开(公告)日：2018-02-20
申请号：US14421894
申请日：2012-08-24
申请人： Michael Staudenmaier , Kshitij Bajaj , Mehul Kumar , Sarthak Mittal
发明人： Michael Staudenmaier , Kshitij Bajaj , Mehul Kumar , Sarthak Mittal
IPC分类号： G06F13/00 , H04N5/91 , G09G5/393 , G06T1/60 , H04N5/04 , H04N5/265 , G09G5/00
CPC分类号： H04N5/91 , G06T1/60 , G09G5/001 , G09G5/393 , G09G2320/103 , G09G2360/10 , G09G2380/10 , H04N5/04 , H04N5/265
摘要： A display control unit is connected to a display and arranged to generate a video signal representing a sequence of video frames to be displayed consecutively on said display. The display control unit may include a first memory unit arranged to buffer a set of image descriptors; a second memory unit connected between said first memory unit and said display; an update unit connected to said first memory unit and arranged to update said image descriptors in said first memory unit and to generate a proceed signal only when said set of image descriptors in said first memory unit is up to date; a copy unit arranged to copy said image descriptors from said first memory unit to said second memory unit in response to said proceed signal; and a video unit arranged to generate said video signal on the basis of said image descriptors in said second memory unit.

8. 发明申请

US20150161759A1 DIAGNOSTIC DATA GENERATION APPARATUS, INTEGRATED CIRCUIT AND METHOD OF GENERATING DIAGNOSTIC DATA 审中-公开
标题翻译：诊断数据生成装置，集成电路及产生诊断数据的方法
公开(公告)号：US20150161759A1
公开(公告)日：2015-06-11
申请号：US14390193
申请日：2012-04-05
申请人： Michael Staudenmaier , Kshitij Bajaj , Mehul Kumar , Steven Mcaslan , Sarthak Mittal
发明人： Michael Staudenmaier , Kshitij Bajaj , Mehul Kumar , Steven Mcaslan , Sarthak Mittal
IPC分类号： G06T1/60 , G09G5/36
CPC分类号： G06T1/60 , G09G3/20 , G09G3/2092 , G09G5/005 , G09G5/36 , G09G5/363 , G09G5/393 , G09G2330/12 , G09G2360/12
摘要： A diagnostic data generation apparatus for a display controller comprises an underrun detector arranged to monitor, when in use, buffer depletion in order to detect an underrun condition. The underrun condition results from a data feed lag associated with a mismatch between a buffer fill rate and a predetermined output data rate. The underrun detector is arranged to generate diagnostic data in response to detection of the underrun condition, the diagnostic data identifying the underrun condition and a location in an array of pixels associated with the underrun condition
摘要翻译：一种用于显示控制器的诊断数据产生装置，包括一个欠载检测器，其布置成在使用时监视缓冲器耗尽以便检测欠载状况。欠载条件是由与缓冲器填充率和预定输出数据速率之间的不匹配相关联的数据馈送滞后产生的。欠运动检测器被布置成响应于欠载状况的检测而产生诊断数据，识别欠载条件的诊断数据和与欠载条件相关联的像素阵列中的位置

9. 发明申请

US20130120437A1 DISPLAY CONTROLLING UNIT, IMAGE DISPLAYING SYSTEM AND METHOD FOR OUTPUTTING IMAGE DATA 审中-公开
标题翻译：显示控制单元，图像显示系统和用于输出图像数据的方法
公开(公告)号：US20130120437A1
公开(公告)日：2013-05-16
申请号：US13810746
申请日：2010-07-20
申请人： Kshitij Bajaj , Michael Staudenmaier
发明人： Kshitij Bajaj , Michael Staudenmaier
IPC分类号： G06T5/00
CPC分类号： G06T5/00 , G06F3/14 , G09G3/2044 , G09G5/363 , G09G2330/12 , G09G2340/10 , G09G2340/12 , G09G2340/125 , G09G2358/00 , G09G2380/10
摘要： A display controlling unit comprises an input connectable to receive input image data representing an input image comprising a first set and a second set of image elements. The second set of image elements comprises a safety relevant information. The display controlling unit also comprises an output connectable to provide output image data representing an output image at least comprising the safety relevant information, an image enhancement module arranged to perform an image enhancement processing for the first set of image elements when a safety mode signal indicates a first mode, and a verification module arranged to perform a verification processing for the second set of image elements when the safety mode signal indicates a second mode.
摘要翻译：显示控制单元包括可连接以接收表示包括第一组和第二组图像元素的输入图像的输入图像数据的输入。第二组图像元素包括安全相关信息。显示控制单元还包括可输出的输出，以提供表示至少包括安全相关信息的输出图像的输出图像数据;图像增强模块，被安排为当安全模式信号指示时，对第一组图像元素执行图像增强处理第一模式和验证模块，其被布置为当所述安全模式信号指示第二模式时对所述第二组图像元素执行验证处理。

10. 发明申请

US20140223239A1 MEMORY ERROR MANAGEMENT SYSTEM 有权
标题翻译：内存错误管理系统
公开(公告)号：US20140223239A1
公开(公告)日：2014-08-07
申请号：US13759054
申请日：2013-02-05
申请人： Sarthak Mittal , Kshitij Bajaj , Prashant Bhargava
发明人： Sarthak Mittal , Kshitij Bajaj , Prashant Bhargava
IPC分类号： G06F11/07
CPC分类号： G06F11/073 , G06F11/0781 , G06F11/0787 , G11C7/1006 , G11C16/349 , G11C2029/0409
摘要： A memory error management system connected to memory channels for managing errors detected in corresponding memory devices includes a reporting table including a list of historically reported errors, a binary value representing the current error status of the memory channels, a uniqueness check module for checking whether a historically reported error is reappearing as a current error, an error mask register for generating a masked binary value representing unique current errors in the memory channels, and a channel arbitration module for decoding the channel identifiers of corrupted memory channels from the masked binary value and storing the decoded channel identifiers into the reporting table.
摘要翻译：连接到存储器通道的存储器错误管理系统用于管理在对应存储器件中检测到的错误，包括报告表，其包括历史报告的错误列表，表示存储器通道的当前错误状态的二进制值，用于检查是否存在的唯一性检查模块历史报告的错误正在作为当前误差重现，用于产生表示存储器通道中的唯一电流错误的掩蔽二进制值的误差掩码寄存器，以及用于从掩蔽的二进制值中解码损坏的存储器通道的通道标识符的通道仲裁模块，将解码的信道标识符转换为报告表。

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