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1. 发明申请

US20140223239A1 MEMORY ERROR MANAGEMENT SYSTEM 有权
标题翻译：内存错误管理系统
公开(公告)号：US20140223239A1
公开(公告)日：2014-08-07
申请号：US13759054
申请日：2013-02-05
申请人： Sarthak Mittal , Kshitij Bajaj , Prashant Bhargava
发明人： Sarthak Mittal , Kshitij Bajaj , Prashant Bhargava
IPC分类号： G06F11/07
CPC分类号： G06F11/073 , G06F11/0781 , G06F11/0787 , G11C7/1006 , G11C16/349 , G11C2029/0409
摘要： A memory error management system connected to memory channels for managing errors detected in corresponding memory devices includes a reporting table including a list of historically reported errors, a binary value representing the current error status of the memory channels, a uniqueness check module for checking whether a historically reported error is reappearing as a current error, an error mask register for generating a masked binary value representing unique current errors in the memory channels, and a channel arbitration module for decoding the channel identifiers of corrupted memory channels from the masked binary value and storing the decoded channel identifiers into the reporting table.
摘要翻译：连接到存储器通道的存储器错误管理系统用于管理在对应存储器件中检测到的错误，包括报告表，其包括历史报告的错误列表，表示存储器通道的当前错误状态的二进制值，用于检查是否存在的唯一性检查模块历史报告的错误正在作为当前误差重现，用于产生表示存储器通道中的唯一电流错误的掩蔽二进制值的误差掩码寄存器，以及用于从掩蔽的二进制值中解码损坏的存储器通道的通道标识符的通道仲裁模块，将解码的信道标识符转换为报告表。

2. 发明授权

US08843791B2 Memory error management system 有权
标题翻译：内存错误管理系统
公开(公告)号：US08843791B2
公开(公告)日：2014-09-23
申请号：US13759054
申请日：2013-02-05
申请人： Sarthak Mittal , Kshitij Bajaj , Prashant Bhargava
发明人： Sarthak Mittal , Kshitij Bajaj , Prashant Bhargava
IPC分类号： G06F11/00 , G06F11/07
CPC分类号： G06F11/073 , G06F11/0781 , G06F11/0787 , G11C7/1006 , G11C16/349 , G11C2029/0409
摘要： A memory error management system connected to memory channels for managing errors detected in corresponding memory devices includes a reporting table including a list of historically reported errors, a binary value representing the current error status of the memory channels, a uniqueness check module for checking whether a historically reported error is reappearing as a current error, an error mask register for generating a masked binary value representing unique current errors in the memory channels, and a channel arbitration module for decoding the channel identifiers of corrupted memory channels from the masked binary value and storing the decoded channel identifiers into the reporting table.
摘要翻译：连接到存储器通道的存储器错误管理系统用于管理在对应存储器件中检测到的错误，包括报告表，其包括历史报告的错误列表，表示存储器通道的当前错误状态的二进制值，用于检查是否存在的唯一性检查模块历史报告的错误正在作为当前误差重现，用于产生表示存储器通道中的唯一电流错误的掩蔽二进制值的误差掩码寄存器，以及用于从掩蔽的二进制值中解码损坏的存储器通道的通道标识符的通道仲裁模块，将解码的信道标识符转换为报告表。

3. 发明授权

US09031736B2 Channel diagnostic system for sent receiver 有权
标题翻译：发送接收机的通道诊断系统
公开(公告)号：US09031736B2
公开(公告)日：2015-05-12
申请号：US14150738
申请日：2014-01-08
申请人： Rohit Tomar , Prashant Bhargava , Neha Jain , Matthew B. Ruff
发明人： Rohit Tomar , Prashant Bhargava , Neha Jain , Matthew B. Ruff
IPC分类号： G06F7/00 , G07C5/00 , G01P15/125 , H02M1/36 , H04L7/04
CPC分类号： G07C5/00 , G01P15/125 , H02M1/36 , H04L7/044
摘要： A system for performing diagnostic checks on a data message transmitted from a sensor and received by a receiver includes a receiver clock tick counter, a prescaler counter, a calibration pulse detector, a nibble counter, and a calculator. The system receives first and second data messages transmitted from the sensor. Pulse widths of first and second calibration pulses of the first and second data messages, respectively, and lengths of the first and second data messages are measured using the receiver clock tick, prescaler, and nibble counters based on a compensated receiver clock signal. Thereafter, the pulse widths of the first and second calibration pulses and the lengths of the first and second data messages are compared using the calculator to perform the diagnostic checks.
摘要翻译：用于对从传感器发送并由接收器接收的数据消息进行诊断检查的系统包括接收机时钟计数器，预分频器计数器，校准脉冲检测器，半字节计数器和计算器。系统接收从传感器发送的第一和第二数据消息。第一和第二数据消息的第一和第二校准脉冲的分别为第一和第二数据消息的长度的脉冲宽度使用接收器时钟tick，预分频器和半字节计数器基于经补偿的接收机时钟信号来测量。此后，使用计算器比较第一和第二校准脉冲的脉冲宽度以及第一和第二数据消息的长度以执行诊断检查。

4. 发明授权

US08689357B2 Tamper detector for secure module 有权
标题翻译：防拆检测器用于安全模块
公开(公告)号：US08689357B2
公开(公告)日：2014-04-01
申请号：US13475947
申请日：2012-05-19
申请人： Mohit Arora , Rakesh Pandey , Pushkar Sareen , Prashant Bhargava
发明人： Mohit Arora , Rakesh Pandey , Pushkar Sareen , Prashant Bhargava
IPC分类号： G06F21/00
CPC分类号： G06F21/72 , G06F21/755
摘要： A tamper detector has input and output pins for connection to ends of a tamper detection circuit, and a corresponding set of linear feedback shift registers (LFSRs) timed by clock signals for generating pseudo-random coded detection signals as a function of seed values and of a generator polynomial defined by feedback taps. A comparator compares signals received from the detection circuit with the coded detection signals. A multiplexer provides the coded detection signal selectively from the LFSRs to the output pin and the comparator. A controller varies the seed values for different cycles of values of the pseudo-random coded detection signals. The controller also controls the generator polynomial and a frequency of the clock signals for different cycles of values of the pseudo-random coded detection signals.
摘要翻译：篡改检测器具有用于连接到篡改检测电路的端部的输入和输出引脚和由时钟信号定时的对应的一组线性反馈移位寄存器（LFSR），用于产生作为种子值的函数的伪随机编码检测信号，以及由反馈抽头定义的生成多项式。比较器将从检测电路接收的信号与编码的检测信号进行比较。复用器将选择性地从LFSR向编码的检测信号提供给输出引脚和比较器。控制器改变伪随机编码检测信号的不同周期值的种子值。控制器还控制生成多项式和针对伪随机编码检测信号的不同周期值的时钟信号的频率。

5. 发明申请

US20140353849A1 SYSTEM FOR PREVENTING TAMPERING WITH INTEGRATED CIRCUIT 有权
标题翻译：用于集成电路防止篡改的系统
公开(公告)号：US20140353849A1
公开(公告)日：2014-12-04
申请号：US13905150
申请日：2013-05-30
申请人： Mohit Arora , Prashant Bhargava , Rishi Bhooshan
发明人： Mohit Arora , Prashant Bhargava , Rishi Bhooshan
IPC分类号： H01L23/00
CPC分类号： G06F21/86 , G06F2221/2143 , H01L23/573 , H01L2924/0002 , H01L2924/00
摘要： A system for generating a tamper detection signal indicating tampering with one or more circuits of an integrated circuit (IC) includes a tamper detection module, and wire-pairs connected to the tamper detection module and arranged in a winding configuration to form a wire-mesh. The wire-mesh is placed a predefined distance from the circuits. The tamper detection module generates and provides serial bit-streams to the wire-pairs for detecting a breach in the wire-mesh by an external probe.
摘要翻译：用于产生表示篡改集成电路（IC）的一个或多个电路的篡改检测信号的系统包括篡改检测模块和连接到篡改检测模块并且以绕组配置布置以形成线网的线对。线网放置在与电路预定距离的位置。篡改检测模块生成并提供串行比特流到线对，用于通过外部探针检测金属丝网中的突破。

6. 发明授权

US08447004B2 Estimation and compensation of clock variation in received signal 有权
标题翻译：接收信号时钟变化的估计和补偿
公开(公告)号：US08447004B2
公开(公告)日：2013-05-21
申请号：US13020815
申请日：2011-02-04
申请人： Rohit Tomar , Prashant Bhargava
发明人： Rohit Tomar , Prashant Bhargava
IPC分类号： H04L7/00
CPC分类号： H04L7/0331 , H04L7/044
摘要： A method and system for estimating and compensating for variation between a receiver clock and a transmitter clock, where a receiver utilizes a high frequency clock signal to generate a receiver clock and then adjusts the receiver clock to compensate for variations between the receiver and transmitter clocks. The adjusted receiver clock is used to sample nibble pulses in a received data frame. Counter based compensation of the receiver clock eliminates the need for the receiver to perform floating point calculations, improves the accuracy of nibble pulse sampling and also reduces area and power consumption of the device.
摘要翻译：一种用于估计和补偿接收机时钟和发射机时钟之间的变化的方法和系统，其中接收机利用高频时钟信号来产生接收机时钟，然后调整接收机时钟以补偿接收机和发射机时钟之间的变化。经调整的接收机时钟用于对接收到的数据帧中的半字节进行采样。接收机时钟的基于计数器的补偿消除了接收机执行浮点计算的需要，提高了半字节脉冲采样的精度，并且还减少了器件的面积和功耗。

7. 发明申请

US20150186676A1 REAL-TIME CLOCK (RTC) MODIFICATION DETECTION SYSTEM 审中-公开
标题翻译：实时时钟（RTC）修改检测系统
公开(公告)号：US20150186676A1
公开(公告)日：2015-07-02
申请号：US14145991
申请日：2014-01-01
申请人： Mohit Arora , Prashant Bhargava , Pradip Singh
发明人： Mohit Arora , Prashant Bhargava , Pradip Singh
IPC分类号： G06F21/64
CPC分类号： G06F21/725
摘要： A system for securing a real-time clock (RTC) of an electronic device includes a RTC counter that counts clock pulses of a RTC signal generated by a crystal oscillator, and a reference-time register that periodically stores a reference time value generated by a network-clock generator. A hash-value generator uses a predefined hash algorithm to generate first and second hash values based on the reference time value and the count of the RTC counter, respectively, at predetermined time intervals. A comparator compares the first and second hash values and generates a trigger signal when there is a mismatch.
摘要翻译：用于保护电子设备的实时时钟（RTC）的系统包括对由晶体振荡器产生的RTC信号的时钟脉冲进行计数的RTC计数器和周期性地存储由网络时钟发生器。散列值生成器使用预定义的散列算法，以预定的时间间隔分别基于参考时间值和RTC计数器的计数来产生第一和第二散列值。比较器比较第一和第二散列值，并且当存在不匹配时产生触发信号。

8. 发明授权

US08643410B1 System for compensating for variations in clock signal frequency 有权
标题翻译：用于补偿时钟信号频率变化的系统
公开(公告)号：US08643410B1
公开(公告)日：2014-02-04
申请号：US13602199
申请日：2012-09-02
申请人： Prashant Bhargava , Mohit Arora , James R. Feddeler , Martin Mienkina
发明人： Prashant Bhargava , Mohit Arora , James R. Feddeler , Martin Mienkina
IPC分类号： H03K9/08
CPC分类号： G04F10/04 , H03L7/00
摘要： A system for compensating for variations in the frequency of an input clock signal having a first frequency includes a coarse counter that receives the input clock signal, counts a predetermined number of clock pulses of the input clock signal, and generates a coarse compensated clock signal having a second frequency. A first compensation module adjusts a clock pulse of the input clock signal based on a coarse compensation value. A residual period adjustment module accumulates a fine compensation value for each clock pulse of the coarse compensated clock signal. A fine counter operates at a third frequency of a fine clock signal, receives an adjusted delay value based on the accumulated fine compensation value, counts a number of fine clock pulses in each clock pulse of the coarse compensated clock signal, and generates a fine compensated clock signal having the second frequency.
摘要翻译：用于补偿具有第一频率的输入时钟信号的频率变化的系统包括接收输入时钟信号的粗计数器，对输入时钟信号的预定数量的时钟脉冲进行计数，并产生具有第二个频率。第一补偿模块基于粗略的补偿值调整输入时钟信号的时钟脉冲。残余周期调整模块对粗补偿时钟信号的每个时钟脉冲累积精细补偿值。精细计数器以精细时钟信号的第三频率工作，基于累积的精细补偿值接收经调整的延迟值，对粗略补偿时钟信号的每个时钟脉冲中的精细时钟脉冲数进行计数，并产生精细补偿时钟信号具有第二频率。

9. 发明申请

US20130345924A1 CHANNEL DIAGNOSTIC SYSTEM FOR SENT RECEIVER 有权
标题翻译：用于接收器的通道诊断系统
公开(公告)号：US20130345924A1
公开(公告)日：2013-12-26
申请号：US13530085
申请日：2012-06-21
申请人： Rohit Tomar , Prashant Bhargava , Neha Jain , Matthew B. Ruff
发明人： Rohit Tomar , Prashant Bhargava , Neha Jain , Matthew B. Ruff
IPC分类号： G06F19/00 , H04B17/00
CPC分类号： G07C5/00 , G01P15/125 , H02M1/36 , H04L7/044
摘要： A system for performing diagnostic checks on a data message transmitted from a sensor and received by a receiver includes a receiver clock tick counter, a prescaler counter, a calibration pulse detector, a nibble counter, and a calculator. The system receives first and second data messages transmitted from the sensor. Pulse widths of first and second calibration pulses of the first and second data messages, respectively, and lengths of the first and second data messages are measured using the receiver clock tick, prescaler, and nibble counters based on a compensated receiver clock signal. Thereafter, the pulse widths of the first and second calibration pulses and the lengths of the first and second data messages are compared using the calculator to perform the diagnostic checks.
摘要翻译：用于对从传感器发送并由接收器接收的数据消息进行诊断检查的系统包括接收机时钟计数器，预分频器计数器，校准脉冲检测器，半字节计数器和计算器。系统接收从传感器发送的第一和第二数据消息。第一和第二数据消息的第一和第二校准脉冲的分别为第一和第二数据消息的长度的脉冲宽度使用接收器时钟tick，预分频器和半字节计数器基于经补偿的接收机时钟信号来测量。此后，使用计算器比较第一和第二校准脉冲的脉冲宽度以及第一和第二数据消息的长度以执行诊断检查。

10. 发明授权

US08443224B2 Apparatus and method for decoupling asynchronous clock domains 有权
标题翻译：用于解耦异步时钟域的装置和方法
公开(公告)号：US08443224B2
公开(公告)日：2013-05-14
申请号：US12912780
申请日：2010-10-27
申请人： Prashant Bhargava , Mohit Arora
发明人： Prashant Bhargava , Mohit Arora
IPC分类号： G06F1/12 , G06F1/04 , G06F5/06
CPC分类号： G06F1/12
摘要： A circuit and method for synchronizing signals between asynchronous clock domains within digital electronic circuits decouples asynchronous clocks. The timing of the slower clock is used to prevent read and write to counters so that write signals from the fast clock domain can be directly used in the slower clock domain when the counters are not toggling. This feature removes the need for sampling and holding the data on the fast clock, which would require consume additional power and require additional circuit area.
摘要翻译：用于在数字电子电路内的异步时钟域之间同步信号的电路和方法解耦异步时钟。较慢时钟的定时用于防止读取和写入计数器，以便当计数器不切换时，来自快速时钟域的写入信号可以直接用于较慢时钟域。该功能消除了对快速时钟采样和保持数据的需求，这将需要消耗额外的功率并需要额外的电路面积。

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