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1. 发明授权

US5296722A Electrically alterable resistive component stacked above a semiconductor substrate 失效
标题翻译：堆叠在半导体衬底之上的电可变电阻元件
公开(公告)号：US5296722A
公开(公告)日：1994-03-22
申请号：US9372
申请日：1993-01-26
申请人： Hanan Potash , Melvyn E. Genter , Bruce B. Roesner
发明人： Hanan Potash , Melvyn E. Genter , Bruce B. Roesner
IPC分类号： H01L27/112 , H01L45/00
CPC分类号： H01L27/112 , Y10S257/91
摘要： A memory cell includes a pair of spaced apart conductors on an insulating layer, and a novel electrically alterable resistive component between the conductors. This resistive component consists essentially of a single element semiconductor selected from the group of Si, Ge, C, and .alpha.-Sn, having a crystalline grain size which is smaller than polycrystalline. Dopant atoms in the semiconductor are limited to be less than 10.sup.17 atoms/CM.sup.3 ; and, such a doping range includes zero doping. All dopant atoms are interstitial in the semiconductor crystals and not substitutional.
摘要翻译：存储单元包括在绝缘层上的一对间隔开的导体，以及在导体之间的新颖的电可变电阻元件。该电阻元件基本上由选自Si，Ge，C和（α）-Sn的单元素半导体组成，其晶粒尺寸小于多晶。半导体中的掺杂原子被限制在小于1017原子/ CM3; 并且这种掺杂范围包括零掺杂。所有掺杂剂原子在半导体晶体中是间隙的，而不是取代的。

2. 发明授权

US4467409A Flexible computer architecture using arrays of standardized microprocessors customized for pipeline and parallel operations 失效
标题翻译：灵活的计算机架构，使用针对管道和并行操作定制的标准化微处理器阵列
公开(公告)号：US4467409A
公开(公告)日：1984-08-21
申请号：US175430
申请日：1980-08-05
申请人： Hanan Potash , Burton L. Levin , Melvyn E. Genter
发明人： Hanan Potash , Burton L. Levin , Melvyn E. Genter
IPC分类号： G06F9/30 , G06F15/78 , G06F9/28 , G06F15/16
CPC分类号： G06F15/7835 , G06F9/30
摘要： A flexible architecture for digital computers can be adapted to meet the many different functional requirements of several computer models. Each model includes an array of sequential logic units. These units include respective control memories for storing commands, means for sequentially fetching and executing selectable sequences of the commands, and soft functional structures for performing customized functions in response to the commands. Included within the soft functional structures are a plurality of selectable electrical contacts which customize the functional response of the structures to the commands. Except for these contacts and the content of the respective control memories, the units are substantially identical. All of the units in the array execute respective command sequences from their control memory to perform a single instruction for the computer model.
摘要翻译：数字计算机的灵活架构可以适应多种计算机模型的许多不同功能需求。每个模型包括一系列顺序逻辑单元。这些单元包括用于存储命令的各自的控制存储器，用于顺序地取出和执行可选择的命令序列的装置，以及用于响应于命令执行定制功能的软功能结构。包括在软功能结构内的是多个可选择的电触点，其定制结构对命令的功能响应。除了这些触点和各个控制存储器的内容之外，这些单元基本相同。阵列中的所有单元从其控制存储器执行相应的命令序列，以执行计算机模型的单个指令。

3. 发明授权

US5148256A Digital computer having an interconnect mechanism stacked above a semiconductor substrate 失效
标题翻译：具有堆叠在半导体衬底之上的互连机构的数字计算机
公开(公告)号：US5148256A
公开(公告)日：1992-09-15
申请号：US237429
申请日：1981-02-23
申请人： Hanan Potash , Melvyn E. Genter , Bruce B. Roesner
发明人： Hanan Potash , Melvyn E. Genter , Bruce B. Roesner
IPC分类号： H01L27/112
CPC分类号： H01L27/112 , Y10S257/91
摘要： In the disclosed computer, a plurality of register means for storing digital operands and control signals are in a semiconductor substrate; an arithmetic means for performing functional opertions on the operands are also in the substrate; an insulating layer covers the register means and the arithmetic means; and an interconnect matrix is on top of this insulating layer. The interconnect matrix includes pluralities of logic gates coupled through the insulating layer to the register means and arithmetic means and selectively interconnects them in response to the control signals.
摘要翻译：在所公开的计算机中，用于存储数字操作数和控制信号的多个寄存器装置在半导体衬底中; 用于对操作数执行功能操作的算术装置也在基板中; 绝缘层覆盖寄存器装置和算术装置; 并且互连矩阵位于该绝缘层的顶部。互连矩阵包括通过绝缘层耦合到寄存器装置和算术装置的多个逻辑门，并且响应于控制信号选择性地互连它们。

4. 发明授权

US4744024A Method of operating a bus in a data processing system via a repetitive three stage signal sequence 失效
标题翻译：通过重复的三级信号序列在数据处理系统中操作总线的方法
公开(公告)号：US4744024A
公开(公告)日：1988-05-10
申请号：US633662
申请日：1984-07-23
申请人： Hanan Potash , Melvyn E. Genter
发明人： Hanan Potash , Melvyn E. Genter
IPC分类号： G06F13/378 , G06F13/00
CPC分类号： G06F13/378
摘要： Disclosed is a data processing system which is comprised of a plurality of devices that carry on conversations with each other over a time-shared bus. These conversions can consist of a message from a device A to a device B which is immediately followed by a message from device B back to device A, or a message from device A to device B which is immediately followed by a message from device B to another device C, or a single message from device A to device B. In each case, the last device to receive a message assumes control of the bus; and it relinquishes this control by either sending a message to another device or by broadcasting a poll code to all devices on the bus.
摘要翻译：公开了一种数据处理系统，其由在时分公共总线上进行对话的多个设备组成。这些转换可以包括从设备A到设备B的消息，紧随其后是来自设备B的消息回到设备A，或者从设备A到设备B的消息，紧接着是来自设备B的消息另一个设备C或从设备A到设备B的单个消息。在每种情况下，接收消息的最后一个设备承担总线的控制; 并且通过向另一设备发送消息或通过向总线上的所有设备广播轮询代码来放弃该控制。

5. 发明授权

US4327355A Digital device with interconnect matrix 失效
标题翻译：具有互连矩阵的数字设备
公开(公告)号：US4327355A
公开(公告)日：1982-04-27
申请号：US162057
申请日：1980-06-23
申请人： Melvyn E. Genter , Hanan Potash
发明人： Melvyn E. Genter , Hanan Potash
IPC分类号： G06F9/22 , G06F7/00 , G06F9/30 , G06F15/78 , H04Q3/42 , G06F7/38
CPC分类号： G06F15/7842 , G06F15/7821
摘要： Disclosed is a digital device on a semiconductor chip, which is comprised of a plurality of storage means for storing digital signals therein, a plurality of functional means for performing functional operations on the digital signals, and an interconnect matrix. The matrix includes a plurality of input busses connected to receive signals from the storage means and the functional means, and a plurality of output busses connected to send signals to the storage means and functional means. The interconnect matrix further includes N sets of selectable electrical contacts where N is any positive integer. Each set selectively intercouples the input busses to the output busses in various parallel paths. Signals are transferred between the input and output busses through any one set of the N sets of electrical contacts in response to N respective control signals.
摘要翻译：公开了一种半导体芯片上的数字装置，其包括用于在其中存储数字信号的多个存储装置，用于对数字信号执行功能操作的多个功能装置和互连矩阵。该矩阵包括连接到从存储装置和功能装置接收信号的多个输入总线，以及连接到向存储装置和功能装置发送信号的多个输出总线。互连矩阵还包括N组可选择的电触点，其中N是任何正整数。每个组件选择性地将输入总线互连到各种并行路径中的输出总线。响应于N个相应的控制信号，信号通过N组电触点中的任何一组在输入和输出总线之间传送。

6. 发明申请

US20170083449A1 PROCESSOR WITH LOGICAL MENTOR 审中-公开
公开(公告)号：US20170083449A1
公开(公告)日：2017-03-23
申请号：US14863041
申请日：2015-09-23
申请人： Hanan Potash
发明人： Hanan Potash
IPC分类号： G06F12/10
CPC分类号： G06F12/10 , G06F8/41 , G06F9/00 , G06F9/34 , G06F9/4488 , G06F2212/65
摘要： A computing device includes a memory structure storing one or more Variables; and a logical mentor. The logical mentor is assigned to at least one of the one or more Variables and performs addressing operations with respect to the Variables to which it is assigned. In an embodiment, a method of computing includes storing one or more Variables in the memory of a computing device, assigning a logical mentor to the Variables; and performing, by the logical mentor, addressing operations with respect to the Variables.

7. 发明授权

US06340588B1 Matrices with memories 失效
标题翻译：有记忆的矩阵
公开(公告)号：US06340588B1
公开(公告)日：2002-01-22
申请号：US09051022
申请日：1998-09-22
申请人： Michael P. Nova , Hanan Potash
发明人： Michael P. Nova , Hanan Potash
IPC分类号： C12M134
CPC分类号： G11C13/0019 , B01J19/0046 , B01J2219/00283 , B01J2219/00295 , B01J2219/00299 , B01J2219/00308 , B01J2219/00333 , B01J2219/00344 , B01J2219/00461 , B01J2219/00463 , B01J2219/005 , B01J2219/00502 , B01J2219/0054 , B01J2219/00542 , B01J2219/00547 , B01J2219/00549 , B01J2219/00551 , B01J2219/00554 , B01J2219/0056 , B01J2219/00563 , B01J2219/00567 , B01J2219/00569 , B01J2219/00585 , B01J2219/0059 , B01J2219/00592 , B01J2219/00596 , B01J2219/00689 , B01J2219/00695 , B01J2219/0072 , B01J2219/00722 , B01J2219/00725 , B01L3/5027 , B01L3/502761 , B01L3/50825 , B01L2300/0609 , B82Y10/00 , C07H21/00 , C07K1/00 , C07K1/04 , C07K1/047 , C40B40/06 , C40B40/10 , C40B60/14 , C40B70/00 , G01N35/00732 , G01N35/00871 , G01N2015/149 , G01N2035/00782 , G01N2333/9121 , G01N2500/00 , G11C13/0014 , G11C13/025
摘要： Combinations, called matrices with memories, of matrix materials that are encoded with an optically readable code are provided. The matrix materials are those that are used in as supports in solid phase chemical and biochemical syntheses, immunoassays and hybridization reactions. The matrix materials may additionally include fluophors or other luminescent moieties to produce luminescing matrices with memories. The memories include electronic and optical storage media and also include optical memories, such as bar codes and other machine-readable codes. By virtue of this combination, molecules and biological particles, such as phage and viral particles and cells, that are in proximity or in physical contact with the matrix combination can be labeled by programming the memory with identifying information and can be identified by retrieving the stored information. Combinations of matrix materials, memories, and linked molecules and biological materials are also provided. The combinations have a multiplicity of applications, including combinatorial chemistry, isolation and purification of target macromolecules, capture and detection of macromolecules for analytical purposes, selective removal of contaminants, enzymatic catalysis, cell sorting, sensors and drug delivery, chemical modification and other uses. Methods for tagging molecules, biological particles and matrix support materials, immunoassays, receptor binding assays, scintillation proximity assays, non-radioactive proximity assays, and other methods are also provided. Sensors containing a memory in combination with a matrix are also provided.
摘要翻译：提供了用光学可读代码编码的矩阵材料的组合，称为具有存储器的矩阵。基质材料是在固相化学和生物化学合成，免疫测定和杂交反应中用作载体的基质材料。基质材料还可以包括荧光体或其它发光部分以产生具有记忆的发光基质。存储器包括电子和光学存储介质，并且还包括诸如条形码和其他机器可读代码的光学存储器。通过这种组合，可以通过用识别信息对存储器进行编程来标记与基质组合接近或物理接触的分子和生物颗粒，例如噬菌体和病毒颗粒和细胞，并且可以通过检索存储的信息。还提供了基质材料，记忆和连接分子和生物材料的组合。这些组合具有多种应用，包括组合化学，目标大分子的分离和纯化，用于分析目的的大分子的捕获和检测，污染物的选择性去除，酶催化，细胞分选，传感器和药物递送，化学修饰和其它用途。还提供了用于标记分子，生物颗粒和基质支持材料的方法，免疫测定，受体结合测定，闪烁亲和测定，非放射性邻近测定和其它方法。还提供了包含与基质结合的记忆体的传感器。

8. 发明授权

US4777615A Backplane structure for a computer superpositioning scalar and vector operations 失效
标题翻译：用于计算机的背板结构叠加标量和矢量操作
公开(公告)号：US4777615A
公开(公告)日：1988-10-11
申请号：US834942
申请日：1986-02-28
申请人： Hanan Potash
发明人： Hanan Potash
IPC分类号： G06F1/16 , G06F1/18 , G06F13/40 , H05K1/14 , H05K7/14
CPC分类号： H05K1/14 , G06F13/409 , H05K7/1445
摘要： A backplane structure for a computer includes first and second spaced apart backplane sections each having a series of spaced, vertical connector assemblies for receiving edge connectors of a series of parallel spaced apart circuit boards in a vertical orientation. Spaced bus lines run horizontally across each backplane section for interconnecting appropriate pins of the respective circuit board connectors. One of the backplane sections receives circuit boards of the memory section of a computer, and the other section receives the computer functional unit boards. A third backplane section extends between the first and second sections and has a series of spaced horizontal connector assemblies for receiving connector edges of a series of circuit boards in a horizontal orientation. At least some of the horizontal connector assemblies receive circuit boards of the buffer section of a computer. Each horizontal buffer board connector assembly is connected at each end to a respective selected portion of the bus lines of the first and second backplane sections, respectively, so a connected buffer board can act as a bridge between these sections.
摘要翻译：用于计算机的背板结构包括第一和第二间隔开的背板部分，每个底板部分具有一系列间隔开的垂直连接器组件，用于在垂直方向上接收一系列平行隔开的电路板的边缘连接器。间距的总线横跨每个背板部分水平运行，用于互连相应电路板连接器的相应引脚。背板部分之一接收计算机的存储器部分的电路板，另一部分接收计算机功能单元板。第三背板部分在第一和第二部分之间延伸并且具有一系列间隔开的水平连接器组件，用于在水平方向上接收一系列电路板的连接器边缘。至少一些水平连接器组件接收计算机的缓冲部分的电路板。每个水平缓冲板连接器组件在每一端分别连接到第一和第二背板部分的总线的相应选定部分，因此连接的缓冲板可以用作这些部分之间的桥梁。

9. 发明授权

US4538241A Address translation buffer 失效
标题翻译：地址转换缓冲区
公开(公告)号：US4538241A
公开(公告)日：1985-08-27
申请号：US513660
申请日：1983-07-14
申请人： Burton L. Levin , Andrew E. Phelps , Hanan Potash
发明人： Burton L. Levin , Andrew E. Phelps , Hanan Potash
IPC分类号： G06F12/10 , G06F13/00
CPC分类号： G06F12/1027
摘要： An apparatus is disclosed that translates virtual memory addresses into physical memory addresses. In particular, this apparatus comprises a plurality of rows of content addressable memory cells, a corresponding plurality of random access memory cells and another corresponding plurality of control circuits. The content addressable memory cells store the virtual memory addresses and the random access memory cells store the physical memory addresses. The control circuits are coupled to both the content addressable and the random access memory cells and are disposed for controlling the operation of the apparatus.
摘要翻译：公开了将虚拟存储器地址转换为物理存储器地址的装置。特别地，该装置包括多行内容可寻址存储单元，相应的多个随机存取存储单元和另一对应的多个控制电路。内容可寻址存储器单元存储虚拟存储器地址，并且随机存取存储器单元存储物理存储器地址。控制电路耦合到内容可寻址存储单元和随机存取存储单元两者，并被设置用于控制设备的操作。

10. 发明授权

US4393465A Digital device for time-multiplexing multiple tasks 失效
标题翻译：用于时分复用多个任务的数字设备
公开(公告)号：US4393465A
公开(公告)日：1983-07-12
申请号：US253717
申请日：1981-04-13
申请人： Hanan Potash
发明人： Hanan Potash
IPC分类号： G06F9/22 , G06F3/00 , G06F9/26 , G06F9/38 , G06F9/46 , G06F9/48 , G06F3/04
CPC分类号： G06F9/4812 , G06F9/3851 , G06F9/4881
摘要： A digital device time-multiplexes the execution of multiple tasks that are defined by respective sequences of control words in a control memory. In this device, the time-multiplexing is performed by sending control signals that are representative of respective resume addresses along with each output message sent by the device that calls for a response. These response messages are thereafter received by the device along with the control signals that were sent with the corresponding output message. Received response messages are thereafter operated on by the device by executing control words in the control memory beginning at the resume address represented by the received control signals.
摘要翻译：数字设备对由控制存储器中的各个控制字序列定义的多个任务的执行进行时间复用。在该装置中，通过发送表示各个恢复地址的控制信号以及由呼叫响应的设备发送的每个输出消息来执行时间复用。这些响应消息随后由与相应输出消息一起发送的控制信号一起被设备接收。接收的响应消息此后由设备通过在由所接收的控制信号表示的恢复地址开始的控制存储器中执行控制字来进行操作。

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