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1. 发明公开

CN108984470A 一种FPGA矿机算力的提升系统及方法无效转让
公开(公告)号：CN108984470A
公开(公告)日：2018-12-11
申请号：CN201810631891.9
申请日：2018-06-19
申请人：四川斐讯信息技术有限公司
发明人：滕达 , 卓尚坤
IPC分类号： G06F15/78
CPC分类号： G06F15/7835
摘要：本发明公开了一种FPGA矿机算力的提升系统及方法，该提升系统包括：分解模块，用于将哈希运算分解为多个子运算；多个子运算模块，用于分别接收上述分解模块所发送的子运算；并行处理模块，用于控制上述多个子运算模块并行处理上述各个子运算模块所接收的子运算。本发明的技术方案是通过将哈希运算分解为多个不同子运算的任务，将其分别发送至矿机内的多个子运算模块进行并行处理，实现了多任务输入，同时多个子运算多路并行进行处理，有效的提高了FPGA矿机整体的哈希运算速度，提高了FPGA矿机的运算能力即算力，具有较好的实用性。

2. 发明授权

US5068823A Programmable integrated circuit using topological and parametric data to selectively connect and configure different high level functional blocks thereof 失效
标题翻译：可编程集成电路使用拓扑和参数数据选择连接和配置不同的高级功能块
公开(公告)号：US5068823A
公开(公告)日：1991-11-26
申请号：US217616
申请日：1988-07-11
申请人： Jeffrey I. Robinson
发明人： Jeffrey I. Robinson
IPC分类号： G06F15/177 , G06F15/78
CPC分类号： G06F15/7867 , G06F15/177 , G06F15/7835
摘要： An apparatus architecture is provided which permits an easily programmed apparatus to serve as an equivalent of an integrated circuit chip, and/or as a building block for a large system. The apparatus is connected to a communications bus which receives apparatus parameter and topological information from a host processor and/or memory. The apparatus includes numerous functional blocks, a core, and a parametric bus. The functional blocks such as serial and parallel ports, D/A and A/D converters, biquad filters, etc. serve to process signal data and are connected in any desired manner through a switching matrix located in the core. The topology of the switching matrix is received via the communication bus. Parameters for the functional blocks are sent to the functional blocks via the communications bus, the core, and the parametric bus. Topological and/or parametric data may be burned into the switch matrix and functional blocks as permanent programmed memory, or held in programmable nonvolatile or volatile memory associated with the core and functional blocks. Signal data is typically received and transmitted via the serial and/or parallel ports and via the D/A and A/D converters (functional blocks) of the apparatus. The signal data is processed extremely quickly by having the parameterized functional blocks perform their operations on the signal data and by forwarding the results to another functional block via the topologically arranged switching matrix. Each apparatus can be made part of a larger wafer-scale system including several identical or architecturally similar apparatus by providing links between the cores of the apparatus.
摘要翻译：提供了一种装置架构，其允许易编程的装置用作集成电路芯片的等同物，和/或用作大型系统的构建块。该装置连接到从主处理器和/或存储器接收设备参数和拓扑信息的通信总线。该装置包括许多功能块，核心和参数总线。诸如串行和并行端口，D / A和A / D转换器，双二阶滤波器等功能块用于处理信号数据，并通过位于核心中的开关矩阵以任何期望的方式连接。交换矩阵的拓扑通过通信总线接收。功能块的参数通过通信总线，内核和参数总线发送到功能块。拓扑和/或参数数据可以被刻录到开关矩阵和功能块中作为永久编程存储器，或者保存在与核心和功能块相关联的可编程非易失性或易失性存储器中。信号数据通常经由串行和/或并行端口并经由设备的D / A和A / D转换器（功能块）来接收和发送。通过使参数化的功能块对信号数据执行其操作并且经由拓扑布置的开关矩阵将结果转发到另一功能块，来极快地处理信号数据。通过提供设备的核心之间的链接，每个装置可以被制成包括几个相同或结构上相似的装置的较大的晶片级系统的一部分。

3. 发明申请

WO2008105898A2 RECONFIGURABLE DATA PROCESSING SYSTEM 审中-公开
标题翻译：可重构数据处理系统
公开(公告)号：WO2008105898A2
公开(公告)日：2008-09-04
申请号：PCT/US2007/072833
申请日：2007-07-05
申请人： ITT MANUFACTURING ENTERPRISES, INC. , SALAMA, Yassir , SALAMA, Assem , FITZGERALD, Dennis
发明人： SALAMA, Yassir , SALAMA, Assem , FITZGERALD, Dennis
IPC分类号： H05K1/14 , H05K1/11
CPC分类号： H05K1/029 , G06F15/7835 , G06F15/7842 , H05K1/141 , H05K3/222 , H05K2201/10212 , H05K2201/10689
摘要： A reconfigurable processing system is provided that comprises a plurality of programmable processing modules arranged on a circuit board. Each of the programmable processing modules is capable of being populated by a programmable integrated circuit of a variety of processing capabilities. Conductive traces on the circuit board connect to the programmable processing modules and the conductive traces are arranged on the circuit board so as to accommodate use of the programmable integrated circuits of varying processing capabilities in the programmable processing modules without the need to alter conductive trace footprints on the circuit board for the programmable processing modules. At least one interface circuit arranged on the circuit board to interface signals to and from the circuit board.
摘要翻译：提供了一种可重构处理系统，其包括布置在电路板上的多个可编程处理模块。每个可编程处理模块能够由各种处理能力的可编程集成电路填充。电路板上的导电迹线连接到可编程处理模块，并且导电迹线布置在电路板上，以便适应在可编程处理模块中使用具有不同处理能力的可编程集成电路，而不需要改变导电迹线覆盖区用于可编程处理模块的电路板。布置在电路板上的至少一个接口电路，用于将信号与电路板接合。

4. 发明申请

WO2008105898A3 RECONFIGURABLE DATA PROCESSING SYSTEM 审中-公开
标题翻译：可重构数据处理系统
公开(公告)号：WO2008105898A3
公开(公告)日：2009-03-12
申请号：PCT/US2007072833
申请日：2007-07-05
申请人： ITT MFG ENTERPRISES INC , SALAMA YASSIR , SALAMA ASSEM , FITZGERALD DENNIS
发明人： SALAMA YASSIR , SALAMA ASSEM , FITZGERALD DENNIS
IPC分类号： H05K1/11
CPC分类号： H05K1/029 , G06F15/7835 , G06F15/7842 , H05K1/141 , H05K3/222 , H05K2201/10212 , H05K2201/10689
摘要： A reconfigurable processing system is provided that comprises a plurality of programmable processing modules arranged on a circuit board. Each of the programmable processing modules is capable of being populated by a programmable integrated circuit of a variety of processing capabilities. Conductive traces on the circuit board connect to the programmable processing modules and the conductive traces are arranged on the circuit board so as to accommodate use of the programmable integrated circuits of varying processing capabilities in the programmable processing modules without the need to alter conductive trace footprints on the circuit board for the programmable processing modules. At least one interface circuit arranged on the circuit board to interface signals to and from the circuit board.
摘要翻译：提供了一种可重构处理系统，其包括布置在电路板上的多个可编程处理模块。每个可编程处理模块能够由各种处理能力的可编程集成电路填充。电路板上的导电迹线连接到可编程处理模块，并且导电迹线布置在电路板上，以便适应在可编程处理模块中使用具有不同处理能力的可编程集成电路，而不需要改变导电迹线覆盖区用于可编程处理模块的电路板。布置在电路板上的至少一个接口电路，用于将信号与电路板接合。

5. 发明公开

EP0325419A3 Method and apparatus for caching interlock variables in an integrated cache memory 失效
标题翻译：用于在集成的高速缓存存储器中缓存互锁变量的方法和设备
公开(公告)号：EP0325419A3
公开(公告)日：1991-01-02
申请号：EP89300432.5
申请日：1989-01-18
申请人： ADVANCED MICRO DEVICES, INC.
发明人： Baror, Gigy
IPC分类号： G06F12/08
CPC分类号： G06F12/0888 , G06F12/0837 , G06F12/0848 , G06F15/7835
摘要： Methods and apparatus are disclosed for supporting the caching of interlock variables in cache memory units employed in multiprocessor and/or multitasking environments. The preferred embodiment of the invention includes methods and apparatus for selectively treating interlock variables as cachable or non-cachable. The disclosed methods and apparatus are suitable for supporting high speed data and instruction processing applications in both RISC and non-RISC architecture environments, can be integrated on a single chip and allows for better performance and utilization of the computer system bus structure since most of the interlock variable accesses are faster and do not appear on the memory bus (only in the cache).

6. 发明公开

EP0325419A2 Method and apparatus for caching interlock variables in an integrated cache memory 失效
标题翻译：在一个集成的高速缓存写入相互锁定变量的方法和设备。
公开(公告)号：EP0325419A2
公开(公告)日：1989-07-26
申请号：EP89300432.5
申请日：1989-01-18
申请人： ADVANCED MICRO DEVICES, INC.
发明人： Baror, Gigy
IPC分类号： G06F12/08
CPC分类号： G06F12/0888 , G06F12/0837 , G06F12/0848 , G06F15/7835
摘要： Methods and apparatus are disclosed for supporting the caching of interlock variables in cache memory units employed in multiprocessor and/or multitasking environments. The preferred embodiment of the invention includes methods and apparatus for selectively treating interlock variables as cachable or non-cachable. The disclosed methods and apparatus are suitable for supporting high speed data and instruction processing applications in both RISC and non-RISC architecture environments, can be integrated on a single chip and allows for better performance and utilization of the computer system bus structure since most of the interlock variable accesses are faster and do not appear on the memory bus (only in the cache).
摘要翻译：的方法和装置游离缺失圆盘用于支撑联锁变量的高速缓存在多处理器和/或多任务环境中采用的高速缓冲存储器单元。本发明的优选实施例包括用于选择性治疗联锁变量作为可超高速缓存或非超高速缓存的方法和装置。盘游离缺失方法和装置适用于支撑在RISC和非RISC体系结构环境中的高速数据和指令处理应用中，可以在单个芯片上集成并且由于大部分的允许获得更好的性能和计算机系统总线结构的利用联锁可变访问更快，并且不出现（仅在高速缓冲存储器）的存储器总线上。

7. 发明公开

US20230195682A1 CHIPLET SYSTEM AND POSITIONING METHOD THEREOF 审中-公开
公开(公告)号：US20230195682A1
公开(公告)日：2023-06-22
申请号：US18070514
申请日：2022-11-29
申请人： Sunplus Technology Co., Ltd.
发明人： Hsing-Sheng HUANG , Hao-Chang CHANG , Ming-Chang SU , Hwan-Rei LEE
IPC分类号： G06F15/173 , G06F15/78 , G06F13/40
CPC分类号： G06F15/17306 , G06F15/7835 , G06F13/4027
摘要： A chiplet system and a positioning method thereof are provided. The positioning method of the chiplet system includes the following steps. Two end chiplets and a plurality of middle chiplets are classified. A quantity calculation packet is transmitted and accumulated from each of the end chiplets towards another end to analyze a quantity of middle chiplets. A serial number comparison packet is transmitted and accumulated from each of the middle chiplets connected to one of the end chiplets towards another end to set a starting point. An identify number setting packet is transmitted and accumulated from the middle chiplet set as the starting point towards another end to set a positioning number of each of the middle chiplets.

8. 发明授权

US08004855B2 Reconfigurable data processing system 有权
标题翻译：可重构数据处理系统
公开(公告)号：US08004855B2
公开(公告)日：2011-08-23
申请号：US11481884
申请日：2006-07-07
申请人： Yassir Salama , Assem Salama , Dennis Fitzgerald
发明人： Yassir Salama , Assem Salama , Dennis Fitzgerald
IPC分类号： H05K1/11
CPC分类号： H05K1/029 , G06F15/7835 , G06F15/7842 , H05K1/141 , H05K3/222 , H05K2201/10212 , H05K2201/10689
摘要： A reconfigurable processing system is provided that comprises a plurality of programmable processing modules arranged on a circuit board. Each of the programmable processing modules is capable of being populated by a programmable integrated circuit of a variety of processing capabilities. Conductive traces on the circuit board connect to the programmable processing modules and the conductive traces are arranged on the circuit board so as to accommodate use of the programmable integrated circuits of varying processing capabilities in the programmable processing modules without the need to alter conductive trace footprints on the circuit board for the programmable processing modules. At least one interface circuit arranged on the circuit board to interface signals to and from the circuit board.
摘要翻译：提供了一种可重构处理系统，其包括布置在电路板上的多个可编程处理模块。每个可编程处理模块能够由各种处理能力的可编程集成电路填充。电路板上的导电迹线连接到可编程处理模块，并且导电迹线布置在电路板上，以便适应在可编程处理模块中使用具有不同处理能力的可编程集成电路，而不需要改变导电迹线覆盖区用于可编程处理模块的电路板。布置在电路板上的至少一个接口电路，用于将信号与电路板接合。

9. 发明授权

US4086626A Microprocessor system 失效
标题翻译：微处理器系统
公开(公告)号：US4086626A
公开(公告)日：1978-04-25
申请号：US693811
申请日：1976-06-07
申请人： David H. Chung
发明人： David H. Chung
IPC分类号： G06F1/04 , G06F1/06 , G06F15/78 , G06F13/00
CPC分类号： G06F15/7835 , G06F1/04 , G06F1/06
摘要： A microprocessor system having at least two separate scale integration devices. A first of the two large scale integration devices is a central processing unit formed on a single semiconductor die, and the second large scale integration device is a memory circuit formed on a separate single semiconductor die. The term "die" as used herein is conventional and refers to a unitary semiconductor body or chip. The central processing unit requires an external program counter which contains memory addresses of instruction codes to be used by the central processing unit. The memory device is electrically coupled to the central processing unit and includes a memory for storing the instruction codes, and a program counter for addressing the memory. Provision is made to incorporate additional memory circuits to expand the size and capability of the microprocessor system. System interrupt circuitry is also provided for interrupting system operation to change to a new sequence of instruction codes.
摘要翻译：一种具有至少两个分开的规模集成装置的微处理器系统。两个大规模集成装置中的第一个是形成在单个半导体管芯上的中央处理单元，第二大规模集成装置是形成在单独的半导体管芯上的存储电路。本文所用的术语“裸片”是常规的，并且是指整体半导体本体或芯片。中央处理单元需要外部程序计数器，其中包含中央处理单元要使用的指令代码的存储器地址。存储器件电耦合到中央处理单元，并且包括用于存储指令代码的存储器和用于寻址存储器的程序计数器。提供了额外的存储器电路以扩大微处理器系统的尺寸和能力。还提供系统中断电路用于中断系统操作以改变为新的指令代码序列。

10. 发明授权

US08239539B2 Management processors cooperating to control partition resources 有权
标题翻译：合作管理处理器来控制分区资源
公开(公告)号：US08239539B2
公开(公告)日：2012-08-07
申请号：US12639360
申请日：2009-12-16
申请人： Kenneth C. Duisenberg , Stephen B. Lyle , Rajeev Grover , Loren M. Koehler , Ivan Farkas
发明人： Kenneth C. Duisenberg , Stephen B. Lyle , Rajeev Grover , Loren M. Koehler , Ivan Farkas
IPC分类号： G06F13/00
CPC分类号： G06F15/7835 , G06F9/5077
摘要： Systems, methods and computing components are provided for allocating a plurality of computing components among one or more logical partitions. Each of the plurality of computing components may have a management processor that is configured to assume a role among management processors of a partition. Each management processor may then cooperate with other management processors of the partition to control resources of the partition.
摘要翻译：系统，方法和计算组件被提供用于在一个或多个逻辑分区之间分配多个计算组件。多个计算组件中的每一个可以具有被配置为在分区的管理处理器中承担角色的管理处理器。然后，每个管理处理器可以与分区的其他管理处理器协作来控制分区的资源。

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