专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US5296722A Electrically alterable resistive component stacked above a semiconductor substrate 失效
标题翻译：堆叠在半导体衬底之上的电可变电阻元件
公开(公告)号：US5296722A
公开(公告)日：1994-03-22
申请号：US9372
申请日：1993-01-26
申请人： Hanan Potash , Melvyn E. Genter , Bruce B. Roesner
发明人： Hanan Potash , Melvyn E. Genter , Bruce B. Roesner
IPC分类号： H01L27/112 , H01L45/00
CPC分类号： H01L27/112 , Y10S257/91
摘要： A memory cell includes a pair of spaced apart conductors on an insulating layer, and a novel electrically alterable resistive component between the conductors. This resistive component consists essentially of a single element semiconductor selected from the group of Si, Ge, C, and .alpha.-Sn, having a crystalline grain size which is smaller than polycrystalline. Dopant atoms in the semiconductor are limited to be less than 10.sup.17 atoms/CM.sup.3 ; and, such a doping range includes zero doping. All dopant atoms are interstitial in the semiconductor crystals and not substitutional.
摘要翻译：存储单元包括在绝缘层上的一对间隔开的导体，以及在导体之间的新颖的电可变电阻元件。该电阻元件基本上由选自Si，Ge，C和（α）-Sn的单元素半导体组成，其晶粒尺寸小于多晶。半导体中的掺杂原子被限制在小于1017原子/ CM3; 并且这种掺杂范围包括零掺杂。所有掺杂剂原子在半导体晶体中是间隙的，而不是取代的。

2. 发明授权

US5148256A Digital computer having an interconnect mechanism stacked above a semiconductor substrate 失效
标题翻译：具有堆叠在半导体衬底之上的互连机构的数字计算机
公开(公告)号：US5148256A
公开(公告)日：1992-09-15
申请号：US237429
申请日：1981-02-23
申请人： Hanan Potash , Melvyn E. Genter , Bruce B. Roesner
发明人： Hanan Potash , Melvyn E. Genter , Bruce B. Roesner
IPC分类号： H01L27/112
CPC分类号： H01L27/112 , Y10S257/91
摘要： In the disclosed computer, a plurality of register means for storing digital operands and control signals are in a semiconductor substrate; an arithmetic means for performing functional opertions on the operands are also in the substrate; an insulating layer covers the register means and the arithmetic means; and an interconnect matrix is on top of this insulating layer. The interconnect matrix includes pluralities of logic gates coupled through the insulating layer to the register means and arithmetic means and selectively interconnects them in response to the control signals.
摘要翻译：在所公开的计算机中，用于存储数字操作数和控制信号的多个寄存器装置在半导体衬底中; 用于对操作数执行功能操作的算术装置也在基板中; 绝缘层覆盖寄存器装置和算术装置; 并且互连矩阵位于该绝缘层的顶部。互连矩阵包括通过绝缘层耦合到寄存器装置和算术装置的多个逻辑门，并且响应于控制信号选择性地互连它们。

3. 发明授权

US4327355A Digital device with interconnect matrix 失效
标题翻译：具有互连矩阵的数字设备
公开(公告)号：US4327355A
公开(公告)日：1982-04-27
申请号：US162057
申请日：1980-06-23
申请人： Melvyn E. Genter , Hanan Potash
发明人： Melvyn E. Genter , Hanan Potash
IPC分类号： G06F9/22 , G06F7/00 , G06F9/30 , G06F15/78 , H04Q3/42 , G06F7/38
CPC分类号： G06F15/7842 , G06F15/7821
摘要： Disclosed is a digital device on a semiconductor chip, which is comprised of a plurality of storage means for storing digital signals therein, a plurality of functional means for performing functional operations on the digital signals, and an interconnect matrix. The matrix includes a plurality of input busses connected to receive signals from the storage means and the functional means, and a plurality of output busses connected to send signals to the storage means and functional means. The interconnect matrix further includes N sets of selectable electrical contacts where N is any positive integer. Each set selectively intercouples the input busses to the output busses in various parallel paths. Signals are transferred between the input and output busses through any one set of the N sets of electrical contacts in response to N respective control signals.
摘要翻译：公开了一种半导体芯片上的数字装置，其包括用于在其中存储数字信号的多个存储装置，用于对数字信号执行功能操作的多个功能装置和互连矩阵。该矩阵包括连接到从存储装置和功能装置接收信号的多个输入总线，以及连接到向存储装置和功能装置发送信号的多个输出总线。互连矩阵还包括N组可选择的电触点，其中N是任何正整数。每个组件选择性地将输入总线互连到各种并行路径中的输出总线。响应于N个相应的控制信号，信号通过N组电触点中的任何一组在输入和输出总线之间传送。

4. 发明授权

US4467409A Flexible computer architecture using arrays of standardized microprocessors customized for pipeline and parallel operations 失效
标题翻译：灵活的计算机架构，使用针对管道和并行操作定制的标准化微处理器阵列
公开(公告)号：US4467409A
公开(公告)日：1984-08-21
申请号：US175430
申请日：1980-08-05
申请人： Hanan Potash , Burton L. Levin , Melvyn E. Genter
发明人： Hanan Potash , Burton L. Levin , Melvyn E. Genter
IPC分类号： G06F9/30 , G06F15/78 , G06F9/28 , G06F15/16
CPC分类号： G06F15/7835 , G06F9/30
摘要： A flexible architecture for digital computers can be adapted to meet the many different functional requirements of several computer models. Each model includes an array of sequential logic units. These units include respective control memories for storing commands, means for sequentially fetching and executing selectable sequences of the commands, and soft functional structures for performing customized functions in response to the commands. Included within the soft functional structures are a plurality of selectable electrical contacts which customize the functional response of the structures to the commands. Except for these contacts and the content of the respective control memories, the units are substantially identical. All of the units in the array execute respective command sequences from their control memory to perform a single instruction for the computer model.
摘要翻译：数字计算机的灵活架构可以适应多种计算机模型的许多不同功能需求。每个模型包括一系列顺序逻辑单元。这些单元包括用于存储命令的各自的控制存储器，用于顺序地取出和执行可选择的命令序列的装置，以及用于响应于命令执行定制功能的软功能结构。包括在软功能结构内的是多个可选择的电触点，其定制结构对命令的功能响应。除了这些触点和各个控制存储器的内容之外，这些单元基本相同。阵列中的所有单元从其控制存储器执行相应的命令序列，以执行计算机模型的单个指令。

5. 发明授权

US4744024A Method of operating a bus in a data processing system via a repetitive three stage signal sequence 失效
标题翻译：通过重复的三级信号序列在数据处理系统中操作总线的方法
公开(公告)号：US4744024A
公开(公告)日：1988-05-10
申请号：US633662
申请日：1984-07-23
申请人： Hanan Potash , Melvyn E. Genter
发明人： Hanan Potash , Melvyn E. Genter
IPC分类号： G06F13/378 , G06F13/00
CPC分类号： G06F13/378
摘要： Disclosed is a data processing system which is comprised of a plurality of devices that carry on conversations with each other over a time-shared bus. These conversions can consist of a message from a device A to a device B which is immediately followed by a message from device B back to device A, or a message from device A to device B which is immediately followed by a message from device B to another device C, or a single message from device A to device B. In each case, the last device to receive a message assumes control of the bus; and it relinquishes this control by either sending a message to another device or by broadcasting a poll code to all devices on the bus.
摘要翻译：公开了一种数据处理系统，其由在时分公共总线上进行对话的多个设备组成。这些转换可以包括从设备A到设备B的消息，紧随其后是来自设备B的消息回到设备A，或者从设备A到设备B的消息，紧接着是来自设备B的消息另一个设备C或从设备A到设备B的单个消息。在每种情况下，接收消息的最后一个设备承担总线的控制; 并且通过向另一设备发送消息或通过向总线上的所有设备广播轮询代码来放弃该控制。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式