专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20090212329A1 SUPER HYBRID SOI CMOS DEVICES 失效
标题翻译：超级混合SOI CMOS器件
公开(公告)号：US20090212329A1
公开(公告)日：2009-08-27
申请号：US12434247
申请日：2009-05-01
申请人： Meikei Ieong , Qiqing C. Ouyang
发明人： Meikei Ieong , Qiqing C. Ouyang
IPC分类号： H01L29/04
CPC分类号： H01L21/84 , H01L21/823807 , H01L21/823878 , H01L27/1203 , H01L27/1207 , H01L29/7843
摘要： The present invention provides semiconductor structures comprised of stressed channels on hybrid oriented. In particular, the semiconductor structures include a first active area having a first stressed semiconductor surface layer of a first crystallographic orientation located on a surface of a buried insulating material and a second active area having a second stressed semiconductor surface layer of a second crystallographic orientation located on a surface of a dielectric material. A trench isolation region is located between the first and second active area, and the trench isolation region is partially filled with a trench dielectric material and the dielectric material that is present underneath said second stressed semiconductor surface layer. The dielectric material within the trench isolation region has lower stress compared to that is used in conventional STI process and it is laterally abuts at least the second stressed semiconductor surface layer and extends to an upper surface of the trench isolation region.
摘要翻译：本发明提供由混合取向的应力通道构成的半导体结构。特别地，半导体结构包括第一有源区，其具有位于掩埋绝缘材料的表面上的第一晶体取向的第一应力半导体表面层和具有位于第二晶体取向的第二应力半导体表面层的第二有源区在电介质材料的表面上。沟槽隔离区域位于第一和第二有源区域之间，并且沟槽隔离区域部分地填充有沟槽电介质材料和位于所述第二应力半导体表面层下方的电介质材料。与常规STI工艺中使用的沟槽隔离区域中的电介质材料相比具有较低的应力，并且它至少侧向邻接第二应力半导体表面层并且延伸到沟槽隔离区域的上表面。

2. 发明授权

US07348611B2 Strained complementary metal oxide semiconductor (CMOS) on rotated wafers and methods thereof 有权
标题翻译：旋转晶片上的应变互补金属氧化物半导体（CMOS）及其方法
公开(公告)号：US07348611B2
公开(公告)日：2008-03-25
申请号：US11112820
申请日：2005-04-22
申请人： Meikei Ieong , Qiqing C. Ouyang , Kern Rim
发明人： Meikei Ieong , Qiqing C. Ouyang , Kern Rim
IPC分类号： H01L29/73
CPC分类号： H01L21/823807 , H01L27/0922 , H01L29/6656 , H01L29/6659 , H01L29/7833 , H01L29/7843
摘要： The present invention provides CMOS structures including at least one strained pFET that is located on a rotated semiconductor substrate to improve the device performance. Specifically, the present invention utilizes a Si-containing semiconductor substrate having a (100) crystal orientation in which the substrate is rotated by about 45° such that the CMOS device channels are located along the direction. Strain can be induced upon the CMOS structure including at least a pFET and optionally an nFET, particularly the channels, by forming a stressed liner about the FET, by forming embedded stressed wells in the substrate, or by utilizing a combination of embedded stressed wells and a stressed liner. The present invention also provides methods for fabricating the aforesaid semiconductor structures.
摘要翻译：本发明提供CMOS结构，其包括位于旋转的半导体衬底上的至少一个应变pFET，以改善器件性能。具体地，本发明利用具有（100）晶体取向的含Si半导体衬底，其中衬底旋转约45°，使得CMOS器件沟道沿<100>方向定位。通过在衬底中形成嵌入的应力阱，或者通过利用嵌入的应力阱的组合，或者通过利用嵌入的应力阱的组合，可以在包括至少pFET和任选的nFET，特别是沟道的CMOS结构上诱导应变，一个紧张的班轮。本发明还提供了制造上述半导体结构的方法。

3. 发明授权

US07547641B2 Super hybrid SOI CMOS devices 失效
公开(公告)号：US07547641B2
公开(公告)日：2009-06-16
申请号：US11758454
申请日：2007-06-05
申请人： Meikei Ieong , Qiqing C. Ouyang
发明人： Meikei Ieong , Qiqing C. Ouyang
IPC分类号： H01L21/8238
CPC分类号： H01L21/84 , H01L21/823807 , H01L21/823878 , H01L27/1203 , H01L27/1207 , H01L29/7843
摘要： The present invention provides semiconductor structures comprised of stressed channels on hybrid oriented. In particular, the semiconductor structures include a first active area having a first stressed semiconductor surface layer of a first crystallographic orientation located on a surface of a buried insulating material and a second active area having a second stressed semiconductor surface layer of a second crystallographic orientation located on a surface of a dielectric material. A trench isolation region is located between the first and second active area, and the trench isolation region is partially filled with a trench dielectric material and the dielectric material that is present underneath said second stressed semiconductor surface layer. The dielectric material within the trench isolation region has lower stress compared to that is used in conventional STI process and it is laterally abuts at least the second stressed semiconductor surface layer and extends to an upper surface of the trench isolation region.

4. 发明授权

US07619300B2 Super hybrid SOI CMOS devices 失效
标题翻译：超级混合SOI CMOS器件
公开(公告)号：US07619300B2
公开(公告)日：2009-11-17
申请号：US12434247
申请日：2009-05-01
申请人： Meikei Ieong , Qiqing C. Ouyang
发明人： Meikei Ieong , Qiqing C. Ouyang
IPC分类号： H01L29/04
CPC分类号： H01L21/84 , H01L21/823807 , H01L21/823878 , H01L27/1203 , H01L27/1207 , H01L29/7843
摘要： The present invention provides semiconductor structures comprised of stressed channels on hybrid oriented. In particular, the semiconductor structures include a first active area having a first stressed semiconductor surface layer of a first crystallographic orientation located on a surface of a buried insulating material and a second active area having a second stressed semiconductor surface layer of a second crystallographic orientation located on a surface of a dielectric material. A trench isolation region is located between the first and second active area, and the trench isolation region is partially filled with a trench dielectric material and the dielectric material that is present underneath said second stressed semiconductor surface layer. The dielectric material within the trench isolation region has lower stress compared to that is used in conventional STI process and it is laterally abuts at least the second stressed semiconductor surface layer and extends to an upper surface of the trench isolation region.
摘要翻译：本发明提供由混合取向的应力通道构成的半导体结构。特别地，半导体结构包括第一有源区，其具有位于掩埋绝缘材料的表面上的第一晶体取向的第一应力半导体表面层和具有位于第二晶体取向的第二应力半导体表面层的第二有源区在电介质材料的表面上。沟槽隔离区域位于第一和第二有源区域之间，并且沟槽隔离区域部分地填充有沟槽电介质材料和位于所述第二应力半导体表面层下方的电介质材料。与常规STI工艺中使用的沟槽隔离区域中的电介质材料相比具有较低的应力，并且它至少侧向邻接第二应力半导体表面层并且延伸到沟槽隔离区域的上表面。

5. 发明授权

US07687829B2 Stressed field effect transistors on hybrid orientation substrate 失效
标题翻译：混合取向衬底上强调场效应晶体管
公开(公告)号：US07687829B2
公开(公告)日：2010-03-30
申请号：US12144250
申请日：2008-06-23
申请人： Dureseti Chidambarrao , Judson R. Holt , Meikei Ieong , Qiqing C. Ouyang , Siddhartha Panda
发明人： Dureseti Chidambarrao , Judson R. Holt , Meikei Ieong , Qiqing C. Ouyang , Siddhartha Panda
IPC分类号： H01L29/04
CPC分类号： H01L29/045 , H01L21/823807 , H01L29/7843
摘要： A semiconductor structure having improved carrier mobility is provided. The semiconductor structures includes a hybrid oriented semiconductor substrate having at least two planar surfaces of different crystallographic orientation, and at least one CMOS device located on each of the planar surfaces of different crystallographic orientation, wherein each CMOS device has a stressed channel. The present invention also provides methods of fabricating the same. In general terms, the inventive method includes providing a hybrid oriented substrate having at least two planar surfaces of different crystallographic orientation, and forming at least one CMOS device on each of the planar surfaces of different crystallographic orientation, wherein each CMOS device has a stressed channel.
摘要翻译：提供了具有改进的载流子迁移率的半导体结构。半导体结构包括具有不同晶体取向的至少两个平坦表面的混合取向半导体衬底，以及位于不同结晶取向的每个平面上的至少一个CMOS器件，其中每个CMOS器件具有应力通道。本发明还提供了制造该方法的方法。一般来说，本发明的方法包括提供具有至少两个具有不同晶体取向的平面表面的混合取向衬底，以及在不同结晶取向的每个平面上形成至少一个CMOS器件，其中每个CMOS器件具有受压沟道。

6. 发明申请

US20080303090A1 SUPER HYBRID SOI CMOS DEVICES 失效
标题翻译：超级混合SOI CMOS器件
公开(公告)号：US20080303090A1
公开(公告)日：2008-12-11
申请号：US11758454
申请日：2007-06-05
申请人： Meikei Ieong , Qiqing C. Ouyang
发明人： Meikei Ieong , Qiqing C. Ouyang
IPC分类号： H01L21/8238 , H01L27/12
CPC分类号： H01L21/84 , H01L21/823807 , H01L21/823878 , H01L27/1203 , H01L27/1207 , H01L29/7843
摘要： The present invention provides semiconductor structures comprised of stressed channels on hybrid oriented. In particular, the semiconductor structures include a first active area having a first stressed semiconductor surface layer of a first crystallographic orientation located on a surface of a buried insulating material and a second active area having a second stressed semiconductor surface layer of a second crystallographic orientation located on a surface of a dielectric material. A trench isolation region is located between the first and second active area, and the trench isolation region is partially filled with a trench dielectric material and the dielectric material that is present underneath said second stressed semiconductor surface layer. The dielectric material within the trench isolation region has lower stress compared to that is used in conventional STI process and it is laterally abuts at least the second stressed semiconductor surface layer and extends to an upper surface of the trench isolation region.
摘要翻译：本发明提供由混合取向的应力通道构成的半导体结构。特别地，半导体结构包括第一有源区，其具有位于掩埋绝缘材料的表面上的第一晶体取向的第一应力半导体表面层和具有位于第二晶体取向的第二应力半导体表面层的第二有源区在电介质材料的表面上。沟槽隔离区域位于第一和第二有源区域之间，并且沟槽隔离区域部分地填充有沟槽电介质材料和位于所述第二应力半导体表面层下方的电介质材料。与常规STI工艺中使用的沟槽隔离区域中的电介质材料相比具有较低的应力，并且它至少侧向邻接第二应力半导体表面层并且延伸到沟槽隔离区域的上表面。

7. 发明申请

US20080251817A1 STRESSED FIELD EFFECT TRANSISTORS ON HYBRID ORIENTATION SUBSTRATE 失效
标题翻译：混合定向衬底上的应力场效应晶体管
公开(公告)号：US20080251817A1
公开(公告)日：2008-10-16
申请号：US12144250
申请日：2008-06-23
申请人： Dureseti Chidambarrao , Judson R. Holt , Meikei Ieong , Qiqing C. Ouyang , Siddhartha Panda
发明人： Dureseti Chidambarrao , Judson R. Holt , Meikei Ieong , Qiqing C. Ouyang , Siddhartha Panda
IPC分类号： H01L29/04
CPC分类号： H01L29/045 , H01L21/823807 , H01L29/7843
摘要： A semiconductor structure having improved carrier mobility is provided. The semiconductor structures includes a hybrid oriented semiconductor substrate having at least two planar surfaces of different crystallographic orientation, and at least one CMOS device located on each of the planar surfaces of different crystallographic orientation, wherein each CMOS device has a stressed channel. The present invention also provides methods of fabricating the same. In general terms, the inventive method includes providing a hybrid oriented substrate having at least two planar surfaces of different crystallographic orientation, and forming at least one CMOS device on each of the planar surfaces of different crystallographic orientation, wherein each CMOS device has a stressed channel.
摘要翻译：提供了具有改进的载流子迁移率的半导体结构。半导体结构包括具有不同晶体取向的至少两个平坦表面的混合取向半导体衬底，以及位于不同结晶取向的每个平面上的至少一个CMOS器件，其中每个CMOS器件具有应力通道。本发明还提供了制造它们的方法。一般来说，本发明的方法包括提供具有至少两个具有不同晶体取向的平面表面的混合取向衬底，以及在不同结晶取向的每个平面上形成至少一个CMOS器件，其中每个CMOS器件具有受压沟道。

8. 发明申请

US20080171413A1 Method of Reducing Detrimental STI-Induced Stress in MOSFET Channels 有权
标题翻译：降低MOSFET通道中有害的STI诱导应力的方法
公开(公告)号：US20080171413A1
公开(公告)日：2008-07-17
申请号：US11623935
申请日：2007-01-17
申请人： Meikei Leong , Qiqing C. Ouyang , Chun-Yung Sung
发明人： Meikei Leong , Qiqing C. Ouyang , Chun-Yung Sung
IPC分类号： H01L21/26 , H01L21/8238
CPC分类号： H01L21/823878 , H01L21/823807 , H01L29/1083 , H01L29/665 , H01L29/7846
摘要： A method for reducing STI processing induced stress on a substrate during fabrication of a MOSFET. The method includes providing a substrate, wells (including dopants), and STIs in an upper layer of the substrate. A layer of an oxide substance is formed on a top surface of the upper layer of the substrate covering the STIs. A layer of a nitride substance is formed over the oxide layer. The substrate is annealed using temperatures greater than 1000° C. to activate the dopants in the wells which results in less stress on the STIs and hence less stress in the channels because of the nitride substance layer. The nitride and oxide substance layers are then stripped off the substrate, and CMOS fabrication is continued. The low stress remains in the channels if the thermal budget in following processes are low by using low temperature RTA and/or laser anneal.
摘要翻译：一种在制造MOSFET期间减少STI处理引起的衬底上的应力的方法。该方法包括在衬底的上层中提供衬底，阱（包括掺杂剂）和STI。在覆盖STI的衬底的上层的顶表面上形成氧化物层。在氧化物层上形成氮化物层。使用大于1000℃的温度对衬底进行退火，以激活阱中的掺杂剂，这导致STI上的应力较小，因此由于氮化物物质层而导致通道中的较小的应力。然后将氮化物和氧化物物质层从衬底上剥离，继续进行CMOS制造。如果通过使用低温RTA和/或激光退火，以下过程中的热预算为低，则低应力保留在通道中。

9. 发明授权

US07354822B2 Method of forming a MOSFET with dual work function materials 有权
标题翻译：用双功能材料形成MOSFET的方法
公开(公告)号：US07354822B2
公开(公告)日：2008-04-08
申请号：US11553072
申请日：2006-10-26
申请人： Xiangdong Chen , Geng Wang , Yujun Li , Qiqing C. Ouyang
发明人： Xiangdong Chen , Geng Wang , Yujun Li , Qiqing C. Ouyang
IPC分类号： H01L21/8242
CPC分类号： H01L29/66181 , H01L27/10864
摘要： A vertical pass transistor used in a DRAM cell for maintaining a low total leakage current and providing adequate drive current is described together with a method of fabricating such a device. The transistor gate is engineered in lieu of the channel. The vertical pass transistor for the DRAM cell incorporates two gate materials having different work functions. The gate material near the storage node is n-type doped polysilicon. The gate material near the bit line diffusion is made of silicide or metal having a higher work function than the n-polysilicon. The novel device structure shows several advantages: the channel doping is reduced while maintaining a high Vt and a low sub-threshold leakage current; the carrier mobility improves with the reduced channel doping; the body effect of the device is reduced which improves the write back current; and the sub-threshold swing is reduced because of the low channel doping.
摘要翻译：在DRAM单元中使用的用于保持低总漏电流并提供足够的驱动电流的垂直传输晶体管与制造这种器件的方法一起被描述。晶体管栅极被设计代替通道。用于DRAM单元的垂直传输晶体管包括具有不同功函数的两个栅极材料。存储节点附近的栅极材料为n型掺杂多晶硅。位线扩散附近的栅极材料由具有比n-多晶硅更高的功函数的硅化物或金属制成。该新颖的器件结构显示出几个优点：沟道掺杂减少，同时保持高Vt和低的亚阈值漏电流; 载流子迁移率随着沟道掺杂的降低而提高; 减少了器件的体效，提高了回写电流; 并且由于低通道掺杂，子阈值摆幅减小。

10. 发明申请

US20120208356A1 Device component forming method with a trim step prior to sidewall image transfer (SIT) processing 审中-公开
标题翻译：在侧壁图像转印（SIT）处理之前具有修整步骤的装置部件形成方法
公开(公告)号：US20120208356A1
公开(公告)日：2012-08-16
申请号：US13456282
申请日：2012-04-26
申请人： Toshiharu Furukawa , David V. Horak , Charles W. Koburger, III , Qiqing C. Ouyang
发明人： Toshiharu Furukawa , David V. Horak , Charles W. Koburger, III , Qiqing C. Ouyang
IPC分类号： H01L21/20 , H01L21/302
CPC分类号： H01L21/28132 , H01L21/0337 , H01L21/0338 , H01L29/66795
摘要： Disclosed is an imaging method for patterning component shapes (e.g., fins, gate electrodes, etc.) into a substrate. By conducting a trim step prior to performing either an additive or subtractive sidewall image transfer process, the method avoids the formation of a loop pattern in a hard mask and, thus, avoids a post-SIT process trim step requiring alignment of a trim mask to sub-lithographic features to form a hard mask pattern with the discrete segments. In one embodiment a hard mask is trimmed prior to conducting an additive SIT process so that a loop pattern is not formed. In another embodiment an oxide layer and memory layer that are used to form a mandrel are trimmed prior to the conducting a subtractive SIT process. A mask is then used to protect portions of the mandrel during etch back of the oxide layer so that a loop pattern is not formed.
摘要翻译：公开了一种用于将部件形状（例如散热片，栅电极等）图案化成基板的成像方法。通过在执行加法或减损侧壁图像转移处理之前进行修整步骤，该方法避免了在硬掩模中形成环形图案，并且因此避免了后SIT工艺修整步骤，需要修剪蒙版对准亚光刻特征以形成具有离散片段的硬掩模图案。在一个实施例中，在进行添加SIT处理之前修剪硬掩模，使得不形成环形图案。在另一个实施例中，用于形成心轴的氧化物层和记忆层在进行减法SIT处理之前被修整。然后在氧化层的回蚀刻期间使用掩模来保护心轴的部分，使得不形成环形图案。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式