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1. 发明授权

US06492212B1 Variable threshold voltage double gated transistors and method of fabrication 失效
标题翻译：可变门限电压双门控晶体管及其制造方法
公开(公告)号：US06492212B1
公开(公告)日：2002-12-10
申请号：US09972172
申请日：2001-10-05
申请人： MeiKei Ieong , Edward J. Nowak
发明人： MeiKei Ieong , Edward J. Nowak
IPC分类号： H01L210084
CPC分类号： H01L29/7831 , H01L21/823842 , H01L21/82385 , H01L29/458 , H01L29/4908 , H01L29/66484 , H01L29/66795 , H01L29/785
摘要： The present invention provides a double gate transistor and a method for forming the same that facilitates the formation of different transistors having different threshold voltages. The embodiments of the present invention form transistors having different body widths. By forming double gate transistors with different body widths, the preferred embodiment forms double gate transistors that have different threshold voltages, without adding excessive process complexity. The preferred embodiment of the present invention is implemented using a fin type double gated structure. In a fin type structure, the double gates are formed on each side of the body, with the body being disposed horizontally between the gates.
摘要翻译：本发明提供一种双栅极晶体管及其形成方法，其有助于形成具有不同阈值电压的不同晶体管。本发明的实施例形成具有不同体宽的晶体管。通过形成具有不同体宽度的双栅极晶体管，优选实施例形成具有不同阈值电压的双栅晶体管，而不增加过多的工艺复杂性。本发明的优选实施例使用翅片式双门控结构来实现。在翅片型结构中，双门形成在主体的每一侧上，其中主体被水平地设置在门之间。

2. 发明申请

US20070020867A1 Buried stress isolation for high-performance CMOS technology 失效
标题翻译：埋地应力隔离用于高性能CMOS技术
公开(公告)号：US20070020867A1
公开(公告)日：2007-01-25
申请号：US11183062
申请日：2005-07-15
申请人： MeiKei Ieong , Zhibin Ren , Haizhou Yin
发明人： MeiKei Ieong , Zhibin Ren , Haizhou Yin
IPC分类号： H01L21/336
CPC分类号： H01L29/7846 , H01L21/823807 , H01L21/823878 , H01L21/84 , H01L27/1203 , H01L29/66772 , H01L29/78654 , H01L29/78696
摘要： A field effect transistor (FET) comprises a substrate; a buried oxide (BOX) layer over the substrate; a current channel region over the BOX layer; source/drain regions adjacent to the current channel region; a buried high-stress film in the BOX layer and regions of the substrate, wherein the high-stress film comprises any of a compressive film and a tensile film; an insulating layer covering the buried high-stress film; and a gate electrode over the current channel region, wherein the high-stress film is adapted to create mechanical stress in the current channel region, wherein the high-stress film is adapted to stretch the current channel region in order to create the mechanical stress in the current channel region; wherein the mechanical stress comprises any of compressive stress and tensile stress, and wherein the mechanical stress caused by the high-stress film causes an increased charge carrier mobility in the current channel region.
摘要翻译：场效应晶体管（FET）包括衬底; 在衬底上的掩埋氧化物（BOX）层; BOX层上的当前通道区域; 源极/漏极区域与当前沟道区域相邻; BOX层中的埋置的高应力膜和衬底的区域，其中高应力膜包括任何压缩膜和拉伸膜; 覆盖埋置的高应力膜的绝缘层; 以及在电流通道区域上的栅电极，其中所述高应力膜适于在所述电流通道区域中产生机械应力，其中所述高应力膜适于拉伸所述电流通道区域，以便产生机械应力当前通道区域; 其中机械应力包括任何压缩应力和拉伸应力，并且其中由高应力膜引起的机械应力导致当前通道区域中电荷载流子迁移率增加。

3. 发明授权

US07018891B2 Ultra-thin Si channel CMOS with improved series resistance 有权
标题翻译：超薄Si沟道CMOS，具有改善的串联电阻
公开(公告)号：US07018891B2
公开(公告)日：2006-03-28
申请号：US10735736
申请日：2003-12-16
申请人： Bruce B. Doris , MeiKei Ieong , Thomas S. Kanarsky
发明人： Bruce B. Doris , MeiKei Ieong , Thomas S. Kanarsky
IPC分类号： H01L21/00
CPC分类号： H01L27/1203 , H01L21/823814 , H01L21/84
摘要： Thin silicon channel SOI devices provide the advantage of sharper sub-threshold slope, high mobility, and better short-channel effect control but exhibit a typical disadvantage of increased series resistance. This high series resistance is avoided by using a raised source-drain (RSD), and expanding the source drain on the pFET transistor in the CMOS pair using selective epitaxial Si growth which is decoupled between nFETs and pFETs. By doing so, the series resistance is improved, the extensions are implanted after RSD formation and thus not exposed to the high thermal budget of the RSD process while the pFET and nFET can achieve independent effective offsets.
摘要翻译：薄硅沟道SOI器件具有更清晰的子阈值斜率，高迁移率和更好的短沟道效应控制的优点，但呈现增加串联电阻的典型缺点。通过使用升高的源极 - 漏极（RSD）和使用在nFET和pFET之间去耦合的选择性外延Si生长来扩展CMOS对中的pFET晶体管上的源极漏极来避免该高串联电阻。通过这样做，串联电阻得到改善，扩展在RSD形成后植入，因此不暴露于RSD工艺的高热预算，而pFET和nFET可以实现独立的有效偏移。

4. 发明申请

US20080246090A1 SELF-ALIGNED PLANAR DOUBLE-GATE TRANSISTOR STRUCTURE 有权
标题翻译：自对准平面双栅晶体管结构
公开(公告)号：US20080246090A1
公开(公告)日：2008-10-09
申请号：US12119765
申请日：2008-05-13
申请人： Omer H. Dokumaci , Bruce B. Doris , Kathryn W. Guarini , Suryanarayan G. Hegde , MeiKei Ieong , Erin Catherine Jones
发明人： Omer H. Dokumaci , Bruce B. Doris , Kathryn W. Guarini , Suryanarayan G. Hegde , MeiKei Ieong , Erin Catherine Jones
IPC分类号： H01L27/12
CPC分类号： H01L29/78648 , H01L21/0338 , H01L21/2007 , H01L21/26506 , H01L21/26586 , H01L29/42384
摘要： A double-gate transistor having front (upper) and back gates that are aligned laterally is provided. The double-gate transistor includes a back gate thermal oxide layer below a device layer; a back gate electrode below a back gate thermal oxide layer; a front gate thermal oxide above the device layer; a front gate electrode layer above the front gate thermal oxide and vertically aligned with the back gate electrode; and a transistor body disposed above the back gate thermal oxide layer, symmetric with the first gate. The back gate electrode has a layer of oxide formed below the transistor body and on either side of a central portion of the back gate electrode, thereby positioning the back gate self-aligned with the front gate. The transistor also includes source and drain electrodes on opposite sides of said transistor body.
摘要翻译：提供了具有横向排列的前（上）和后门的双栅极晶体管。双栅晶体管包括在器件层下面的背栅热氧化层; 位于背栅极氧化物层下面的背栅电极; 位于器件层上方的前门热氧化物; 前栅极热氧化物上方的前栅极电极层，并与背栅电极垂直对准; 以及设置在背栅极热氧化物层上方的与第一栅极对称的晶体管体。背栅电极具有形成在晶体管本体下方和在背栅电极的中心部分的任一侧上的氧化物层，从而将后栅极与前栅极自对准。晶体管还包括在所述晶体管体的相对侧上的源极和漏极。

5. 发明授权

US07388259B2 Strained finFET CMOS device structures 有权
标题翻译：应变finFET CMOS器件结构
公开(公告)号：US07388259B2
公开(公告)日：2008-06-17
申请号：US10536483
申请日：2002-11-25
申请人： Bruce B. Doris , Dureseti Chidambarrao , MeiKei Ieong , Jack A. Mandelman
发明人： Bruce B. Doris , Dureseti Chidambarrao , MeiKei Ieong , Jack A. Mandelman
IPC分类号： H01L29/94
CPC分类号： H01L27/1203 , H01L21/84 , H01L29/7843 , H01L29/785
摘要： A semiconductor device structure, includes a PMOS device 200 and an NMOS device 300 disposed on a substrate 1,2, the PMOS device including a compressive layer 6 stressing an active region of the PMOS device, the NMOS device including a tensile layer 9 stressing an active region of the NMOS device, wherein the compressive layer includes a first dielectric material, the tensile layer includes a second dielectric material, and the PMOS and NMOS devices are FinFET devices 200, 300.
摘要翻译：半导体器件结构包括PMOS器件200和设置在衬底1,2上的NMOS器件300，PMOS器件包括压迫PMOS器件的有源区的压缩层6，NMOS器件包括拉伸层9，所述NMOS器件的有源区，其中所述压缩层包括第一介电材料，所述拉伸层包括第二介电材料，并且所述PMOS和NMOS器件为FinFET器件200,300。

6. 发明授权

US07002214B1 Ultra-thin body super-steep retrograde well (SSRW) FET devices 有权
标题翻译：超薄体超陡逆行井（SSRW）FET器件
公开(公告)号：US07002214B1
公开(公告)日：2006-02-21
申请号：US10710736
申请日：2004-07-30
申请人： Diane C. Boyd , Judson R. Holt , MeiKei Ieong , Renee T. Mo , Zhibin Ren , Ghavam G. Shahidi
发明人： Diane C. Boyd , Judson R. Holt , MeiKei Ieong , Renee T. Mo , Zhibin Ren , Ghavam G. Shahidi
IPC分类号： H01L27/12
CPC分类号： H01L27/1203 , H01L21/76283 , H01L21/823892 , H01L21/84 , H01L29/66772 , H01L29/78609 , H01L29/78618 , H01L29/78696
摘要： A method of manufacture of a Super Steep Retrograde Well Field Effect Transistor device starts with an SOI layer formed on a substrate, e.g. a buried oxide layer. Thin the SOI layer to form an ultra-thin SOI layer. Form an isolation trench separating the SOI layer into N and P ground plane regions. Dope the N and P ground plane regions formed from the SOI layer with high levels of N-type and P-type dopant. Form semiconductor channel regions above the N and P ground plane regions. Form FET source and drain regions and gate electrode stacks above the channel regions. Optionally form a diffusion retarding layer between the SOI ground plane regions and the channel regions.
摘要翻译：超陡逆行井场效应晶体管器件的制造方法从形成在衬底上的SOI层开始。掩埋氧化层。使SOI层变薄以形成超薄SOI层。形成将SOI层分离成N和P接地平面区域的隔离沟槽。用高水平的N型和P型掺杂剂掺杂由SOI层形成的N和P接地平面区域。在N和P接地平面区域之上形成半导体沟道区。在沟道区域上方形成FET源极和漏极区域以及栅极电极堆叠。可选地，在SOI接地平面区域和沟道区域之间形成扩散延迟层。

7. 发明授权

US07704839B2 Buried stress isolation for high-performance CMOS technology 失效
标题翻译：埋地应力隔离用于高性能CMOS技术
公开(公告)号：US07704839B2
公开(公告)日：2010-04-27
申请号：US12099195
申请日：2008-04-08
申请人： MeiKei Ieong , Zhibin Ren , Haizhou Yin
发明人： MeiKei Ieong , Zhibin Ren , Haizhou Yin
IPC分类号： H01L21/336
CPC分类号： H01L29/7846 , H01L21/823807 , H01L21/823878 , H01L21/84 , H01L27/1203 , H01L29/66772 , H01L29/78654 , H01L29/78696
摘要： A field effect transistor (FET) comprises a substrate; a buried oxide (BOX) layer over the substrate; a current channel region over the BOX layer; source/drain regions adjacent to the current channel region; a buried high-stress film in the BOX layer and regions of the substrate, wherein the high-stress film comprises any of a compressive film and a tensile film; an insulating layer covering the buried high-stress film; and a gate electrode over the current channel region, wherein the high-stress film is adapted to create mechanical stress in the current channel region, wherein the high-stress film is adapted to stretch the current channel region in order to create the mechanical stress in the current channel region; wherein the mechanical stress comprises any of compressive stress and tensile stress, and wherein the mechanical stress caused by the high-stress film causes an increased charge carrier mobility in the current channel region.
摘要翻译：场效应晶体管（FET）包括衬底; 在衬底上的掩埋氧化物（BOX）层; BOX层上的当前通道区域; 源极/漏极区域与当前沟道区域相邻; BOX层中的埋置的高应力膜和衬底的区域，其中高应力膜包括任何压缩膜和拉伸膜; 覆盖埋置的高应力膜的绝缘层; 以及在电流通道区域上的栅电极，其中所述高应力膜适于在所述电流通道区域中产生机械应力，其中所述高应力膜适于拉伸所述电流通道区域，以便产生机械应力当前通道区域; 其中机械应力包括任何压缩应力和拉伸应力，并且其中由高应力膜引起的机械应力导致当前通道区域中电荷载流子迁移率增加。

8. 发明申请

US20080142852A1 SEMICONDUCTOR DEVICE STRUCTURE WITH ACTIVE REGIONS HAVING DIFFERENT SURFACE DIRECTIONS 审中-公开
标题翻译：具有不同表面方向的主动区域的半导体器件结构
公开(公告)号：US20080142852A1
公开(公告)日：2008-06-19
申请号：US12032913
申请日：2008-02-18
申请人： Bruce B. Doris , Oleg Gluschenkov , MeiKei Ieong , Effendi Leobandung , Huilong Zhu
发明人： Bruce B. Doris , Oleg Gluschenkov , MeiKei Ieong , Effendi Leobandung , Huilong Zhu
IPC分类号： H01L27/092
CPC分类号： H01L29/045 , H01L21/76275 , H01L21/76278 , H01L21/823807 , H01L21/84 , H01L27/1203 , H01L29/7842
摘要： Semiconductor structure and method to simultaneously achieve optimal stress type and current flow for both nFET and pFET devices, and for gates orientated in one direction, are disclosed. One embodiment of the method includes bonding a first wafer having a first surface direction and a first surface orientation atop a second wafer having a different second surface orientation and a different second surface direction; forming an opening through the first wafer to the second wafer; and forming a region in the opening coplanar with a surface of the first wafer, wherein the region has the second surface orientation and the second surface direction. The semiconductor device structure includes at least two active regions having different surface directions, each active region including one of a plurality of nFETs and a plurality of pFETs, and wherein a gate electrode orientation is such that the nFETs and the pFETs are substantially parallel to each other.
摘要翻译：公开了同时实现nFET和pFET器件以及朝向一个方向的栅极的最佳应力类型和电流流动的半导体结构和方法。该方法的一个实施例包括将具有第一表面方向的第一晶片和具有不同的第二表面取向和不同的第二表面方向的第二晶片顶部的第一表面取向接合; 形成通过所述第一晶片的开口到所述第二晶片; 以及在所述开口中形成与所述第一晶片的表面共面的区域，其中所述区域具有第二表面取向和所述第二表面方向。半导体器件结构包括具有不同表面方向的至少两个有源区，每个有源区包括多个nFET和多个pFET中的一个，并且其中栅电极取向使得nFET和pFET基本上平行于每个其他。

9. 发明授权

US07205185B2 Self-aligned planar double-gate process by self-aligned oxidation 有权
标题翻译：自对准平面双栅极工艺通过自对准氧化
公开(公告)号：US07205185B2
公开(公告)日：2007-04-17
申请号：US10663471
申请日：2003-09-15
申请人： Omer H. Dokumaci , Bruce B. Doris , Kathryn W. Guarini , Suryanarayan G. Hegde , MeiKei Ieong , Erin Catherine Jones
发明人： Omer H. Dokumaci , Bruce B. Doris , Kathryn W. Guarini , Suryanarayan G. Hegde , MeiKei Ieong , Erin Catherine Jones
IPC分类号： H01L21/336 , H01L21/8234
CPC分类号： H01L29/78648 , H01L21/0338 , H01L21/2007 , H01L21/26506 , H01L21/26586 , H01L29/42384
摘要： A double-gate transistor has front (upper) and back gates aligned laterally by a process of forming symmetric sidewalls in proximity to the front gate and then oxidizing the back gate electrode at a temperature of at least 1000 degrees for a time sufficient to relieve stress in the structure, the oxide penetrating from the side of the transistor body to thicken the back gate oxide on the outer edges, leaving an effective thickness of gate oxide at the center, aligned with the front gate electrode. Optionally, an angled implant from the sides of an oxide enhancing species encourages relatively thicker oxide in the outer implanted areas and an oxide-retarding implant across the transistor body retards oxidation in the vertical direction, thereby permitting increase of the lateral extent of the oxidation.
摘要翻译：双栅极晶体管具有通过在前栅极附近形成对称侧壁然后在至少1000度的温度下氧化背栅电极足以缓解应力的时间的方法横向排列的前（上）和后门在该结构中，氧化物从晶体管主体的侧面渗透，以增厚外边缘上的背栅氧化层，留下中心的栅极氧化物的有效厚度，与前栅电极对准。任选地，来自氧化物增强物质的侧面的成角度的植入物鼓励外部注入区域中相对较厚的氧化物，并且跨越晶体管体的氧化物延迟植入阻碍垂直方向上的氧化，从而允许增加氧化的横向范围。

10. 发明申请

US20080185658A1 Buried Stress Isolation for High-Performance CMOS Technology 失效
标题翻译：埋地应力隔离用于高性能CMOS技术
公开(公告)号：US20080185658A1
公开(公告)日：2008-08-07
申请号：US12099195
申请日：2008-04-08
申请人： MeiKei Ieong , Zhibin Ren , Haizhou Yin
发明人： MeiKei Ieong , Zhibin Ren , Haizhou Yin
IPC分类号： H01L27/08 , H01L21/8238
CPC分类号： H01L29/7846 , H01L21/823807 , H01L21/823878 , H01L21/84 , H01L27/1203 , H01L29/66772 , H01L29/78654 , H01L29/78696
摘要： A field effect transistor (FET) comprises a substrate; a buried oxide (BOX) layer over the substrate; a current channel region over the BOX layer; source/drain regions adjacent to the current channel region; a buried high-stress film in the BOX layer and regions of the substrate, wherein the high-stress film comprises any of a compressive film and a tensile film; an insulating layer covering the buried high-stress film; and a gate electrode over the current channel region, wherein the high-stress film is adapted to create mechanical stress in the current channel region, wherein the high-stress film is adapted to stretch the current channel region in order to create the mechanical stress in the current channel region; wherein the mechanical stress comprises any of compressive stress and tensile stress, and wherein the mechanical stress caused by the high-stress film causes an increased charge carrier mobility in the current channel region.
摘要翻译：场效应晶体管（FET）包括衬底; 在衬底上的掩埋氧化物（BOX）层; BOX层上的当前通道区域; 源极/漏极区域与当前沟道区域相邻; BOX层中的埋置的高应力膜和衬底的区域，其中高应力膜包括任何压缩膜和拉伸膜; 覆盖埋置的高应力膜的绝缘层; 以及在电流通道区域上的栅电极，其中所述高应力膜适于在所述电流通道区域中产生机械应力，其中所述高应力膜适于拉伸所述电流通道区域，以便产生机械应力当前通道区域; 其中机械应力包括任何压缩应力和拉伸应力，并且其中由高应力膜引起的机械应力导致当前通道区域中电荷载流子迁移率增加。

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