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1. 发明授权

US07418369B2 Method and system for efficient implementation of boolean satisfiability 有权
标题翻译：有效实现布尔可满足性的方法和系统
公开(公告)号：US07418369B2
公开(公告)日：2008-08-26
申请号：US10238125
申请日：2002-09-09
申请人： Matthew Moskewicz , Conor Madigan , Sharad Malik
发明人： Matthew Moskewicz , Conor Madigan , Sharad Malik
IPC分类号： G06F17/11
CPC分类号： G06F17/504
摘要： Disclosed is a complete SAT solver, Chaff, which is one to two orders of magnitude faster than existing SAT solvers. Using the Davis-Putnam (DP) backtrack search strategy, Chaff employs efficient Boolean Constraint Propagation (BCP), termed two literal watching, and a low overhead decision making strategy, termed Variable State Independent Decaying Sum (VSIDS). During BCP, Chaff watches two literals not assigned to zero. The literals can be specifically ordered or randomly selected. VSIDS ranks variables, the highest-ranking literal having the highest counter value, where counter value is incremented by one for each occurrence of a literal in a clause. Periodically, the counters are divided by a constant to favor literals included in recently created conflict clauses. VSIDS can also be used to select watched literals, the literal least likely to be set (i.e., lowest VSIDS rank, or lowest VSIDS rank combined with last decision level) being selected to watch.
摘要翻译：披露了一个完整的SAT求解器，Chaff，比现有的SAT解算器快一到两个数量级。 Chaff采用戴维斯 - 普特南（DP）回溯搜索策略，采用高效的布尔约束传播（BCP），称为两个文字观看，以及称为可变状态独立衰减（VSIDS）的低开销决策策略。在BCP期间，Chaff观察到两个文字未分配到零。文字可以特别订购或随机选择。 VSIDS排列变量，最高排名的文字具有最高的计数器值，其中计数器值在子句中每次出现文字时增加1。定期地，计数器除以常数，以支持最近创建的冲突条款中包括的文字。 VSIDS也可以用于选择观看的文字，被选择观看的文字最少可能设置（即，最低的VSIDS等级或最后的VSIDS等级与最后的决定级别相结合）。

2. 发明申请

US20090307642A1 METHOD AND SYSTEM FOR MODEL-BASED DESIGN AND LAYOUT OF AN INTEGRATED CIRCUIT 有权
标题翻译：用于基于模型的集成电路设计和布局的方法和系统
公开(公告)号：US20090307642A1
公开(公告)日：2009-12-10
申请号：US12133563
申请日：2008-06-05
申请人： Ya-Chieh Lai , Frank E. Gennari , Matthew Moskewicz , Srinivas Doddi , Junjiang Lei , Weiping Fang , Kuanghao Lay
发明人： Ya-Chieh Lai , Frank E. Gennari , Matthew Moskewicz , Srinivas Doddi , Junjiang Lei , Weiping Fang , Kuanghao Lay
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： A approach is described for allowing electronic design, verification, and optimization tools to implement very efficient approaches to allow the tools to directly address the effects of manufacturing processes, e.g., to identify and prevent problems caused by lithography processing. Fast models and pattern checking are employed to integrate lithography and manufacturing aware processes within EDA tools such as routers.
摘要翻译：描述了一种允许电子设计，验证和优化工具实现非常有效的方法以允许工具直接解决制造过程的影响的方法，例如识别和防止由光刻处理引起的问题。采用快速模型和模式检查来集成光刻和制造感知过程，如EDA工具，如路由器。

3. 发明授权

US08381152B2 Method and system for model-based design and layout of an integrated circuit 有权
标题翻译：集成电路基于模型设计和布局的方法和系统
公开(公告)号：US08381152B2
公开(公告)日：2013-02-19
申请号：US12133563
申请日：2008-06-05
申请人： Ya-Chieh Lai , Frank E. Gennari , Matthew Moskewicz , Srinivas Doddi , Junjiang Lei , Weiping Fang , Kuanghao Lay
发明人： Ya-Chieh Lai , Frank E. Gennari , Matthew Moskewicz , Srinivas Doddi , Junjiang Lei , Weiping Fang , Kuanghao Lay
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： A approach is described for allowing electronic design, verification, and optimization tools to implement very efficient approaches to allow the tools to directly address the effects of manufacturing processes, e.g., to identify and prevent problems caused by lithography processing. Fast models and pattern checking are employed to integrate lithography and manufacturing aware processes within EDA tools such as routers.
摘要翻译：描述了一种允许电子设计，验证和优化工具实现非常有效的方法以允许工具直接解决制造过程的影响的方法，例如识别和防止由光刻处理引起的问题。采用快速模型和模式检查来集成光刻和制造感知过程，如EDA工具，如路由器。

4. 发明授权

US08645887B2 Method and system for model-based design and layout of an integrated circuit 有权
公开(公告)号：US08645887B2
公开(公告)日：2014-02-04
申请号：US13535242
申请日：2012-06-27
申请人： Ya-Chieh Lai , Frank E. Gennari , Matthew Moskewicz , Srinivas Doddi , Junjiang Lei , Weiping Fang , Kuanghao Lay
发明人： Ya-Chieh Lai , Frank E. Gennari , Matthew Moskewicz , Srinivas Doddi , Junjiang Lei , Weiping Fang , Kuanghao Lay
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： A approach is described for allowing electronic design, verification, and optimization tools to implement very efficient approaches to allow the tools to directly address the effects of manufacturing processes, e.g., to identify and prevent problems caused by lithography processing. Fast models and pattern checking are employed to integrate lithography and manufacturing aware processes within EDA tools such as routers.

5. 发明申请

US20120272201A1 METHOD AND SYSTEM FOR MODEL-BASED DESIGN AND LAYOUT OF AN INTEGRATED CIRCUIT 有权
公开(公告)号：US20120272201A1
公开(公告)日：2012-10-25
申请号：US13535242
申请日：2012-06-27
申请人： Ya-Chieh Lai , Frank Gennari , Matthew Moskewicz , Srinivas Doddi , Junjiang Lei , Weiping Fang , Kuanghao Lay
发明人： Ya-Chieh Lai , Frank Gennari , Matthew Moskewicz , Srinivas Doddi , Junjiang Lei , Weiping Fang , Kuanghao Lay
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： A approach is described for allowing electronic design, verification, and optimization tools to implement very efficient approaches to allow the tools to directly address the effects of manufacturing processes, e.g., to identify and prevent problems caused by lithography processing. Fast models and pattern checking are employed to integrate lithography and manufacturing aware processes within EDA tools such as routers.

6. 发明申请

US20100064269A1 METHOD AND SYSTEM FOR DESIGN RULE CHECKING ENHANCED WITH PATTERN MATCHING 有权
标题翻译：用于图案匹配的设计规则检查方法与系统
公开(公告)号：US20100064269A1
公开(公告)日：2010-03-11
申请号：US12208167
申请日：2008-09-10
申请人： Ya-Chieh Lai , Matthew Moskewicz , Frank Gennari
发明人： Ya-Chieh Lai , Matthew Moskewicz , Frank Gennari
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： According to various embodiments of the invention, systems and methods for design rule checking enhanced with pattern matching is provided, wherein the design rule checker ignores certain patterns of the layout that violate design rules during validation. One embodiment of the invention includes receiving a first layout pattern that containing the original layout of an integrated circuit pattern. The pattern matcher processes the layout pattern and designates certain patterns of the integrated circuit pattern that meet a design waiver. The pattern matcher generates a second layout pattern with the waived patterns marked. The design rule checker subsequently processes the marked layout pattern and validates all but the marked patterns of the second layout pattern against a set of specified design rules. The design rule checker generates a third layout pattern with only the unmarked patterns of the layout being validated against the set of specified design rules.
摘要翻译：根据本发明的各种实施例，提供了通过模式匹配增强的用于设计规则检查的系统和方法，其中设计规则检查器忽略在验证期间违反设计规则的布局的某些模式。本发明的一个实施例包括接收包含集成电路图案的原始布局的第一布局图案。模式匹配器处理布局模式并指定满足设计豁免的集成电路图案的某些模式。模式匹配器生成第二个布局模式，并标记放弃的模式。设计规则检查器随后处理标记的布局图案，并根据一组指定的设计规则验证除了第二布局图案的标记图案之外的所有图案。设计规则检查器生成第三个布局模式，只有布局的未标记模式根据指定的设计规则进行验证。

7. 发明授权

US08677301B2 Method and system for model-based design and layout of an integrated circuit 有权
标题翻译：集成电路基于模型设计和布局的方法和系统
公开(公告)号：US08677301B2
公开(公告)日：2014-03-18
申请号：US13535225
申请日：2012-06-27
申请人： Ya-Chieh Lai , Frank Gennari , Matthew Moskewicz , Srinivas Doddi , Junjiang Lei , Weiping Fang , Kuanghao Lay
发明人： Ya-Chieh Lai , Frank Gennari , Matthew Moskewicz , Srinivas Doddi , Junjiang Lei , Weiping Fang , Kuanghao Lay
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： A approach is described for allowing electronic design, verification, and optimization tools to implement very efficient approaches to allow the tools to directly address the effects of manufacturing processes, e.g., to identify and prevent problems caused by lithography processing. Fast models and pattern checking are employed to integrate lithography and manufacturing aware processes within EDA tools such as routers.
摘要翻译：描述了一种允许电子设计，验证和优化工具实现非常有效的方法以允许工具直接解决制造过程的影响的方法，例如识别和防止由光刻处理引起的问题。采用快速模型和模式检查来集成光刻和制造感知过程，如EDA工具，如路由器。

8. 发明申请

US20120272200A1 METHOD AND SYSTEM FOR MODEL-BASED DESIGN AND LAYOUT OF AN INTEGRATED CIRCUIT 有权
标题翻译：用于基于模型的集成电路设计和布局的方法和系统
公开(公告)号：US20120272200A1
公开(公告)日：2012-10-25
申请号：US13535225
申请日：2012-06-27
申请人： Ya-Chieh Lai , Frank E. Gennari , Matthew Moskewicz , Srinivas Doddi , Junjiang Lei , Weiping Fang , Kuanghao Lay
发明人： Ya-Chieh Lai , Frank E. Gennari , Matthew Moskewicz , Srinivas Doddi , Junjiang Lei , Weiping Fang , Kuanghao Lay
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： A approach is described for allowing electronic design, verification, and optimization tools to implement very efficient approaches to allow the tools to directly address the effects of manufacturing processes, e.g., to identify and prevent problems caused by lithography processing. Fast models and pattern checking are employed to integrate lithography and manufacturing aware processes within EDA tools such as routers.
摘要翻译：描述了一种允许电子设计，验证和优化工具实现非常有效的方法以允许工具直接解决制造过程的影响的方法，例如识别和防止由光刻处理引起的问题。采用快速模型和模式检查来集成光刻和制造感知过程，如EDA工具，如路由器。

9. 发明授权

US08086981B2 Method and system for design rule checking enhanced with pattern matching 有权
标题翻译：通过模式匹配增强设计规则检查的方法和系统
公开(公告)号：US08086981B2
公开(公告)日：2011-12-27
申请号：US12208167
申请日：2008-09-10
申请人： Ya-Chieh Lai , Matthew Moskewicz , Frank Gennari
发明人： Ya-Chieh Lai , Matthew Moskewicz , Frank Gennari
IPC分类号： G06F17/50 , G06F9/455
CPC分类号： G06F17/5081
摘要： According to various embodiments of the invention, systems and methods for design rule checking enhanced with pattern matching is provided, wherein the design rule checker ignores certain patterns of the layout that violate design rules during validation. One embodiment of the invention includes receiving a first layout pattern that containing the original layout of an integrated circuit pattern. The pattern matcher processes the layout pattern and designates certain patterns of the integrated circuit pattern that meet a design waiver. The pattern matcher generates a second layout pattern with the waived patterns marked. The design rule checker subsequently processes the marked layout pattern and validates all but the marked patterns of the second layout pattern against a set of specified design rules. The design rule checker generates a third layout pattern with only the unmarked patterns of the layout being validated against the set of specified design rules.
摘要翻译：根据本发明的各种实施例，提供了通过模式匹配增强的用于设计规则检查的系统和方法，其中设计规则检查器忽略在验证期间违反设计规则的布局的某些模式。本发明的一个实施例包括接收包含集成电路图案的原始布局的第一布局图案。模式匹配器处理布局模式并指定满足设计豁免的集成电路图案的某些模式。模式匹配器生成第二个布局模式，并标记放弃的模式。设计规则检查器随后处理标记的布局图案，并根据一组指定的设计规则验证除了第二布局图案的标记图案之外的所有图案。设计规则检查器生成第三个布局模式，只有布局的未标记模式根据指定的设计规则进行验证。

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