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1. 发明授权

US5766498A Anisotropic etching method and apparatus 失效
公开(公告)号：US5766498A
公开(公告)日：1998-06-16
申请号：US623737
申请日：1996-03-29
申请人： Masayuki Kojima , Yoshikazu Ito , Kazushi Tomita , Shigeki Tozawa , Shunichi Iimuro , Masashi Arasawa , Eiichi Nishimura
发明人： Masayuki Kojima , Yoshikazu Ito , Kazushi Tomita , Shigeki Tozawa , Shunichi Iimuro , Masashi Arasawa , Eiichi Nishimura
IPC分类号： C23F4/00 , H01J37/32 , H01L21/302 , H01L21/3065
CPC分类号： H01J37/32009 , H01J37/3244 , H01J37/32522 , H01J37/32532 , H01J37/32541 , H01J37/32724 , H01J2237/3345
摘要： A parallel-plate plasma etching apparatus includes a susceptor electrode and a shower electrode which are arranged in a process chamber. A semiconductor wafer is placed on the susceptor electrode. A shower region defined by a plurality of process gas supply holes is formed in the shower electrode. The shower electrode is cooled by a cooling block and causes an effective electrode portion of the shower electrode to have a temperature gradient such that a temperature at the central portion of the effective electrode portion is lower than a temperature at the peripheral portion of the effective electrode portion. The diameter of the shower region is selected to be smaller than the diameter of the wafer by 5 to 25% such that degradation of planar uniformity of a degree of etching anisotropy on the wafer caused by the temperature gradient of the effective electrode portion is compensated for. The diameter of the effective electrode portion is selected to be larger than the size of a wafer by 5 to 35% such that a taper angle of a side wall to be etched formed by etching is set to be 85.degree. to 90.degree..

2. 发明授权

US5445709A Anisotropic etching method and apparatus 失效
标题翻译：各向异性蚀刻方法和装置
公开(公告)号：US5445709A
公开(公告)日：1995-08-29
申请号：US154566
申请日：1993-11-19
申请人： Masayuki Kojima , Yoshikazu Ito , Kazuhsi Tomita , Shigeki Tozawa , Shunichi Iimuro , Masashi Arasawa , Eiichi Nishimura
发明人： Masayuki Kojima , Yoshikazu Ito , Kazuhsi Tomita , Shigeki Tozawa , Shunichi Iimuro , Masashi Arasawa , Eiichi Nishimura
IPC分类号： C23F4/00 , H01J37/32 , H01L21/302 , H01L21/3065 , H01L21/06
CPC分类号： H01J37/32009 , H01J37/3244 , H01J37/32522 , H01J37/32532 , H01J37/32541 , H01J37/32724 , H01J2237/3345
摘要： A parallel-plate plasma etching apparatus includes a susceptor electrode and a shower electrode which are arranged in a process chamber. A semiconductor wafer is placed on the susceptor electrode. A shower region defined by a plurality of process gas supply holes is formed in the shower electrode. The shower electrode is cooled by a cooling block and causes an effective electrode portion of the shower electrode to have a temperature gradient such that a temperature at the central portion of the effective electrode portion is lower than a temperature at the peripheral portion of the effective electrode portion. The diameter of the shower region is selected to be smaller than the diameter of the wafer by 5 to 25% such that degradation of planar uniformity of a degree of etching anisotropy on the wafer caused by the temperature gradient of the effective electrode portion is compensated for. The diameter of the effective electrode portion is selected to be larger than the size of a wafer by 5 to 35% such that a taper angle of a side wall to be etched formed by etching is set to be 85.degree. to 90.degree..
摘要翻译：平行板等离子体蚀刻装置包括布置在处理室中的基座电极和淋浴电极。将半导体晶片放置在基座电极上。在淋浴电极中形成由多个处理气体供给孔限定的淋浴区域。淋浴电极被冷却块冷却，使淋浴电极的有效电极部分具有温度梯度，使得有效电极部分的中心部分的温度低于有效电极周边部分的温度一部分。淋浴区域的直径被选择为小于晶片的直径5至25％，使得由有效电极部分的温度梯度引起的晶片上的蚀刻各向异性程度的平面均匀度的降低被补偿。选择有效电极部分的直径大于晶片的尺寸5至35％，使得通过蚀刻形成的待蚀刻侧壁的锥角设定为85°至90°。

3. 发明授权

US5423936A Plasma etching system 失效
标题翻译：等离子体蚀刻系统
公开(公告)号：US5423936A
公开(公告)日：1995-06-13
申请号：US138039
申请日：1993-10-19
申请人： Kazushi Tomita , Yoshikazu Ito , Motohiro Hirano , Akira Nozawa , Hiromitsu Matsuo , Shunichi Iimuro , Shigeki Tozawa , Yutaka Miura
发明人： Kazushi Tomita , Yoshikazu Ito , Motohiro Hirano , Akira Nozawa , Hiromitsu Matsuo , Shunichi Iimuro , Shigeki Tozawa , Yutaka Miura
IPC分类号： H01J37/32 , H01L21/00
CPC分类号： H01J37/32449 , H01J37/3244 , H01J37/32532 , H01J37/32724 , H01J2237/3347
摘要： The present invention provides a plasma etching system, comprising a process chamber enclosing a plasma, means for evacuating said process chamber, a chuck electrode for supporting a substrate, a shower electrode positioned to face said chuck electrode and provided with a large number of small holes, a power source for applying a plasma voltage between the chuck electrode and said shower electrode, gas supply means communicating with said small holes of the shower electrode for supplying a plasma-forming gas into the process chamber through the small holes, and means for controlling said gas supply means such that said plasma-forming gas flows through said small holes at a mass flow rate of at least 620 kg/m.sup.2 /hr.
摘要翻译：本发明提供了一种等离子体蚀刻系统，其包括封装等离子体的处理室，用于抽出处理室的装置，用于支撑基板的卡盘电极，与所述卡盘电极相对设置并设有大量小孔的喷淋电极用于在所述卡盘电极和所述淋浴电极之间施加等离子体电压的电源，与所述淋浴电极的所述小孔连通的气体供给装置，用于通过所述小孔将等离子体形成气体供给到所述处理室，以及用于控制所述气体供给装置使得所述等离子体形成气体以至少620kg / m 2 / hr的质量流量流过所述小孔。

4. 发明授权

US5593540A Plasma etching system and plasma etching method 失效
标题翻译：等离子体蚀刻系统和等离子体蚀刻方法
公开(公告)号：US5593540A
公开(公告)日：1997-01-14
申请号：US429648
申请日：1995-04-27
申请人： Kazushi Tomita , Yoshikazu Ito , Motohiro Hirano , Akira Nozawa , Hiromitsu Matsuo , Shunichi Iimuro , Shigeki Tozawa , Yutaka Miura
发明人： Kazushi Tomita , Yoshikazu Ito , Motohiro Hirano , Akira Nozawa , Hiromitsu Matsuo , Shunichi Iimuro , Shigeki Tozawa , Yutaka Miura
IPC分类号： H01J37/32 , B44C1/22
CPC分类号： H01J37/32449 , H01J37/3244 , H01J37/32532 , H01J37/32724 , H01J2237/3347
摘要： The present invention provides a plasma etching system, comprising a process chamber enclosing a plasma, means for evacuating said process chamber, a chuck electrode for supporting a substrate, a shower electrode positioned to face said chuck electrode and provided with a large number of small holes, a power source for applying a plasma voltage between the chuck electrode and said shower electrode, gas supply means communicating with said small holes of the shower electrode for supplying a plasma-forming gas into the process chamber through the small holes, and means for controlling said gas supply means such that said plasma-forming gas flows through said small holes at a mass flow rate of at least 620 kg/m.sup.2 /hr.
摘要翻译：本发明提供了一种等离子体蚀刻系统，其包括封装等离子体的处理室，用于抽出处理室的装置，用于支撑基板的卡盘电极，与所述卡盘电极相对设置并设有大量小孔的喷淋电极用于在所述卡盘电极和所述淋浴电极之间施加等离子体电压的电源，与所述淋浴电极的所述小孔连通的气体供给装置，用于通过所述小孔将等离子体形成气体供给到所述处理室，以及用于控制所述气体供给装置使得所述等离子体形成气体以至少620kg / m 2 / hr的质量流量流过所述小孔。

5. 发明授权

US08991333B2 Substrate processing method and system 有权
公开(公告)号：US08991333B2
公开(公告)日：2015-03-31
申请号：US13292518
申请日：2011-11-09
申请人： Shigeki Tozawa
发明人： Shigeki Tozawa
IPC分类号： C23C16/30 , C23C16/56 , C23C16/44 , C23C16/52 , H01L21/02 , H01L21/67 , H01L21/768
CPC分类号： H01L21/02063 , H01L21/67173 , H01L21/6719 , H01L21/67201 , H01L21/76897
摘要： A substrate processing method includes a first step of subjecting a target substrate to a gas process within an atmosphere containing a fluorine-containing process gas, thereby forming a fluorine-containing reaction product on a surface of the target substrate. The method further includes a second step of subjecting the target substrate treated by the gas process to a heating process and a gas process within an atmosphere containing a reactive gas that reacts with fluorine.

6. 发明授权

US08956546B2 Substrate processing method and substrate processing apparatus 有权
标题翻译：基板处理方法和基板处理装置
公开(公告)号：US08956546B2
公开(公告)日：2015-02-17
申请号：US13813663
申请日：2011-08-02
申请人： Hajime Ugajin , Shigeki Tozawa
发明人： Hajime Ugajin , Shigeki Tozawa
IPC分类号： B44C1/22 , H01L21/302 , H01L21/311 , H01L21/67 , H01L21/677 , H01L21/762 , H01L27/115 , H01L29/66
CPC分类号： H01L21/302 , H01L21/31116 , H01L21/67069 , H01L21/67201 , H01L21/67745 , H01L21/76224 , H01L21/76283 , H01L27/11521 , H01L29/66825 , H01L29/66833
摘要： A substrate processing method for removing an Si-based film on a surface of a substrate accommodated in a processing chamber includes a first step in which the Si-based film on the surface of the substrate is transformed into a reaction product by a gas containing a halogen element and an alkaline gas in the processing chamber and a second step in which the reaction product is vaporized in the processing chamber which is depressurized to a pressure lower than a pressure during the first step. The first step and the second step are repeated two or more times.
摘要翻译：用于在容纳在处理室中的基板的表面上除去Si基膜的基板处理方法包括第一步骤，其中基板表面上的Si基膜通过含有卤素元素和碱性气体，第二步骤，其中反应产物在处理室中蒸发，该处理室被减压到比第一步骤期间的压力低的压力。第一步和第二步重复两次或更多次。

7. 发明申请

US20130130499A1 SUBSTRATE PROCESSING METHOD AND SUBSTRATE PROCESSING APPARATUS 有权
标题翻译：基板加工方法和基板加工装置
公开(公告)号：US20130130499A1
公开(公告)日：2013-05-23
申请号：US13813663
申请日：2011-08-02
申请人： Hajime Ugajin , Shigeki Tozawa
发明人： Hajime Ugajin , Shigeki Tozawa
IPC分类号： H01L21/302
CPC分类号： H01L21/302 , H01L21/31116 , H01L21/67069 , H01L21/67201 , H01L21/67745 , H01L21/76224 , H01L21/76283 , H01L27/11521 , H01L29/66825 , H01L29/66833
摘要： A substrate processing method for removing an Si-based film on a surface of a substrate accommodated in a processing chamber includes a first step in which the Si-based film on the surface of the substrate is transformed into a reaction product by a gas containing a halogen element and an alkaline gas in the processing chamber and a second step in which the reaction product is vaporized in the processing chamber which is depressurized to a pressure lower than a pressure during the first step. The first step and the second step are repeated two or more times.
摘要翻译：用于在容纳在处理室中的基板的表面上除去Si基膜的基板处理方法包括第一步骤，其中基板表面上的Si基膜通过含有卤素元素和碱性气体，第二步骤，其中反应产物在处理室中蒸发，该处理室被减压到比第一步骤期间的压力低的压力。第一步和第二步重复两次或更多次。

8. 发明申请

US20090242129A1 THERMAL PROCESSING APPARATUS AND PROCESSING SYSTEM 审中-公开
标题翻译：热处理设备和加工系统
公开(公告)号：US20090242129A1
公开(公告)日：2009-10-01
申请号：US12409664
申请日：2009-03-24
申请人： Tadashi Onishi , Shigeki Tozawa , Yusuke Muraki , Takafumi Nitoh
发明人： Tadashi Onishi , Shigeki Tozawa , Yusuke Muraki , Takafumi Nitoh
IPC分类号： B44C1/22 , C23C16/46
CPC分类号： H01L21/67069 , H01L21/31116 , H01L21/67109
摘要： A heat treatment apparatus for heat-treating a silicon substrate includes a mounting table for mounting and heating the silicon substrate thereon, wherein a cover made of any of silicon, silicon carbide, and aluminum nitride is placed on an upper surface of the mounting table. By covering the upper surface of the mounting table by the cover made of silicon or the like, metal contamination of the lower surface of the silicon substrate is suppressed.
摘要翻译：用于热处理硅衬底的热处理设备包括用于在其上安装和加热硅衬底的安装台，其中由硅，碳化硅和氮化铝中的任何一个制成的盖子被放置在安装台的上表面上。通过用硅等覆盖安装台的上表面，抑制了硅衬底的下表面的金属污染。

9. 发明授权

US5578164A Plasma processing apparatus and method 失效
标题翻译：等离子体处理装置及方法
公开(公告)号：US5578164A
公开(公告)日：1996-11-26
申请号：US363270
申请日：1994-12-23
申请人： Yoichi Kurono , Shigeki Tozawa , Shozo Hosoda
发明人： Yoichi Kurono , Shigeki Tozawa , Shozo Hosoda
IPC分类号： H01J37/32 , B44C1/22
CPC分类号： H01J37/32623 , H01J37/32633
摘要： An apparatus for subjecting a semiconductor wafer having an uncovered marginal portion, from which a photoresist film is removed, to an anisotropic etching. The apparatus comprises a process chamber which can be set to a vacuum. Upper and lower electrodes opposite to each other are provided in the process chamber. An etching gas is made into plasma between these electrodes. An electrostatic chuck is arranged on the lower electrode. A wafer is mounted on the electrostatic chuck. A ring made of dielectric material, movable upward and downward, is arranged between the electrodes. A central portion of the ring is formed as a hood having a recessed shape corresponding to the marginal portion of the wafer. During the etching, the hood covers the marginal portion of the wafer under a plasma sheath, so as to be out of contact with the wafer, thereby preventing the marginal portion of the wafer from being etched.
摘要翻译：一种用于对具有未被覆盖的边缘部分的半导体晶片（其中除去光致抗蚀剂膜）进行各向异性蚀刻的设备。该装置包括可设置为真空的处理室。在处理室中设置彼此相对的上下电极。蚀刻气体在这些电极之间被制成等离子体。下电极上设有静电吸盘。将晶片安装在静电卡盘上。由电介质材料制成的可上下移动的环设置在电极之间。环的中心部分形成为具有对应于晶片的边缘部分的凹形的罩。在蚀刻期间，罩覆盖等离子体护套下的晶片的边缘部分，以便与晶片脱离接触，从而防止晶片的边缘部分被蚀刻。

10. 发明授权

US09105586B2 Etching of silicon oxide film 有权
标题翻译：刻蚀氧化硅膜
公开(公告)号：US09105586B2
公开(公告)日：2015-08-11
申请号：US12078958
申请日：2008-04-08
申请人： Shigeki Tozawa , Yusuke Muraki
发明人： Shigeki Tozawa , Yusuke Muraki
IPC分类号： H01L21/306 , H01L21/311 , H01L21/67
CPC分类号： H01L21/31138 , H01L21/67069 , H01L21/67155
摘要： An etching method includes preparing a target object such that a first oxide film made of silicon oxide containing at least one of B and P is formed on a substrate, a second oxide film made of silicon oxide containing neither of B and P is formed on the first oxide film, and a contact portion is present below an interface between the first oxide film and the second oxide film. The etching method further includes etching the second oxide film and the first oxide film, thereby forming a hole reaching the contact portion, and etching the first oxide film by a dry process using a gas containing HF, thereby expanding a portion of the hole adjacent to an upper side of the contact portion and inside the first oxide film.
摘要翻译：蚀刻方法包括制备目标物体，使得在基板上形成由含有B和P中的至少一个的氧化硅制成的第一氧化物膜，在不含有B和P的氧化硅中形成的第二氧化物膜形成在第一氧化物膜和接触部分存在于第一氧化物膜和第二氧化物膜之间的界面之下。蚀刻方法还包括蚀刻第二氧化物膜和第一氧化物膜，从而形成到达接触部分的孔，并且通过使用含有HF的气体的干法来蚀刻第一氧化物膜，从而使孔的一部分与接触部分的上侧和第一氧化膜内部。

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