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1. 发明申请

US20110208904A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20110208904A1
公开(公告)日：2011-08-25
申请号：US13099720
申请日：2011-05-03
申请人： Masamichi Fujito , Makoto Mizuno , Takahiro Yokoyama , Kenji Kawada , Takashi Iwase , Yasunobu Aoki , Takashi Kurafuji , Tomohiro Uchiyama , Shuichi Sato , Yuji Uji
发明人： Masamichi Fujito , Makoto Mizuno , Takahiro Yokoyama , Kenji Kawada , Takashi Iwase , Yasunobu Aoki , Takashi Kurafuji , Tomohiro Uchiyama , Shuichi Sato , Yuji Uji
IPC分类号： G06F12/00
CPC分类号： G11C7/04 , G11C16/0441 , G11C16/10 , G11C16/28
摘要： The semiconductor device includes a nonvolatile memory, having a memory array containing 1-bit twin cells, each composed of electrically rewritable first and second storage devices, the first and second storage devices holding binary data according to difference of their threshold voltages, and having different retention characteristics depending on difference of the binary data thereof; a read circuit for differentially amplifying complementary data output from the first and second storage devices of the twin cell selected for read, and judging information stored in the twin cell; and a control circuit. Two memory cells constituting a twin cell are arranged to hold different data. Therefore, even when the retention performance of one memory cell deteriorates, the difference between data held by the two memory cells can be maintained. Hence, differential amplification of such difference enables acquisition of proper stored information. Thus, retention performance of an electrically rewritable nonvolatile memory cell is improved.
摘要翻译：半导体器件包括非易失性存储器，具有包含1比特双胞格的存储器阵列，每个存储器阵列由电可重写的第一和第二存储器件组成，第一和第二存储器件根据其阈值电压的差异保持二进制数据，并且具有不同的保留特性取决于其二进制数据的差异; 用于差分放大从被选择读取的双胞胎的第一和第二存储装置输出的互补数据的读取电路，以及判断存储在双胞胎中的信息; 和控制电路。布置构成双胞胎的两个存储单元以保存不同的数据。因此，即使一个存储单元的保持性能劣化，也能够维持由两个存储单元保持的数据之间的差异。因此，这种差异的差分放大使得能够获得正确的存储信息。因此，提高了电可重写非易失性存储单元的保持性能。

2. 发明申请

US20100080058A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20100080058A1
公开(公告)日：2010-04-01
申请号：US12630295
申请日：2009-12-03
申请人： Masamichi Fujito , Makoto Mizuno , Takahiro Yokoyama , Kenji Kawada , Takashi Iwase , Yasunobu Aoki , Takashi Kurafuji , Tomohiro Uchiyama , Shuichi Sato , Yuji Uji
发明人： Masamichi Fujito , Makoto Mizuno , Takahiro Yokoyama , Kenji Kawada , Takashi Iwase , Yasunobu Aoki , Takashi Kurafuji , Tomohiro Uchiyama , Shuichi Sato , Yuji Uji
IPC分类号： G11C16/26 , G11C16/04
CPC分类号： G11C7/04 , G11C16/0441 , G11C16/10 , G11C16/28
摘要： The semiconductor device includes a nonvolatile memory, having a memory array containing 1-bit twin cells, each composed of electrically rewritable first and second storage devices, the first and second storage devices holding binary data according to difference of their threshold voltages, and having different retention characteristics depending on difference of the binary data thereof; a read circuit for differentially amplifying complementary data output from the first and second storage devices of the twin cell selected for read, and judging information stored in the twin cell; and a control circuit. Two memory cells constituting a twin cell are arranged to hold different data. Therefore, even when the retention performance of one memory cell deteriorates, the difference between data held by the two memory cells can be maintained. Hence, differential amplification of such difference enables acquisition of proper stored information. Thus, retention performance of an electrically rewritable nonvolatile memory cell is improved.
摘要翻译：半导体器件包括非易失性存储器，具有包含1比特双胞胞的存储器阵列，每个存储器阵列由电可重写的第一和第二存储器件组成，第一和第二存储器件根据其阈值电压的差异保持二进制数据，并具有不同的保留特性取决于其二进制数据的差异; 用于差分放大从被选择读取的双胞胎的第一和第二存储装置输出的互补数据的读取电路，以及判断存储在双胞胎中的信息; 和控制电路。布置构成双胞胎的两个存储单元以保存不同的数据。因此，即使一个存储单元的保持性能劣化，也能够维持由两个存储单元保持的数据之间的差异。因此，这种差异的差分放大使得能够获得正确的存储信息。因此，提高了电可重写非易失性存储单元的保持性能。

3. 发明授权

US07957195B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07957195B2
公开(公告)日：2011-06-07
申请号：US12630295
申请日：2009-12-03
申请人： Masamichi Fujito , Makoto Mizuno , Takahiro Yokoyama , Kenji Kawada , Takashi Iwase , Yasunobu Aoki , Takashi Kurafuji , Tomohiro Uchiyama , Shuichi Sato , Yuji Uji
发明人： Masamichi Fujito , Makoto Mizuno , Takahiro Yokoyama , Kenji Kawada , Takashi Iwase , Yasunobu Aoki , Takashi Kurafuji , Tomohiro Uchiyama , Shuichi Sato , Yuji Uji
IPC分类号： G11C16/00
CPC分类号： G11C7/04 , G11C16/0441 , G11C16/10 , G11C16/28
摘要： The semiconductor device includes a nonvolatile memory, having a memory array containing 1-bit twin cells, each composed of electrically rewritable first and second storage devices, the first and second storage devices holding binary data according to difference of their threshold voltages, and having different retention characteristics depending on difference of the binary data thereof; a read circuit for differentially amplifying complementary data output from the first and second storage devices of the twin cell selected for read, and judging information stored in the twin cell; and a control circuit. Two memory cells constituting a twin cell are arranged to hold different data. Therefore, even when the retention performance of one memory cell deteriorates, the difference between data held by the two memory cells can be maintained. Hence, differential amplification of such difference enables acquisition of proper stored information. Thus, retention performance of an electrically rewritable nonvolatile memory cell is improved.
摘要翻译：半导体器件包括非易失性存储器，具有包含1比特双胞胞的存储器阵列，每个存储器阵列由电可重写的第一和第二存储器件组成，第一和第二存储器件根据其阈值电压的差异保持二进制数据，并具有不同的保留特性取决于其二进制数据的差异; 用于差分放大从被选择读取的双胞胎的第一和第二存储装置输出的互补数据的读取电路，以及判断存储在双胞胎中的信息; 和控制电路。布置构成双胞胎的两个存储单元以保存不同的数据。因此，即使一个存储单元的保持性能劣化，也能够维持由两个存储单元保持的数据之间的差异。因此，这种差异的差分放大使得能够获得正确的存储信息。因此，提高了电可重写非易失性存储单元的保持性能。

4. 发明授权

US08144518B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08144518B2
公开(公告)日：2012-03-27
申请号：US13099720
申请日：2011-05-03
申请人： Masamichi Fujito , Makoto Mizuno , Takahiro Yokoyama , Kenji Kawada , Takashi Iwase , Yasunobu Aoki , Takashi Kurafuji , Tomohiro Uchiyama , Shuichi Sato , Yuji Uji
发明人： Masamichi Fujito , Makoto Mizuno , Takahiro Yokoyama , Kenji Kawada , Takashi Iwase , Yasunobu Aoki , Takashi Kurafuji , Tomohiro Uchiyama , Shuichi Sato , Yuji Uji
IPC分类号： G11C16/00
CPC分类号： G11C7/04 , G11C16/0441 , G11C16/10 , G11C16/28
摘要： The semiconductor device includes a nonvolatile memory, having a memory array containing 1-bit twin cells, each composed of electrically rewritable first and second storage devices, the first and second storage devices holding binary data according to difference of their threshold voltages, and having different retention characteristics depending on difference of the binary data thereof; a read circuit for differentially amplifying complementary data output from the first and second storage devices of the twin cell selected for read, and judging information stored in the twin cell; and a control circuit. Two memory cells constituting a twin cell are arranged to hold different data. Therefore, even when the retention performance of one memory cell deteriorates, the difference between data held by the two memory cells can be maintained. Hence, differential amplification of such difference enables acquisition of proper stored information. Thus, retention performance of an electrically rewritable nonvolatile memory cell is improved.
摘要翻译：半导体器件包括非易失性存储器，具有包含1比特双胞胞的存储器阵列，每个存储器阵列由电可重写的第一和第二存储器件组成，第一和第二存储器件根据其阈值电压的差异保持二进制数据，并具有不同的保留特性取决于其二进制数据的差异; 用于差分放大从被选择读取的双胞胎的第一和第二存储装置输出的互补数据的读取电路，以及判断存储在双胞胎中的信息; 和控制电路。布置构成双胞胎的两个存储单元以保存不同的数据。因此，即使一个存储单元的保持性能劣化，也能够维持由两个存储单元保持的数据之间的差异。因此，这种差异的差分放大使得能够获得正确的存储信息。因此，提高了电可重写非易失性存储单元的保持性能。

5. 发明授权

US07646642B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07646642B2
公开(公告)日：2010-01-12
申请号：US11869144
申请日：2007-10-09
申请人： Masamichi Fujito , Makoto Mizuno , Takahiro Yokoyama , Kenji Kawada , Takashi Iwase , Yasunobu Aoki , Takashi Kurafuji , Tomohiro Uchiyama , Shuichi Sato , Yuji Uji
发明人： Masamichi Fujito , Makoto Mizuno , Takahiro Yokoyama , Kenji Kawada , Takashi Iwase , Yasunobu Aoki , Takashi Kurafuji , Tomohiro Uchiyama , Shuichi Sato , Yuji Uji
IPC分类号： G11C16/00
CPC分类号： G11C7/04 , G11C16/0441 , G11C16/10 , G11C16/28
摘要： The semiconductor device includes a nonvolatile memory, having a memory array containing 1-bit twin cells, each composed of electrically rewritable first and second storage devices, the first and second storage devices holding binary data according to difference of their threshold voltages, and having different retention characteristics depending on difference of the binary data thereof; a read circuit for differentially amplifying complementary data output from the first and second storage devices of the twin cell selected for read, and judging information stored in the twin cell; and a control circuit. Two memory cells constituting a twin cell are arranged to hold different data. Therefore, even when the retention performance of one memory cell deteriorates, the difference between data held by the two memory cells can be maintained. Hence, differential amplification of such difference enables acquisition of proper stored information. Thus, retention performance of an electrically rewritable nonvolatile memory cell is improved.
摘要翻译：半导体器件包括非易失性存储器，具有包含1比特双胞胞的存储器阵列，每个存储器阵列由电可重写的第一和第二存储器件组成，第一和第二存储器件根据其阈值电压的差异保持二进制数据，并具有不同的保留特性取决于其二进制数据的差异; 用于差分放大从被选择读取的双胞胎的第一和第二存储装置输出的互补数据的读取电路，以及判断存储在双胞胎中的信息; 和控制电路。布置构成双胞胎的两个存储单元以保存不同的数据。因此，即使一个存储单元的保持性能劣化，也能够维持由两个存储单元保持的数据之间的差异。因此，这种差异的差分放大使得能够获得正确的存储信息。因此，提高了电可重写非易失性存储单元的保持性能。

6. 发明申请

US20110145521A1 DATA PROCESSING SEMICONDUCTOR DEVICE 有权
标题翻译：数据处理半导体器件
公开(公告)号：US20110145521A1
公开(公告)日：2011-06-16
申请号：US12964803
申请日：2010-12-10
申请人： Yasunobu AOKI , Hideo Kasai , Masamichi Fujito , Junpei Inoue
发明人： Yasunobu AOKI , Hideo Kasai , Masamichi Fujito , Junpei Inoue
IPC分类号： G06F12/00
CPC分类号： G11C7/04 , G11C16/22
摘要： To improve the reliability of controlling overwriting of a nonvolatile memory in a data processing semiconductor device.In a data processing semiconductor device, a control unit which controls reading, writing, or erasing of data in a rewritable nonvolatile memory area has an operation mode that, referring to the input temperature data, controls a temperature range in which writing or erasing of data is performed to be narrower than the temperature range that allows reading of data in the memory area.
摘要翻译：提高在数据处理半导体器件中控制非易失性存储器的重写的可靠性。在数据处理半导体器件中，控制可重写非易失性存储区域中的数据的读取，写入或擦除的控制单元具有操作模式，其参考输入温度数据来控制数据写入或擦除的温度范围被执行为比允许读取存储器区域中的数据的温度范围窄。

7. 发明授权

US08478929B2 Data processing semiconductor device 有权
标题翻译：数据处理半导体器件
公开(公告)号：US08478929B2
公开(公告)日：2013-07-02
申请号：US12964803
申请日：2010-12-10
申请人： Yasunobu Aoki , Hideo Kasai , Masamichi Fujito , Junpei Inoue
发明人： Yasunobu Aoki , Hideo Kasai , Masamichi Fujito , Junpei Inoue
IPC分类号： G06F12/00
CPC分类号： G11C7/04 , G11C16/22
摘要： To improve the reliability of controlling overwriting of a nonvolatile memory in a data processing semiconductor device.In a data processing semiconductor device, a control unit which controls reading, writing, or erasing of data in a rewritable nonvolatile memory area has an operation mode that, referring to the input temperature data, controls a temperature range in which writing or erasing of data is performed to be narrower than the temperature range that allows reading of data in the memory area.
摘要翻译：提高在数据处理半导体器件中控制非易失性存储器的重写的可靠性。在数据处理半导体器件中，控制可重写非易失性存储区域中的数据的读取，写入或擦除的控制单元具有操作模式，其参考输入温度数据来控制数据写入或擦除的温度范围被执行为比允许读取存储器区域中的数据的温度范围窄。

8. 发明申请

US20110288807A1 FAILURE DETECTING METHOD, SEMICONDUCTOR DEVICE, AND MICROCOMPUTER APPLICATION SYSTEM 审中-公开
标题翻译：故障检测方法，半导体器件和微型计算机应用系统
公开(公告)号：US20110288807A1
公开(公告)日：2011-11-24
申请号：US13111942
申请日：2011-05-19
申请人： Takashi Iwase , Masamichi Fujito
发明人： Takashi Iwase , Masamichi Fujito
IPC分类号： G06F19/00 , G01R31/00
CPC分类号： G06F11/0751
摘要： The present invention is directed to improve the precision of failure detection by performing the failure detection by changing an analog amount of a circuit to be subjected to the failure detection. An analog amount of the circuit to be subjected to failure detection is changed under a predetermined condition by a tuning circuit, and a state change in the circuit to be subjected to failure detection based on the change in the analog amount in the circuit to be subjected to failure detection is determined by a failure detection circuit, thereby detecting a failure in the circuit to be subjected to failure detection. In such a manner, without monitoring an output of the failure detection circuit on the outside of a semiconductor device, a failure in the circuit to be subjected to failure detection can be detected. Moreover, an actual state change in the circuit to be subjected to failure detection based on a change in the analog amount in the circuit to be subjected to failure detection is determined by the failure detection circuit, so that precision of failure detection is improved.
摘要翻译：本发明旨在通过改变要进行故障检测的电路的模拟量来执行故障检测来提高故障检测的精度。通过调谐电路在预定条件下改变要进行故障检测的电路的模拟量，并且基于要承受的电路中的模拟量的变化，进行故障检测的电路的状态变化由故障检测电路确定故障检测，从而检测要进行故障检测的电路中的故障。以这种方式，在不监视半导体装置的外部的故障检测电路的输出的情况下，可以检测到要进行故障检测的电路的故障。此外，由故障检测电路确定基于故障检测的电路中的模拟量的变化而要进行故障检测的电路的实际状态变化，从而提高故障检测的精度。

9. 发明申请

US20090254696A1 SEMICONDUCTOR INTEGRATED CIRCUIT AND METHOD OF OPERATION FOR SEMICONDUCTOR INTEGRATED CIRCUIT 审中-公开
标题翻译：半导体集成电路的半导体集成电路及其工作方法
公开(公告)号：US20090254696A1
公开(公告)日：2009-10-08
申请号：US12417704
申请日：2009-04-03
申请人： Hideo KASAI , Masamichi Fujito , Masayuki Hirasawa
发明人： Hideo KASAI , Masamichi Fujito , Masayuki Hirasawa
IPC分类号： G06F12/02
CPC分类号： G11C16/344 , G11C16/0441
摘要： The semiconductor IC has a nonvolatile memory including twin cells, a selector, and a sense circuit. When complementary data are written into a pair of nonvolatile memory cells of each twin cell, the pair of nonvolatile memory cells is set to be in a written state where one cell of the pair is set to one of low and high threshold voltages, and the other is set to the other threshold voltage. When non-complementary data are written into a pair of nonvolatile memory cells, for example, the memory cells both take the low threshold voltage and are made blank. The selector includes switching elements. During the blank-check action, switching elements of the selector are controlled to ON state. Then, the first total current of the twin cells forced to flow into the first input terminal of the sense circuit commonly is compared with the reference signal on the second input terminal, whereby whether the twin cells have been written or blank can be detected at a high speed. As to a semiconductor nonvolatile memory such that complementary data are written into memory cells in memory cell pairs, the blank-check time can be shortened.
摘要翻译：半导体IC具有包括双电池，选择器和感测电路的非易失性存储器。当互补数据被写入每个双胞胎的一对非易失性存储单元中时，该对非易失性存储器单元被设置为写入状态，其中该对中的一个单元被设置为低和高阈值电压之一，并且另一个设置为另一个阈值电压。当非互补数据被写入一对非易失性存储器单元时，例如，存储单元都采用低阈值电压并且变为空白。选择器包括开关元件。在空白检查动作期间，选择器的开关元件被控制为ON状态。然后，强制流入感测电路的第一输入端的双电池单元的第一总电流与第二输入端子上的参考信号进行比较，由此可以在一个高速。对于将互补数据写入存储单元对的存储单元的半导体非易失性存储器，可以缩短空白检查时间。

10. 发明授权

US07072218B2 Semiconductor integrated circuit, semiconductor non-volatile memory, memory card, and microcomputer 有权
标题翻译：半导体集成电路，半导体非易失性存储器，存储卡和微计算机
公开(公告)号：US07072218B2
公开(公告)日：2006-07-04
申请号：US10486638
申请日：2002-07-03
申请人： Masamichi Fujito , Yuko Nakamura , Kazufumi Suzukawa , Toshihiro Tanaka , Yutaka Shinagawa
发明人： Masamichi Fujito , Yuko Nakamura , Kazufumi Suzukawa , Toshihiro Tanaka , Yutaka Shinagawa
IPC分类号： G11C16/04
CPC分类号： G11C7/1057 , G11C7/1051 , G11C7/1096 , G11C7/12 , G11C8/08 , G11C16/08 , H01L2924/0002 , H01L2924/00
摘要： A high voltage output driver derives operational power from high voltages and a switching circuit which reverses the output state of the high voltage output driver. The high voltage output driver has in a current path of the high voltages, a series circuit of a first MOS transistor (M1) and second MOS transistor (M2), with the serial connection node thereof being the driver output terminal. The switching circuit operates to reverse the complementary switching states of the first and second MOS transistors such that one transistor in the on-state is switched to an off-state first and the other transistor is switched to an on-state afterward. Even if the other MOS transistor has its Vds exceeding the minimum breakdown voltage when it operates to turn on, the through current path is already shut off, and therefore the high voltage output driver does not break down.
摘要翻译：高电压输出驱动器从高电压导出工作电源，并切换反向高压输出驱动器的输出状态的开关电路。高压输出驱动器具有高电压的电流路径，第一MOS晶体管（M 1）和第二MOS晶体管（M 2）的串联电路，其串联连接节点是驱动器输出端子。开关电路操作以反转第一和第二MOS晶体管的互补开关状态，使得处于导通状态的一个晶体管首先被切换到截止状态，而另一个晶体管之后被切换到导通状态。即使其他MOS晶体管的Vds在其操作导通时其Vds超过最小击穿电压，直通电流路径已被切断，因此高压输出驱动器不会分解。

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